Getting Started with the Delta Sigma ADC

PSoC 3 / PSoC 5
CE56170
Associated Part Families: CY8C38xx/CY8C55xx
Software: PSoC Creator
Related Hardware: CY8CKIT-001
Author: Praveen Sekar

Project Objective
This code example explains how to configure the delta-sigma ADC present in PSoC 3 / PSoC 5. The various
configuration settings are briefly explained.

Overview
In this project, delta-sigma ADC reads analog input voltage. Firmware translates the ADC output in terms of volt
age and displays it on the LCD.

Component List
Instance Name

Component Name

Component Category

Comments

ADC_Delsig

Delta-sigma ADC

Analog ADC

LCD

Character LCD

Display

Default configuration

Pin_InputSignal

Analog pin

Ports and pins

Default configuration

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Top Design
The following figure illustrates the components and their routing.

The following figure shows pin placement (as in .cydwr file).

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Component Configuration
ADC_DelSig

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Resolution: 16-bit resolution is used

Conversion Mode: Conversion mode is set to Continuous.

Conversion Rate: Conversion rate is set to 2ksps. This is a simple application to display the ADC data
on an LCD. A very high conversion rate is not required.

Input Range: Vssa to Vdda range is selected. The reference voltage for ADC for this input range is
derived from supply voltage (Vdda). ADC internal reference should lie between 0.9 and 1.3 V for proper
operation. To cater to wide supply range (3.3 V and 5 V), ADC module has two resister dividers (Vdda/4
and Vdda/3) to derive internal ADC reference from supply voltage. In PSoC creator, user must specify the
supply voltage in System tab in Design-Wide-Resources (see below). The ADC component automatically
selects the appropriate reference setting based on supply voltage and shows the selected reference in
ADC component configuration window (see above).

For example, when 3.3 V is selected, ADC module uses Vdda/3 (1.1 V) for internal reference. When 5.0 V
is selected, ADC module uses Vdda/4 (1.25 V) for internal reference.
Note:
PSoC3-ES2 silicon and PSoC5 silicon does not have Vdda/3 option to generate internal reference and
hence user should not use 3.3 V for radiometric measurement (Vssa to Vdda reference).

Input mode: Single ended input is selected. It is to be noted that delta-sigma ADC in PSoC3 and PSoC5
device is inherently uses differential input and single ended mode is implemented by internally connecting
the negative input to ground and shifting the sign bit out of the 2s complement number.
The figure below shows the Input-output characteristics of the delta-sigma ADC in Vssa to Vdda input
range. When the ADC input (Vp-Vn) varies from Vdda to +Vdda, the ADC counts linearly increases from
minimum count (0x8000) to maximum count (0x7fff). The single ended mode is implemented by internally
connecting the negative input (Vn) to ground. When that is done, positive input (Vp) can go from 0 to
Vdda restricting the range of ADC input (Vp-Vn) to 0 to Vdda. Hence only the upper half of X-axis is
usable. But, when the device has a negative offset and the positive input (Vp) is 0 V, the ADC output
wrap around. For example, if the negative offset is -1 counts, the ADC output for 0 V will 0xFFFF which
corresponds to most positive input in single ended mode. To prevent this from happening, the user has to
write to the offset correction register. Refer to AN60263 for more details about how to use offset
correction register.
It should be noted that when the user configures the ADC for 16-bit single ended, the output doesnt stop
at 0x7FFF, but goes all the way up to 0xFFFF. For understanding purposes, we can say a 16-bit ADC is
implemented by considering a 17-bit differential ADC and ignoring half the range. (Though the internal
implementation is slightly different from it)

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Differential Input

Single Ended Input

0xFFFF

0x7FFF

-Vdda

Vp-Vn

0x0000

0x0000
+Vdda

Vp-Vn
+Vdda

0xFFFF
0xFFFE
0xFFFD

0x8000

Ideal ADC

Ideal ADC

Negative Offset

Negative Offset

Buffer Mode: The ADC front end buffer is used since high impedance is required. If the user source has
a very low output impedance, user can bypass buffer so that he can get a higher dynamic range. In this
case, rail to rail buffer is used. The input range of this mode is vssa + 100 mV and vdda 250 mV as
specified in the user module datasheet. This doesnt mean that beyond this range the ADC will not
function. The linearity specs in the datasheet are guaranteed only in this range.

For more detailed explanation about the parameter settings, refer ADC_DelSig component datasheet.

Design Wide Resources

This project uses the default configuration. The voltage of operation of the chip should be entered correctly in the
system tab as shown below. The ADC reference in the ADC configuration window is automatically calculated
based on this value.

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Operation
An input voltage in the range of 0(Vss) to VDDA is measured in the ADCs single ended configuration. With the
ADC resolution set to 16 bits, we get output counts from 0 to 65535. The input voltage (0 to VDDA) is given with a
potentiometer connected to P0[2] pin. The raw ADC result is calibrated to obtain input voltage in terms of volt.
Both the raw ADC result and the calibrated value are displayed on character LCD.

Hardware Connections
This project is tested on the CY8CKIT-001 development board. Following are the connections done on the board
to make the project work.

Connect potentiometer output VR (in P14 on DVK) to ADC input pin P0[2] (in P19 on DVK).
Set jumper J11 to ON position to enable power for the potentiometer. Set J12 to ON position to enable
power for character LCD.
Set switch SW3 to 5 V.

For rest of the basic settings of the DVK, refer CY8CKIT-001 PSoC Development Kit Guide.

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Output

Use device selector (Project->Device Selector) window in PSoC Creator to select the appropriate device
and Device Revision. If you are using PSoC3 device (for example, CY8C3866AXI-040) with production
revision, then use the following selection

Similarly, select the appropriate device number to work with PSoC5 Device family
(for example, CY8C5588AXI-060).
Note For engineering samples, device revision is marked on the package as part of the device number.
Production silicon will not have ES marking.
Build the project and program the device.

Vary the potentiometer VR on the DVK and observe the input voltage value and the ADC counts (in hex)
on LCD.
Note:
The delta-Sigma ADC is inherently a differential ADC and single ended mode is implemented by
connecting the negative input to ground. You may observe large count when the input is closer to 0 V due
to offset. Please refer to ADC component configuration section for details.

Suggested Reading

AN60263: Accurate ADC measurement for a detailed description of ADC errors and how ADC is
calibrated for accurate measurements.

EP56203: ADC Channel Scan with Software.

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Document History
Document Title: Getting Started with the Delta Sigma ADC PSoC 3 / PSoC 5
Document Number: 001-56170
Revision

ECN

Orig. of
Change

Submission
Date

Description of Change

**

2765677

PFZ

09/22/09

New example project.

*A

2944344

PFZ

06/07/10

Updated for PSoC Creator Beta 4.1.

*B

3012446

PFZ

08/25/10

Updated for PSoC Creator Beta 5.0.

*C

3101046

PFZ

12/13/10

Changed ADC to Single Sample mode.

Added coherency settings to the code.
Added description to Top Design.

*D

3156348

PFZ

01/27/11

Updated for PSoC Creator 1.0.

*E

3232657

PFZ

04/19/2011

Updated Suggested Reading (changed AN60623 to AN60263).

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