CMOS Digital Intergrated Circuits-Termwork

HighPrecisionOCDM Architecture

1.INTRODUCTION
With the scalingof semiconductor process technology, theperformanceofmodern
VLSIchipsimproves

significantly.Wehaveseen

operatingfrequenciesof

integratedcircuits

reachmulti-gigahertz,resultinginmorerigorous timingrequirements. Timing related defects

originated from manufacturing process-related problems, such as resistive opens and shorts,
metal mousebites, viavoids, etc.,willbecomemorecommon. Consequently,delayfaultscausedby
thesephysical defects,which preventthe circuit from meeting the timing requirements, are
of

growing

concern

in

nanometer

technologies.Moreover,itshouldbenoted

thatthemanufacturingprocessisbecoming
theincreasingcomplexity

moredifficulttobecontrolledwith

ofmodernVLSIchips.

Therefore,electrical

assaturation

parameters,such

current,gatecapacitance,threshold

voltage,etc.,mayvaryfromonedevicetoanother.Asaresult,thedelayof
pathswillhavelargevariationsandcanhardlybepredictedduring
imprecisionofverification

models.

Furthermore,

gatesand

the

timing-critical

designstagedueto

the

thecircuit

timingwouldalsobeby

urgentneed

toconducteffective

theapplicationenvironmentconditionssuchastemperature,
impactedsupplyvoltagenoise,etc.Hence

thereisan

delaytestingforascertainingthecorrectoperationofchips atthe ratedfrequency.

Delay faults are a category

of faults which cause functional chip to fail at

specifiedclockspeedandtheobjectiveofdelayfaulttestinganddebugis
andensurethatthedesignmeets
timingverification

todetecttiming

defects

thedesiredperformancespecifications.Although

andfunctionalsimulation

during

thedesign

cycle

ensurethatachip

meetsitsperformancespecifications,itshouldbenotedthatthesetechniquesareapplied toamodelof
anIntegratedCircuit(IC)andnottoactualsiliconandhencecannotdetect
arecausedbyfactorslikecrosstalkinduceddelay,excessivevoltage

delayfaultswhich
drop

andswing

on

thesupplynets,etc.Additionally,processvariationscanhavea
significantinfluenceonachipsfailuretomeetspecifiedperformance.Process
variations

canresultindistributeddelayfaultsinthechip,

parameter

whichcauseminordelayfaults

onmultiplegatesin agiven path toaccumulateandresultin thepathfailing tomeet performance

Dept.ofECE

Amrita School of Engineering,

Coimbatore

CMOS Digital Intergrated Circuits-Termwork

specifications.

Adding

moredetails

HighPrecisionOCDM Architecture

tomodels

ofanICtoincorporate

thesefactors

willcausecomputational
costsoftimingverificationmethods

tobecome

prohibitive.Diminishingfeaturesizeslimittheobservabilityofchips,makingtestand
debugmoredifficultespeciallyfortimingviolations.Theuseof on-chiptestingcircuitry allowsforatspeedtestingessentialforaccuratedetectionoftimingviolations.
The on-chip path

delay

measurement

techniques have been

gained many

attentionsforresearchersinrecentyears,foritcanprovideacost-effectivealternative
waytoperformdelaydefectdetectionandsilicondebuginmodernVLSI

chips.Valuable

information,which pointstheperformancelimiterandcircuitfailure,canbe obtainedby theonchippathdelaymeasurementtechniquewithamuchhigherconfidence.

Dept.ofECE

Amrita School of Engineering,

Coimbatore

2.COMPARISON WITHRELATED WORKS

Severalarchitectureshavealreadybeenproposedfordelaytestingand
debug.Oneofthosewhicharecloselyrelatedtothisworkis
Line(VDL)techniqueforpath

themodifiedVernierDelay

delaymeasurement.However;theVDLbased

havesomedisadvantages [1].AtypicalVDLis showninFig2.1.

Fig.2.1TypicalVernier Delay Line

Herethemaximumdelaythatcanbemeasuredislimitedton (t d1-td2).

Fig.2.2ModifiedVDL

silicon
techniques

Theauthorsaremotivatedby

thefactthatalthough

VDL-basedtechniquescan

providehighdelaymeasurementresolution,it,however,needslots
largemeasurementrange

[2].Asaresult,thehardwareoverheadsof

considerable.Also,due
theVDLneedsalotof

ofstages

toachievea

thesetechniquesare

tothemanystages,readingoutthemeasurementresultsstoredin
scanclockcycles,thusthewholedelaymeasurementprocessis

time-

consuming.Moreover,thedelaysoftheimportlines,whichareusedforfeedingthe
PUMintothepathdelaymeasurementunit,shouldbetakenintoaccounttoavoidtheloss
precisionfordelaymeasurementof

of

circuitpaths.Inthispaper,itispresentedanon-

chippathdelaymeasurement(OCDM)circuit,inwhichthedelayrangesof

delaystages

areincreasedbyafactor oftwograduallyfrom thelasttothefirstdelaystage.Thetime differenceof

twoinputsignalsinthenextdelaystagereliesonthestoredvalueof
stage.Further,itisproposedadelay

the

calibration

currentdelay

techniquetocalibratethe

delaydifferenceoftheimportlinesforfeedingthePUMintotheOCDMcircuit.The
maincontributions ofthis workcanbelistedinthefollowing:
1)Without decreasingthedelaymeasurement resolution,theproposedapproachcan expanddelay
measurementrangemuch easierwith significantlylesshardwareoverhead comparedtoprevious
VDL-baseddelaymeasurementapproaches.Bykeepingasmall

quantity

ofthedelaystages,theproposedapproachcanalsoachieveshortdelay measurementtime.
2) A calibration circuit and a signal transition converter are incorporated into the proposed
on-chippath

delaymeasurementarchitecture,thereby

providingamoreprecise

andeffectivewayforpathdelaymeasurement.
3)Foreachoftheflip-flopsexistedattheendpoints
added.Thedatainputs

ofthePUMs,a2-to-1multiplexeris

ofthe2-to-1multiplexerareconnectedtothedata-inputanddata-

outputoftheflip-flop,respectively.Bythisway,thedelaydifferenceoftheimportlines,
whichareusedforconnecting

thePUMintothepath

delaymeasurementunit,canbe

calibrated.Henceahighprecisionofpathdelaymeasurementis guaranteed.

3.OCDMCIRCUIT
ThepurposeoftheproposedOCDMcircuitistoreducethenumberofdelay
stagesintheVDL,thustoachieveasignificantlylesshardwareoverheadaswellaslessdelay
measurementtime [3].TheproposedOCDM circuitis shownbelow.

Fig.3.1.ProposedOCDM circuit
3.1 Structureandoperation
ThebasicstructureoftheproposedOCDM circuitisshowninFig.3.1,whichcan
convertthepath delay ofthePUMintoaseriesofdigitalvaluesthatcanbestoredin the
flip-flopsof theVDL chain.EachdelaystageconsistedintheVDL chainisconstructed
byapositiveedgetriggeredD-typeflip-flop,fourmultiplexers,andseveralbuffers.In
theproposedOCDMcircuit,itisassumedthattheinputxisfedbytheoutputofthe
PUM,whiletheinputyisfedbytheinputofthePUM.Soalwaysyswitchesearlierthan
xdoesduringthedelaymeasurementperiod.Inordertoexplaintheoperationof
OCDM circuit,lets considerthecasethatboththeinputandoutputsignalsofthePUM

the

are risingtransitions.
Theupperdelayunit(UDU)refers

tothebuffer

chainthatstarts

attheinputofthe

delaystageatwhichthetransitionsignalispropagatedfromnodey,andendsatthe
inputofthemultiplexerwhoseoutputisconnectedtothedatainputoftheflip-flopin
eachdelaystageof theOCDMcircuit.Thelowerdelayunit(LDU)issimilartoUDU, exceptthat it
startsatthe input

ofthedelaystageat

whichthetransitionsignalis propagatedfromnodex

andendsattheinputof anothermultiplexerwhoseoutputis connectedtotheclockinputoftheflipflopineachdelaystage.Thedelayrangeis

definedasthedelaydifferencebetweenthetwodelayunitsineachdelaystageof
circuit.FromthelaststagetothefirststageoftheOCDM

the

OCDM

circuit,thedelayrange

ofeachstageisincreasedbyafactoroftwo.
Supposetheinputandoutputsignalsof theupperdelaychaininthefirstdelay stage arey1
andy2,respectively,accordingly,x1andx2areassumedforthelowerdelay chain. All flip-flops
ofthe

OCDM

circuit

are

initialized

to

logic

ZERO

values

assertingtheresetsignal.Thedelaymeasurementmodeisactivatedbyassertingthe
signal.Asx1andy1

signals

by
mode

propagatethroughtheirrespectivedelayunits,thetime

differencebetweenthetwo signals willbereduced.

Fig.3.2.Relationshipbetweentimedifferenceoftwoinputsignals andthatoftwo
outputsignals inthefirstdelaystage.
(a)LogicONE intheflip-710flop. (b) Logic ZEROinthe flip-flop.

As

showninFig.3.2(a),assumingthatx1

signallagsthey1signalbyenoughtime

(i.e.,y1switchesmuchearlier),andhencealogic-highvalue

willbeholdintheflip-flop.

Asaresult,y2willbethesignalthatpassesthroughtheUDUandthebufferBUFBin
chainfromy1,whilex2willbethesignal

theupperdelay

thatpassesthrough

andthebufferBUFBinthelowerdelay

theLDU

chainfromx1.Thedelay

ofBUFBislarge

enoughtoensurethatastablelogichighvaluecanbestoredintheflip-flopbeforethe
twotransitionsignalsarriveattheinputs

ofthemultiplexers

whoseoutputs

areconnected

totheinputsofthenextdelaystage.Clearly,thetimedifferencebetweenandisreduced
byanamountwhichequals thedelayrangeofthis delaystage.
ThebuffernamedBUFAineachdelay
thecumulativedelayof

stagehasadelayvaluethatislargerthan

thepaththatcontainsLDUandBUFBof

Likewise,ifthetimedifferenceofy1andx1issmallerthan

thesamedelaystage.
thedelayrange,theflip-flop

willholdlogicZEROvalue.Therefore,thesignalspropagatingthroughBUFA are then selectedby

themultiplexers.Asaresult,thetimedifferencebetweeny2andx2willbe equaltothatofy1andx1,as
showninFig.3.2(b).
Consequently,theprincipleof

theOCDMcircuitis

thatifthetimedifference

betweenthetwoinputsofeachdelaystageislargerthanthedelayrangeofthesame
stage,alogicONEvaluewillbestoredintheflip-flopof
differencebetweenthetwooutputsignals

thedelaystage.Thetime

willbeupdatedbysimply

subtractingthedelay

rangefromthatbetweentheinputsignalsofthedelaystage.Otherwise,theflip-flopof thedelaystage
willholdalogicZEROvalue,andthetimedifferencebetween theoutput signals willkeepthesameas
thatbetweentheinputsignals ofthedelaystage.
Notethatthereexistsasetuptimeinthestoreblockof
inFig.3.1,whichconsistsof

eachdelaystageasshown

aDflip-flopandtwomultiplexers.If

thetimedifference

betweenthetwoinputsof thestoreblockissmallerthanthesetuptime,anerrorlogic value may be

hold in the flip-flop. Therefore, inorder to provide better delay measurementprecision,the
DCUnitcellconstructedby

twobufferlinesisproposedfor

delaycompensation,whichmeansthattheupperandlowerdelayunitsof DCUnitare designedsuch

thatthedelay differencebetween themisapproximatelyequalto thesetup time.

Thevaluesstoredinthedelaylinecanbeshiftedoutseriallyusingtheclock
signalshiftclkintheshiftmodebyde-assertingthemodesignal.Thedelay

ofthePUM

canthenbeobtained.
3.2DelayRangeCalibration
Thedelayrangeof

eachdelaystageintheOCDMcircuitwouldbevarieddueto

theprominentprocessvariations.Itisthusnecessarytocalibratethedelayrangesto
assuretheprecisionofpathdelaymeasurementresultbeforeusingtheOCDMcircuit. Fig.3.3shows
thebasicstructureof

thecalibrationcircuit,whichcanbeembeddedinto

fordelayrangecalibration.Theoutputsofthecalibrationcircuit,

theOCDMcircuit
denotedasy

andx,aredirectlyconnectedtotheinputswiththesamenotationsofthe
OCDMcircuit,respectively.Twoinputs
arefedbytheinputandoutputof

ofthecalibrationcircuit,denotedaspinandpout,
thePUM,respectively.Clearly,whentheCSsignalis

setto1,thegeneratedtransitionsatthey

andxcanbesentintotheOCDMcircuitfor

delaymeasurement.When theCSsignalissetto0,thedelay range calibration processis conducted.

Fig.3.3. Calibrationcircuit

Fig.3.4.Timingwaveformfor calibrationcircuit
Thesimplifiedtimingwaveformforthedelay

rangecalibrationisshownin

the

Fig.3.4.TheFF1andFF2arerisingandfallingedgetriggeredflip-flops respectively. First,theflipflopsof

FF1andFF2areinitiatedwithlogicZERObytheresetsignal.

Then,logicONEwillbeloadedintotheFF1andFF2bytherisingandfallingedgesof
respectively.Clearly,thetimedifferencebetween

theclocksignal

thegeneratedrising

transitionsatyandxisequaltothewidthofthepositivehalfcycleoftheclocksignal.
Thetimeperiodofthe

clocksignalcanbe

programmeddeterministicallywith

high

resolutionusingtheon-chipclockgenerator.
Assumingthenumberof

delaystagesintheOCDMcircuitism.Thefollowing

presentsthecalculationmethodforobtainingthedelayrangeofeachdelaystage,which
describedby Eq.3.1:
a11x1+a12x2++a1mxm =b1
a21x1+a22x2++a2mxm =b2
..
am1x1+am2x2+..+ammxm =bm

..(3.1)

is

Let

Wehave
wherexj(1<=j<=m)

AX=B(3.2)
inthevectorXrepresents

becalculated,bi(1<=I<=m)inthevector

thedelayrangeofthejthdelaystageto

Brepresentsthewidthof

thepositivehalf

cycleofsignalclockfortheithcalibrationprocess,aijinthematrixArepresentsthe
measuredvalue(0or1)forthejth

delaystageduring

appropriate values for vector B in

theithcalibration.Clearly,by

selecting

each calibration process, it is easy

concludethedelayrangeforeachstagebysolvingEq.3.2.
Notethatthevalueofbi inthevectorB,whichisthewidthofthepositivehalf cycle
oftheclocksignal,maynotbeexactlyequal totheexpectedvaluebecauseofthe
clockjitter,andhencemayinduceerrordelay rangesforthedelaystages.However,this
canbecompensatedbymultiplecalibrationsundereachbivaluebecausetheclockjitter is azeromeanrandomvariable. Hencethedelayrangeofeachdelaystagecanbecalibratedby

to

theprocessmentioned above.Thecalibration errorscausedby theclocktuningresolution

andmeasurement resolution aresmallandcanbeignored.They
canalsobecompensatedbymultiple calibrations usingmultiplenumbersofbivalues.

4.PATHDELAYMEASUREMENT
ARCHITECTURE
Thearchitectureoftheproposed pathdelay measurement schemeusing the OCDM
circuitis showninFig.4.1

Fig.4.1.Pathdelaymeasurementarchitecture
TwoM-to-1multiplexersareincludedaimingtoselectaparticularpathintotheOCDM
circuitfordelaymeasurement.
4.1.SignalTransition Conversion(STC)
Asmentionedintheprevioussection,theOCDMcircuitworkswellonlywhen
theinputandoutputof

thePUMarerisingtransitions.However,thereareotherthree

additionalcasespossiblytoactivatetheworstcasedelayofacircuitpath,suchas apath

inwhichtheinputisarisingtransitionandtheoutputisafallingtransition.Itisthus
bettertotransfertheoutputsignalintothesignalwithrisingtransitionforfacilitatingpath
delaymeasurementregardlessof

thetransitiondirectionof

theoriginalsignal.TheSTC

block showninFig.4.2is usedtohandlethis problem.Therefore,risingtransitions which

arederivedfromthestartandendpoints

ofPUMcanbefedintotheinputsyandxoftheOCDM

circuit,respectively.Fig.4.2shows thebasicstructureoftheSTCblock.

Fig.4.2.Signal Transition Converter

Fig.4.3Simplifiedtimingwaveformfor STC
(a)Risingtransitionat IN (b)FallingtransitionatIN
When

thepre-chargesignalislow,denotedasthepre-chargeperiod,both

the

nodesAandBare chargeduptologichighvalues.Hence theOUTsignalkeepsalogic lowvalue.

IfarisingtransitionisgeneratedattheINsignalwhenthepre-chargesignalis
high,boththenodesAandBaredischargedtologiclowvaluesafterthearrivalof the rising transition
ofIN.Therefore,arising

transitionisgeneratedat

theOUTsignal.

Likewise,arising

transitionwouldalsobegeneratedattheOUTsignalafterthearrivalof
afallingtransitionoftheINsignal.Hence,byusingtheSTC,theinputsignalwitharbitrarytransitiondi
rectioncanbeconvertedintoa risingtransitionsignalforfacilitating pathdelaymeasurement.

4.2Delay Measurement
Theproposedon-chipdelaymeasurementflowcanbedividedintoeightstepsas
follows:
1)Selectthepathsfordelaymeasurement;
2)ForeachPUM,theinputandoutputtransitionsignalsofthePUMcanbefedintothe
OCDM circuitfordelaymeasurementbyusingthetwoM-to-1multiplexes;
3)ThefirstvectorofthetestvectorpairforthePUMisappliedtoinitializetheinternal
logicofthecircuittoastablestate;
4)Allflip-flopsoftheOCDMcircuitareinitializedtologicZEROvaluesbyasserting theresetsignal;
5)Thedelaymeasurementmodeis activatedbyassertingthemodesignal;
6)Thesecondvectorofthetestvectorpairisappliedtothecircuit, andhenceatransition
signalcanbelaunchedattheinputofthePUM,andpropagatedtotheoutputofthe
PUM;consequently,thedelaydifferenceofthetwotransitionsignalsismeasuredbythe
OCDM andrecordedinto thedelayline;
7)Afterthecompletion

of

delaymeasurement,theOCDM

circuitisconfiguredintoshift

modebyde-assertingthemodesignal.Therefore,thevaluesstoredinthedelaylinecan
beshiftedoutseriallyusingclocksignalshiftclk.Consequently,thepathdelayofthe
PUMcanbecalculatedfrom

thevaluesreadout.Allpathscanbeselectedfordelay

measurementbyrepeating theabovesteps 27.

Afterthevaluesstoredinthedelaylinehavebeenreadout,thedelayofthePUM
canthenbeobtained.SupposethetotalnumberofdelaystagesintheOCDM

circuitisN,

thedelaymeasurementresolutionoftheOCMDcircuitisMres,whichishalf

ofthedelay

rangeinthelastdelaystage(Dlas),andthevaluesstoredintheflip-flopfrom

thefirst

delaystagetothelastdelaystageoftheOCDMcircuitareDNtoD1,respectively.Then
thepathdelaycanbecalculatedas follows:
N

DelayofMeasurement=

D i2 i1D las
i0

..4.1

ThemaximumdelaymeasurementrangeoftheOCDMcircuitcanalsobeobtainasfollows:
Maximummeasurementrange=

2i-1*Dlas

4.3.DelayCalibrationforImport Lines
InordertoobtainthedelayofthePUMwithhighprecision,thedelayofimport
linesP2andP3forfeedingthestartandendtransitionsof
circuit,asshownintheFig.4.1,shouldbetakenintoaccount.
difficulttomutually

cancel

thePUMintotheOCDM
Thereasonis

thatitis

thedelaysoftheimportlinesP2andP3duringphysical

design.Eventhoughacarefulcustomlayoutcanbeconductedtobalancetheimportlines
P3servingforonePUM,itcanbehardlytosatisfy

thisrestrictionfortheimport

P2and
linesforall

thePUMs.Moreover,thedelaysofimportlinesP2andP3wouldalsobe
affectedbytheprocessvariationsandhencewouldbringaprecisionlossof
measurement.Inordertoaddress thisproblem,a2-to-1multiplexerisaddedfortheflipflopwhichis theendpointofthePUM.

Fig.4.4. Delaycalibrationfor importlines

Fig.4.3redrawsthearchitectureofthepathdelaymeasurementschemeshownin the
Fig.4.1,whichincludes a2-to-1multiplexerwithdatainputs,respectively,connected

thedelay

tothedata-inputanddata-outputof

theflip-flopattheendpointof

thePUMtocalibrate

thedelaydifferenceofimportlines.
Whenthe

MS

signal

isset

to

1,thepathdelay

measurement

configuredintothedelaymeasurementmode.Hencetheinputandoutput

architectureis
ofPUM1are

selectedintotheOCDMfordelaymeasurement.Thedelaymeasurementresultof

PUM1

withoutconsidering thedelay differenceofimportlinesP2andP3canberepresentedas follows:

Delaymeasurementresult=D1+D3-D2
wheretheD1,D2andD3representthedelaysof PUM1,P2,andP3, respectively.
However,inordertoobtainthedelayofthePUMwithhighprecision,thedelayvalueof D3
D2shouldbeobtainedfirstly.ThedelayofP3istypicallylargerthanthatofP2for theinsertionof
amultiplexer.WhentheMSsignalissetto0, theimportlinesdelay differencecalibrationmodeis
configured.

5.ADVANCED WORK
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for
SoC applications[4]
The proposed all-digital OCDM architecture shown in figure 5.1 consistsof two digitally
controlled delay lines (DCDLs), a phase detector, and acontroller. The inputs of digitally
controlled delay lines A and B (DCDL_Aand DCDL_B) are SignalA and SignalB, respectively,
with timingdifference which will be measured. The delay of DCDL_A and DCDL_Bare
controlled by digital control codes DCCA[6:0] and DCCB[6:0],respectively. After SignalA and
SignalB propagate through the DCDLs,the delayed version signals (SignalA_D and SignalB_D)
are sent into thephase detector (PD) which generate the phase comparison results Lead andLag.
In the beginning, DCCA and DCCB are initialized to zero.Subsequently, the phase detector
asserts a digital signal, either Lead orLag, based on the relation of the SignalB_D rising edge to
the SignalA_Drising edge. If the phase detector asserts Lead, the controller incrementsDCCB by
one to enlarge delay of SignalB_D. Conversely, if the phase detector asserts Lag, the controller
increments DCCA by one to enlarge delay of SignalA_D. Phase comparison continues until the
phase detectorsenses a change in the phase polarity of the SignalB_D relative to theSignalA_D.
At this point, DCCA and DCCB will be saved and the delaymeasurement is complete.

Fig.5.1.Advanced OCDM Architecture

6.CONCLUSION
The on-chip path

delay

measurement

techniques have been gained many

attentionsforresearchersinrecentyears,foritcanprovideacost-effectivealternative
waytoperformdelaydefectdetectionandsilicondebuginmodernVLSIchips.Although
basedtechniquescanprovidehighdelaymeasurement

VDL-

resolution,theproposed

architectureinthispaperforon-chipdelaymeasurementiscertainlysuperiortothem
sincethisarchitectureguaranteesahigh

precision

delaymeasurementrangewithasmallquantity

path

delaymeasurementandalarge

ofdelaystages.Thedelaydifferencefor

theimportlinesforfeedingthestartandendtransitionsofthePUMintotheOCDM
circuitisalsoconsideredin

theproposed

precisionforpathdelaymeasurement.

technique,which

canfurtherprovideahigh