Lab Report: EEE 454

Department of EEE

Lab Report: EEE454

VLSI I

BUET

Group No: 06

Lab Number: 04

LAB TITLE: Layout design with Cadence Virtuoso Layout Suite L Editor.

Prepared By:
Student Name: Navid Anjum Aadit
Student ID: 1006057
Name of Group Member: Sayeed Shafayet
Student ID of Group Member: 1006003
Date of Experiment: 11-04-2015
Date of Report : 25-04-2015

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Lab Report: EEE 454

Department of EEE

BUET

ABSTRACT
In this experiment, Cadence Virtuoso Layout Suite L has been used to build the layout view of a
CMOS Inverter with the constraint that it should be of minimum possible size. Then using
Cadence ASSURA the DRC rules have been checked for design errors and using ASSURA LVS
check, layout has been matched with the schematic. The process technology adopted for this
experiment is gpdk090 which is a 90nm technology. The purpose of this experiment was to get
acquainted with the design rules that come into action when minimum size devices are to be
designed.

KEYWORDS
1.
2.
3.
4.
5.

DRC
ASSURA
Layout
Inverter
LVS

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Lab Report: EEE 454

Department of EEE

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TABLE OF CONTENTS
Page
Abstract....2
Keywords..2
Table of Contents......3
List of Figures.......4
List of Tables...4
1. Introduction..........5
2. Theory..5
3. Lab Handout Question ......8
4.
. Tools Used............8
5. Procedure ....8
6. Results ....8
6.1 Layout of the inverter........8
6.2 Errors Received....................9
.
6.3 List of rules.....9
6.4 List of some good practices........10
6.5 LVS Check .......10
7. Conclusion..11
8. References... 11

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Lab Report: EEE 454

Department of EEE

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LIST OF FIGURES
1.
2.
3.
4.
5
6
7.
8.

VLSI Design Flow

CMOS Inverter Schematic
CMOS Inverter Layout
Basic DRC Rules
Layout of CMOS Inverter
Measurement of the area of the inverter
DRC Check
LVS Check

Page
5
6
6
7
8
9
9
10

LIST OF TABLES
No table is used.

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Lab Report: EEE 454

Department of EEE

BUET

INTRODUCTION
This experiment has been designed to create a layout view of the basic inverter circuit from scratch
using Cadence Virtuoso Layout Suite L Editor and to per-form the design rule check of the inverter
using Cadences ASSURA.
The simple CMOS inverter can be considered to be the foundation of every digital electronic device,
from cell phones to satellites to supercomputers. Be-cause the inverter is so important to the
success and advancement of digital electronics, its client layout design is thus of crucial importance
for extensive studying.

THEORY
VLSI Design Process
The VLSI design process goes through the following steps:

Fig No. 1: VLSI Design Flow

Layout Design
Integrated circuit layout is the representation of an integrated circuit in terms of planar geometric
shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the
components of the integrated circuit [1].
When using a standard process the behavior of the final integrated circuit depends largely on the
positions and interconnections of the geometric shapes. While designing a layout all the components
that make up a chip are placed and connected so that they meet performance and size criterion. The
generated layout must pass a series of checks in a process known as physical verification. The most
common checks in this verification process are:
design rule checking (DRC),
layout versus schematic (LVS),
parasitic extraction,
antenna rule checking
Electrical rule checking (ERC) etc.
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Lab Report: EEE 454

Department of EEE

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CMOS Inverter:
The CMOS inverter consists of a PMOS and an NMOS transistor. They must be properly shaped to
account for the fact that holes have lower mobility than electrons. So the PMOS transistor generally has
a larger size and to reduce the undesirable effects due to larger size, twice the no. of contacts in NMOS
are placed in the PMOS.

Fig No. 2: CMOS Inverter Schematic

Fig No. 3: CMOS Inverter Layout

Layout Design Rules

Layout design is performed maintaining some basic rules of dimension and relative positions of various
layers representing oxide, n-well, poly-silicon, and substrate, metal1 and doped regions (Nimp or Pimp).
An inverter consists of a NMOS and a PMOS transistor. According to the gpdk90nm Mixed Signal
Process Specifications, the primary design rules of NMOS and PMOS transistors are as follows:
As seen from the layout diagram the NMOS inverter consists of oxide, Nimp, Cont and poly layers.

NMOS Transistor Design Rules

Contact size: 0.12m x 0.12m (Fixed)
Poly width Minimum: 0.1m (Fixed MOS gate length)
Contact to poly spacing (Minimum): 0.1m
Contact to oxide spacing (Minimum): 0.06m
Poly extending to oxide (Minimum): 0.18m
Nimp overlapping oxide (Minimum): 0.18m
Minimum Metal 1 width: 0.12m
Maximum Metal 1 width: 12.0m
Minimum Metal 1 to Contact enclosure: 0.06m
The PMOS transistor consists of Oxide, Poly, Pimp, Cont and Nwell layer.
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Lab Report: EEE 454

Department of EEE

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PMOS Transistor Design Rules

Minimum Nwell width: 0.6m,
Minimum Nwell spacing to Nwell (same potential): 0.6m
Minimum Nwell spacing to Nwell (different potential): 1.2m
Minimum Nwell spacing to N+ active area: 0.3m
Minimum Nwell spacing to P+ active area: 0.3m
Minimum Nwell enclosure to P+ active area: 0.12m
Minimum Nwell enclosure to N+ active area: 0.12m
Minimum N+ active Area to P+ active Area Spacing: 0.15m
Minimum Contact to Contact spacing 0.14m

Design Rule Check (DRC)

Design Rule Checking (DRC) is the process that determines whether the physical layout of a particular
chip satisfies a series of recommended parameters called Design Rules. Design rule checking also
involves LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna
Checks etc. [2].
Design Rules are a series of parameters provided by semiconductor manufacturers which are specific to
a particular semiconductor manufacturing process. Design rules specify certain geometric and
connectivity restrictions to ensure that the process can fabricate the device properly. The most basic
design rules for one layer are: width, spacing and enclosure.

Fig No. 4: Basic DRC Rule

Layout versus Schematic (LVS) Check

The Layout Versus Schematic (LVS) is the class of verification that determines whether a particular
integrated circuit layout corresponds to the original schematic or circuit diagram of the design. A
successful Design rule check (DRC) ensures that the layout conforms to the rules designed/required for
faultless fabrication. However, it does not guarantee if it really represents the circuit we desire to
fabricate. This is where an LVS check is used.
LVS Checking involves following three steps:
1. Extraction: The software program takes a database file containing all the layers drawn to
represent the circuit during layout.
2. Reduction: During reduction the software combines the extracted components into series and
parallel combinations if possible and generates a netlist representation of the layout database.
3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit
schematic. If the two netlists match, then the circuit passes the LVS check.
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Lab Report: EEE 454

Department of EEE

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LAB HANDOUT QUESTIONS

There was no lab handout questions.

TOOLS USED
1. Cadence Virtuoso Layout Suite L
2. Cadence ASSURA DRC
3. Cadence ASSURA LVS

PROCEDURE
1. Calculated the two dimensional sizes of each layer conforming to the above mentioned design rules.
2. Created each layer using rectangular shape.
3. Created VDD, GND and Vout terminal/pin selecting the Metal1 layer Created Vin pin selecting the
poly layer.
4. Performed DRC rules check by Cadences ASSURA .
5. Corrected the errors and performed DRC rules check until there remained no error.

RESULTS
1. Layout of the CMOS inverter as designed:

Fig. No. 5. Layout of CMOS Inverter

In the above figure,
Poly pink, Metal1- yellow, Nwell green, Cont black, pimp light blue, nimp blue
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Lab Report: EEE 454

Department of EEE

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Size of the Inverter:

The area of the inverter has been found to be 2.0 um x 2.1 um

Fig. No. 6 Measurement of area of the inverter

This might be the achievable minimum size for the inverter which meets the requirements as specified.

2. Errors Received:
After drawing the layout of the inverter and checking the DRC rules for the first time, the following
error message was received:
Metal1 to Metal1 spacing must be 0.18 m
This corresponded to the fact that in our design the extensions of the VDD, GND and Vout pins were
not properly connected to the main metal1 layer, namely the VDD layer, GND layer and the joining of
the two drain regions respectively.
After seeing to these connection errors DRC checking was performed again without any more error
messages implying that the layout design is complete.
After all the errors have been corrected, DRC check yielded the following window:

Fig. No. 7 DRC Check

3. List of rules relevant to the design of CMOS inverter in addition to the rules
mentioned in the theory section:
1. Metal area smaller than .07 are not allowed.
2. Contact on gate is not allowed.
3. Minimum poly to contact enclosure must be 0.04um. Poly to contact enclosure on at least two
opposite sides must be greater than 0.06 um.
4. Poly gates cannot have bends
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5. Contact must be covered by oxide or poly.

6. Nimp or Pimp must have an area greater than 0.15 .
7. Oxide area must be greater than 0.06 .

4. List of some good practices for Inverter layout design:

1. The source diffusion and the drain diffusion should be filled with the maximum number of
contacts to reduce the resistance of the connection from the metal to the diffusion, and to
maximize the amount of current that can flow through the contacts.
2. The substrate and the N-well are doped lightly. A direct connection from the metal routing
layer to the bulk is not allowed. The connection should be made through a higher doped di usion
such as the p-diffusion and the n-diffusion in order to establish a good contact.
3. In some fabrication process, two additional layers are used for these connections. These layers
have much higher doping than the diffusions for the source and the drain.
4. Reducing the parasitic capacitance and resistance would increase the speed of the transistor.
The frequency response of the transistor can be improved if the source capacitance and drain
capacitance are reduced. These can be done by folding the transistor to an even number of
fingers.
5. Using poly for interconnect could degrade the frequency response of the transistor if the poly
routing is not optimized carefully.
6. To reduce substrate coupling noise, one may use guard ring in the following configuration
around critical transistors.
Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground.
Surround PMOS in the N-well with n-tap guard ring that is connected to VDD.
Contact and via should not be placed directly on top of the transistors gate.

5. LVS Check:
The LVS check lead to no error. The output window is shown below:

Fig. No. 8 LVS Check

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CONCLUSION
CMOS inverter is the primary component of modern day integrated circuits including microprocessors,
microcontrollers, static RAM, image sensors, data converters, and some types of transceivers. Thus
the designing of its layout must be done carefully so that not only there are any errors but also its
design should be as compact as possible. This basic building block can be used later in other layout
designs as well.

In this experiment three basic steps of CMOS process flow Layout Design, DRC and LVS checking
have been studied in Cadence. The layout of a basic inverter has been drawn in the Cadence Virtuoso
Layout Suite L for gpdk90nm process parameters. The design rules of the layout have been checked
by the Cadence ASSURA and all the errors have been resolved. And finally, the LVS check has been
performed. Another objective was to obtain minimum possible dimension for the inverter, which, as
we have calculated, has been obtained as instructed. This experiment helped understand the layout
design process rules.

REFERENCES
1. http://en.wikipedia.org/wiki/Integrated_circuit_layout
2. http://en.wikipedia.org/wiki/Design_rule_checking
3. Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design: A Circuits and
Systems Perspective, Third Edition, Chapter 4, Section 6,Pearson Education, 2005
4. http://www.circuitstoday.com/vlsi-design-flow
5. C. Mead and L. Conway, Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980
6. Louis, Luciano Lavagno, Grant Martin, Electronic Design Automation for Integrated Circuits
Handbook, CRC/Taylor and Francis, 2006

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