Auto User

Virtuoso Space-based Router User Guide
Product Version 6.1.5

January 2011
20062011 Cadence Design Systems, Inc. All rights reserved.

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Patents: Cadence Product Space-based Router, described in this document, is protected by U.S. Patents
[1,111,111]; [2,222,222]; and [3,333,333].
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Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Licensing in Virtuoso Space-based Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents for Virtuoso Space-based Router . . . . . . . . . . . . . . . . . . . . . . . . . .
Installation, Environment, and Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technology Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtuoso Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relative Object Design and Inherited Connections . . . . . . . . . . . . . . . . . . . . . . . . . .
Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
12
13
13
1
Getting Started with the Space-based Router . . . . . . . . . . . . . . . . .
Enabling the Space-based Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Layout XL Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Space-based Router Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Considering Lower Level Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4
4
5
6
2
Technology Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technology File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Layer Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Routing Layer Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Via Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valid Layers and Valid Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Via Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Technology File Requirements for Track Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Using Layer Purposes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Poly Pins Over an Implant Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Support For 45 nm Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
January 2011
Foundry Constraint Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
virtuosoDefaultExtractorSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
virtuosoDefaultSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LEFDefaultRouteSpec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Taper Constraint Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Defined Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storing Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constraint Group Lookup Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scalar Versus Table Spacing Rule Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtuoso Space-based Router Supported Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
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14
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17
17
20
20
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24
3
Routing Your Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Router Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conduit Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Post-Route Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Engineering Change Order (ECO) Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Automatic Routing Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Initialize Route Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Global Route Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Local Route Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Detail Route Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Refinement Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Rule Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tie Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deleting Routes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Highlighting Locked Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
29
30
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30
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31
32
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36
38
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40
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45
45
46
January 2011
4
Congestion Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Congestion Analysis Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5
Interactive Wire Editing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Introduction to Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Types of Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the Wire Editing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Startup Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mouse Button Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring Wire Editing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tapping Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding the lxStickyNet Property to Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Wire Editing Environment Variables and SKILL Functions . . . . . . . . . . . . . . . .
Using Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying a Valid Via List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing Layers and Selecting Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fanning Out Wires to Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Via Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating an Array of Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stacking Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for Voltage-Dependent Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Diagonal Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Floating Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Wires Snapped to Track Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working with Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Bus Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autopicking Bus Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 2011
52
52
54
55
58
58
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60
64
65
66
66
66
72
73
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74
75
81
81
85
85
86
86
90
91
92
Creating a Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Restarting a Bus From Existing Routes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Using the Control Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Point to Point Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Setting Point to Point Wires to Match Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Guided Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Comparing Guided Routing with Point to Point Routing . . . . . . . . . . . . . . . . . . . . . . 114
Guided Single Wire Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Guided Bus Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Smart Snapping in Interactive Wire Editing and Assisted Routing Commands . . . . . . . 122
Finishing Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Finishing a Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Finishing a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Composing and Decomposing Trunks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Displaying Wire Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Selecting Wiring Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Object Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Selecting a Single Object or Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Routing Granularity Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Connectivity For Top Level I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Editing Routed Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Stretching Wires and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Pushing Wires and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Moving Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Copying Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Re-routing a Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Reshaping Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Removing Loops From Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Self-intersecting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Merging Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Deleting Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6
Specialty Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Constraints With the Constraint Manager
January 2011
155
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Symmetry Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Types of Symmetry Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining a Symmetry Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Symmetry Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interactive Two Net Symmetry and Self Symmetry Routing . . . . . . . . . . . . . . . . . . .
Differential Pair Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining a Differential Pair Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing Diff Pair Values in the Process Rules Editor . . . . . . . . . . . . . . . . . . . . . .
Interactive Differential Pair Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shield Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining Shield Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shield Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Shielding Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing Custom Shielding Values in the Process Rules Editor . . . . . . . . . . . . . . .
Tying Shield Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin escapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
156
158
160
161
162
162
163
166
167
167
169
170
174
178
178
7
Space-based Router Batch Checking . . . . . . . . . . . . . . . . . . . . . . . . .
179
Batch Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Batch Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Finding Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixing Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimize Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
179
189
192
194
A
Forms Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
197
Automatic Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialize Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detail Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Refinement Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Net Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
199
202
202
202
203
204
206
January 2011
AutoRouter Extraction Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pre-Load Environment Variables Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Batch Checker Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routability Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process Rules Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speciality Routing Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Placement Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fabrication Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Congestion Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Pair Spacing Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Bus Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Bus Form in L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Bus Form in XL and GXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Bus Context-Sensitive Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Geometric Wire Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Geometric Wire Form in L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Geometric Wire Form in XL and GXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Wire Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Single Wire Context-Sensitive Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Editor Options Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Point to Point Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Point to Point Context-Sensitive Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guided Routing Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guided Routing Context-Sensitive Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Select Via Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stretch Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 2011
207
210
211
211
211
211
212
212
212
214
215
216
216
220
225
232
232
238
247
249
251
253
262
262
262
262
264
268
270
276
279
287
B
Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
291
Automatic Router Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Automatic Routing Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Interactive Wire Editing Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
C
Bindkey Keyboard Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
D
Routing Assistants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
317
Wire Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Launching the Wire Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Assistant User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Assistant Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
317
318
319
324
January 2011
January 2011
10
Preface
The Virtuoso Space-based Router enables high-speed shaped-based routing for physical
designs. With Virtuoso Space-based Router you can quickly and efficiently edit, check, and
manipulate interconnects. The hierarchical connectivity and shape model ensures edits are
design-rule and connectivity correct by default.
This user guide describes how to use Virtuoso Space-based Router. It is aimed at developers
and designers of integrated circuits and assumes that you are familiar with:
The Virtuoso design environment and application infrastructure mechanisms designed

to support consistent operations between all Cadence tools.
The applications used to design and develop integrated circuits in the Virtuoso design
environment, notably Virtuoso Layout Suite and Virtuoso Schematic Editor.
The design and use of Quick Cells and other types of parameterized cells.
The OpenAccess version 2.2 technology file.
Component description format (CDF), which lets you create and describe your own
components for use with Layout XL.
Licensing in Virtuoso Space-based Router

Virtuoso Space-based Router requires licenses for both IC 6.1.4 and ICS 6.1.4.
For information on licensing in the Virtuoso design environment, see Virtuoso Software
Licensing and Configuration Guide.
Related Documents for Virtuoso Space-based Router

This user guide does not contain information on all of the functions and commands that are
enabled in Virtuoso Space-based Router.
Commands enabled in a lower tier of Virtuoso Layout Suite are documented in the user guide
for the application in which they are enabled. For example, the base Move command is
documented in the Virtuoso Layout Suite L User Guide; only its extended functionality is
documented in this user guide.
January 2011
11

Preface
Many of the advanced features available in Layout XL are covered in dedicated user guides.
Where this is the case, reference is always made to the book containing detailed information.
The following documents provide more information about the topics discussed in this guide.
Installation, Environment, and Infrastructure
For information on installing Cadence products, see the Cadence Installation Guide.
For information on the Virtuoso design environment, see the Virtuoso Design
Environment User Guide.
For information on database SKILL functions, including data access functions, see the
Virtuoso Design Environment SKILL Reference.
For information on library structure, the library definitions file, and name mapping for data
shared by multiple Cadence tools, see the Cadence Application Infrastructure User
Guide.
Technology Information
For information on how to create and maintain a technology file and display resource file,
see the Virtuoso Technology Data User Guide and the Virtuoso Technology Data
ASCII Files Reference.
For information on how to access the technology file using SKILL functions, see the
Virtuoso Technology Data SKILL Reference.
Virtuoso Tools
For whats new, refer to the Virtuoso Space-based Router Whats New.
For outstanding Cadence Change Requests (CCRs), refer to the Virtuoso Spacebased Router Known Problems and Solutions.
For information about custom layout SKILL functions, see the Virtuoso Layout Suite
SKILL Reference.
For information on how to perform design tasks with the Virtuoso Layout Suite L layout
editor, see the Virtuoso Layout Suite L User Guide
For information on design rule driven editing, see the Virtuoso Design Rule Driven
Editing User Guide.
January 2011
12

Preface
For information on a collection of general layout tools designed to streamline command

sequences and solve specific issues common to custom mask designers, see the
Virtuoso Toolbox User Guide.
For information on how to use the Virtuoso Layout Suite wire editing capability, see
Virtuoso Space-based Router User Guide.
For information on how to use the automatic custom digital placer to place your design
components, see the Virtuoso Custom Digital Placer User Guide.
For information on creating parameterized cells using the graphical user interface or lowlevel SKILL functions, see the Virtuoso Parameterized Cell Reference.
For information on Quick Cells, see the Virtuoso Quick Cells User Guide.
For information on Component Description Format, see the Component Description

Format User Guide.
For information on how to stream mask data, see the Design Data Translators
Reference.
For information on custom layout SKILL functions, see the Virtuoso Layout Suite
SKILL Reference.
Relative Object Design and Inherited Connections
For information on using relative object design (ROD) functions, see the Virtuoso
Relative Object Design User Guide.
For information on connectivity and naming conventions for inherited connections, and
how to add and edit net expressions in a schematic or symbol cellview, see Virtuoso
Schematic Editor L User Guide.
Typographic and Syntax Conventions

The following typographic and syntax conventions are used in this manual.
text
Indicates text you must type exactly as it is presented.
z_argument
Indicates text that you must replace with an appropriate

argument. The prefix (in this case, z_) indicates the data type
the argument can accept. Do not type the data type or
underscore.
January 2011
13

Preface
[ ]
Denotes an optional argument. When used with vertical bars,

they enclose a list of choices from which you can choose one.
{ }
Used with vertical bars, they denote a list of choices from which
you must choose one.
Separates a choice of options.
Indicates that you can repeat the previous argument.
=>
Precedes the values returned by a Cadence SKILL language

function.
Separates the possible values that can be returned by a

Cadence SKILL language function.
text
Indicates names of manuals, menu commands, form buttons,

and form fields.
January 2011
14
1
Getting Started with the Space-based
Router
The Virtuoso Space-based Router GUIs aids designers in running the autorouter. It provides
access to the options for various steps in a routing flow and also provides a template of TCL
code that will run the steps so that the user can customize it as they become more familiar
with the routing commands.
This section discusses the following.
Enabling the Space-based Router
Using Layout XL Extraction
Hierarchical Level Control
Enabling the Space-based Router

The Virtuoso Space-based router is available in Virtuoso Layout Suite XL and GXL. You
can access the Space-based Router functionality using the Route menu, which is available
by default in Layout XL and GXL.
The VSR toolbar is not available by default in the layout window. To activate the VSR toolbar
from Virtuoso Layout Editor GXL, perform the following steps:
1. Click Launch Layout GXL.
The VLS GXL window is displayed.
January 2011

Getting Started with the Space-based Router
2. Click Window Toolbars Space-based Router. The Space-based Router toolbar
is displayed. You can access the Space-based Router functionality using the icons on the
Space-based Router toolbar as shown in the following figure.
Automatic Routing
Highlight Locked Nets
Straighten Wires
Optimize Route
Delete Routing
Fix Violations
Toolbar Customize
Congestion Analysis
Fix Antenna
Automatic Routing
The Automatic Routing menu option or icon displays the Automatic Routing form.
The form has sub forms allowing you to set up and route the Initialize, Global, Local,
Conduit, Detailed, and Refinement routing modes. See Using the Automatic Routing
Form for more information.
Routing Scripts
An existing routing flow may be captured in the form of TCL routing commands within a
TCL script. You can execute the TCL script to view the desired routing results. The
Routing Scripts menu option allows you to execute the TCL script.
Tie Shield
Ties shield wires to shield nets in the design and allows you to set the tie frequency. Tie
frequency is the distance between the ties.
Delete Routing
This is an interactive action where you explicitly ask for the routing to be deleted. Clicking
the Delete Routing menu option deletes all the routes that were not in the constraints or
were in FIXED constraints. However, the routes in the LOCKED constraint are not
deleted.
January 2011

Straighten Wires
Straighten Wires View Area
Runs a critic pass that smooths wires by removing unnecessary jogs where possible
after routing for a selected area.
Straighten Wires Entire Cell View
after routing for entire cell view.
Straighten Wires Selected Nets
after routing for the selected nets in the design.
Fix Antenna
Fix Antenna attempts to fix the error types. It takes all nets in the visible window into
account. No selections or exclusions are considered.
Fix Violation
Fixing View Area
Allows you to fix the violation operations for a selected area
Fixing Entire Cell View
Allows you to fix the violation operations for the entire cell view.
Optimize Route
Optimize Route View Area
Allows you to perform various wire optimization post processes for a selected area.
Optimize Route Entire Cell View
Allows you to perform various wire optimization post processes for entire cell view.
Optimize Route Selected Nets
January 2011

Allows you to perform various wire optimization post processes for the selected nets in
the design.
Congestion Analysis
Allows you to do a quick global route to calculate a congestion map that allows the user
to identify areas of heavy routing congestion.See Congestion Analysis for information.
Highlight Locked Nets

Highlights locked nets in the design.
Note: You can also access the menu items using your keyboard. With the Route menu
displayed, press the corresponding key to display each form as follows.
for the Automatic Routing form, press a.
for the Delete Routing form, press d.
for Straighten Wires, press s.
for Congestion Analysis, press c.
to Highlight Locked Nets, press h.
Using Layout XL Extraction

When using the wire editing commands in Virtuoso Layout XL and GXL, be sure that the XL
extractor is enabled by checking Verify connectivity during interactive editing in the
Layout XL Options form. The DRD Enforce and Notify interactive modes use the XL
extractor to correctly handle unassigned shapes during the commands, Create Wire,
Stretch, Reshape, and Point to Point. If the XL extractor is disabled, these commands may
not work as expected on unassigned shapes (shapes not assigned to a net).
Space-based Router Extraction

The Space-based Router Extract option on the Extraction tab of the Layout XL Options
form provides a means to extract connectivity for instances whose master does not have its
shapes properly stamped with connectivity. Shapes without connectivity are considered
blockages and the router cannot create connections to the instance.
January 2011

The extraction process is called at the start of routing commands or when remastering
instances. By default, pcells are extracted. Two other options are available, none and all. The
none option by passes the extraction process, and the all option runs the extraction process
on all instance masters. The all option can be useful for designs that have pcells nested two
or more levels down in the hierarchy, as the XL connectivity extractor does not extract pcell
masters during hierarchical extraction.
When working on the top levels of a large hierarchical design, setting the Space-based
Router Extract option to all can have a performance impact.
Hierarchical Level Control

You can control the hierarchy depth for the following.
Display - set Start and Stop Display Levels in the Display Options form.
The stopLevel setting controls the range of hierarchy levels displayed in the canvas
window. The initial display stopLevel for a given design is determined in the current
session when the design is opened and levels of nested design data are displayed.
Routing - set Start and Stop Display Levels in the Display Options form.
Hierarchy depth is the level of hierarchical design data processed by interactive and
automatic routing commands including point-to-point, finish routing, power routing, and
signal routing.
For routing, the hierarchy depth is determined by the display stopLevel at the time you
run any interactive or automatic routing command. The router sees and processes data
to the currently set display stopLevel. For example, the router sees blockages down to
that level of the design data hierarchy.
Subsequent changes to the display stopLevel add, but do not subtract, levels of
hierarchy. If the display stopLevel is reduced, for example from 32 to 1, then the levels
of nested data processed remain unchanged. If display stopLevel is subsequently
increased, then the additional levels of nested data are processed.
For example, if the display level is set to 32 and you return up the hierarchy to display
level 1, data to display level 32 is still recognized. If the display level is set to 1and you
descend to display level 32, a display level of 32 is now recognized.
Note: If you change the stopLevel while you are in a command, for example, Create
Wire, the additional levels of hierarchy will not be recognized by the command. You need
to exit the command, change the stopLevel, then execute command.
Routing hierarchy depth is re-established, and therefore can be reduced, when the
design is reopened for routing after Discard Edits. For example, set display level to 32.
January 2011

Route. The hierarchy depth is 32. Discard Edits. Reduce the display level to 2. Route.
The routing hierarchy depth is now 2.
Extraction - set Extract connectivity to level in the Extraction tab of the Layout XL
Options form.
This setting controls the number of hierarchy levels to check when extracting
connectivity.
Interactive rule checking - set the Hierarchy Depth in the DRD Options form.
This settings tells the DRD rule checker the level to which to check for violations.
It is important to be aware of all three depth settings to ensure intended results.
Considering Lower Level Shapes

The environment variable allLowerLevelShapeForRoute controls the pin model used for
extraction. A value of t causes the entire net to be modelled as a pin. A value of nil will
cause only the labelled shapes to be modelled as a pin. The use model for considering lower
level shapes is, once the cellview is loaded in Virtuoso XL or GXL,
1. Set the Options Display Stop (Display Levels) to 1
This controls the extraction level or hierarchy depth that the extractor will use.
2. Set the Extract connectivity to level in the Extraction tab of the Layout XL Options
form to all
This controls the type of instances to be extracted.
3. Set the environment variable allLowerLevelShapeForRoute as follows:
envSetVal("rte" "allowLowerLevelShapeForRoute" 'boolean t))
This controls the pin model used by the extractor. Alternatively this setting can be add to
the .cdsenv.
January 2011
2
Technology Requirements
This section discusses the following:
Technology File Requirements
Constraint Groups
Virtuoso Space-based Router Supported Constraints
Technology File Requirements

This section specifies minimum requirements for the technology file.
Layer Definitions
The layerDefinitions section of the technology file defines the layers that can be used
throughout the technology file. layerRules in the layerDefinitions section defines a
layer function and unique mask number for each layer.
Defining the layer function and the mask number in the technology file functions section,
gives explicit information about which layers are adjacent to each other. Specify layers and
mask numbers for all interconnect layers in the technology file.
The mask number is used to,
order the layers in the Select Via form
determine which layer is the next layer up and the next layer down from the current layer
when selecting Via Up or Via Down
determine the next or previous layer automatically when the Create Wire command
is initiated and a non-routing layer is the current layer.
In absence of mask numbers, the layer purpose priority is used. However, this is not as
reliable as defining the mask number since the mask number is not dependent on purposes.
January 2011

Note: The router may not work if the mask numbers are not specified correctly.
Valid Values: cut, li, metal, ndiff, pdiff, nplus, pplus, nwell, pwell, poly, diff,
recognition, other, unknown
The following example is specific to Space-based routing. The layerRules section in your
techfile will have more layers and layer definitions.
layerRules(
functions(
;( layer function [maskNumber])
;( ----- -------- ------------)
( POLY
"poly"
0 )
( CO
"cut"
1 )
( Metal1 "metal"
2 )
( VIA
"cut"
3 )
( Metal2 "metal"
4 )
...
Note: The router currently understands only one poly layer, so include only one poly layer in
the technology file.
Define one and only one cut layer between each pair of metal layers.
Note: When the function table is not defined or it is defined but the mask numbers are not
defined, vias are still available through the Create Wire command. However, the following
warning message is issued.
\w *WARNING* geViaSet : Incomplete layer maskNumber, the order of the vias may
not be correct.
For more information, see Technology File Layer Definitions in the Virtuoso Technology
Data ASCII Files Reference.
Routing Layer Directions

Set a preferred routing direction for each routing layer.
layerRules(
routingDirections(
;( layer direction )
;( ----- --------- )
( POLY
( Metal1
( Metal2
...
"none" )
"horizontal" )
"vertical" )
For more information, see Routing Directions in the Virtuoso Technology Data ASCII
Files Reference.
January 2011

Via Definitions
At a minimum, define all standard vias for interconnect using routing layers in the viaDefs
section of the technology file. Typically, this is a set of standard vias between the poly layer
and the highest metal layer.
For example.
viaDefs(
standardViaDefs(
;(
viaDefName layer1 layer2 (cutLayer cutWidth cutHeight [resistancePerCut])
; (cutRows cutCol (cutSpace))
; (layer1Enc)
(layer2Enc)
(layer1Offset)
(layer2Offset)
(origOffset)
; [implant1
(implant1Enc) [implant2
(implant2Enc) [well/substrate]]])
;( -------------------------------------------------------------------------- )
( mpoly
Metal1 POLY
("CO"
0.09
0.09)
(1
1
(0.11 0.11))
(0.04 0.0)
(0.04 0.01)
(0.0 0.0)
(0.0 0.0)
(0.0 0.0)
)
( m1m2
Metal1 Metal2 ("VIA"
0.1
0.1)
(1
1
(0.1 0.1))
(0.04 0.0)
(0.04 0.0)
(0.0 0.0)
(0.0 0.0)
(0.0 0.0)
)
...
Define custom vias required for routing.

customViaDefs(
;(
viaDefName
;(------------
libName
cellName
viewName
layer1
layer2
resistancePerCut)
--------- --------- --------- ------- ------
--------------)
(VIAm1m2_2CUT_N
tsmc65lp
VIAm1m2
via
Metal1
Metal2
0.95)
(VIAm1m2_2CUT_S
tsmc65lp
VIAm1m2
via
Metal1
Metal2
0.95)
(VIAm1m2_2CUT_E
tsmc65lp
VIAm1m2
via
Metal1
Metal2
0.95)
(VIAm1m2_2CUT_W
tsmc65lp
VIAm1m2
via
Metal1
Metal2
0.95)
...
In constraint groups, include appropriate subset of vias.

Note: Via variants used by other tools are not currently recognized by Virtuoso.
For more information, see Technology File Via Definitions and Via Specifications in the
Virtuoso Technology Data ASCII Files Reference.
January 2011

Valid Layers and Valid Vias

Define valid layers and vias in a default constraint group. Do not use the foundry constraint
group for validLayers and validVias. Define only process rules in the foundry constraint
group.
For example.
;( group [override] )
;( ----- ---------- )
( "virtuosoDefaultSetup" nil
interconnect(
( validLayers
( validVias
) ;interconnect
(POLY
(mpoly
Metal1
m1m2
Metal2 ...) )
... ) )
) ;virtuosoDefaultSetup
Note: If no validVias statement exists, a full set of standard vias is defined for the session
based on the layers in the validLayers statement.
The autorouter only uses vias having both layers defined as valid routing layers. If a via has
a metal layer that is not a valid routing layer, the router can still use it for pin access if it is in
the valid via list. In particular, vias for which the bottom layer is oxide, well or implant are not
used. Virtuoso Space-based Router issues a warning message when initializing a design if
the constraint group contains such vias.
For more information, see validLayers and validVias in the Technology File Constraint
Groups and Constraints section of the Virtuoso Technology Data ASCII Files
Reference.
Via Usage Model

For Detail routing, Virtuoso Space-based Router considers a limited number of vias and via
variations for each layer pair. The standard via variations are based on the constraints and
the type of route (e.g. taper).
The detail router chooses a limited number to use during routing from the custom vias and
the derived standard via variations based on the amount of routing resource required by each.
The vias/via variations chosen are those that require the fewest resources.
Technology File Requirements for Track Patterns

Following is an example of the technology file requirements that support track patterns.
January 2011
10

layerDefinitions(
techPurposes(
(track 229 trk)
...
)
Note: techPurposes are system reserved purposes found in the default cdsDefTechLib
techDisplays(
(METAL1 track m1_Packet t t t t t)
...
)
techLayerPurposePriorites(
(METAL1 track)
...
)
layerRules(
functions(
(METAL1 "metal" 3)
...
)
Using Layer Purposes

In the Virtuoso design environment technology file, it is possible to define technology rules for
layer purpose pairs (LPP). However, OpenAccess rules/constraints are only applicable to
layers, not layer purpose pairs. In the Virtuoso design environment, any technology rule which
is defined for a layer purpose pair is stored as a private extension and is only available for
Virtuoso applications. The private extension is not visible outside Virtuoso applications.
Layers based on a purpose can be selected from the LSW (LPPs must be valid and visible).
However, when tapping an existing shape, the layer purpose is not used directly. You can
create a prioritized list of purposes that allow you to use a layer based on a purpose. See
Tapping Wires.
Poly Pins Over an Implant Layer

If minSpacing is defined between poly and implant layers, then any poly pin shape which is
fully overlapped by an implant layer will be viewed as blocked and will not be accessible by
the automatic router, Point to Point router, and Finish Wire and will result in routing failures.
Support For 45 nm Rules

In order to use the newer 45 nm technology rules, these rules must coded in the technology
file techLayerProperties section. The following example shows LEF57_AREA,
LEF57_ENCLOSUREEDGE, and LEF57_SPACING for second EOL rule support.
January 2011
11

techLayerProperties(
;( PropName
Layer1 [ Layer2 ]
PropValue )
;( --------
------ ----------
--------- )
( LEF57_AREA
Metal1 "AREA 0.07 EXCEPTEDGELENGTH 0.41 EXCEPTMINSIZE 0.41 0.14 ;"
)
( LEF57_ENCLOSUREEDGE Via2
"ENCLOSUREEDGE 0.08 WIDTH 0.26 PARALLEL 0.5 WITHIN
0.4 ;" )
( LEF57_SPACING metal1
"SPACING 0.12 ENDOFLINE 0.10 WITHIN 0.035 MINLENGTH 0.07
PARALLELEDGE 0.12 WITHIN 0.10 ENCLOSECUT BELOW 0.05 CUTSPACING 0.15 ;")
) ;techLayerProperties
Constraint Groups
Using constraint groups within Virtuoso is a very powerful and versatile way to control both
interactive and automatic routing behavior and ultimately the final design results. Constraint
group application spans a wide array of usage from dictating the technology foundry rules to
application-specific rules to user-defined constraint groups to aid layout designers in designspecific tasks.
It is important to understand that there are two distinct steps necessary to realize the
application of any constraint group within the physical layout.
1. Definition of a constraint group
2. Application of the constraint group
Constraint groups can be defined within the technology database (provided you have write
permission) or on the design (i.e. lib/cell/cellview). But until constraint groups are actually
applied to objects within your design or set as the default constraint group, they are
meaningless. The exception to this rule is the foundry constraint group which defines the
technology rules.
There are three types of constraint groups you can create.
1. Foundry constraint group
Example: foundry
2. Application-specific constraint group(s)
Examples: virtuosoDefaultExtractorSetup, virtuosoDefaultSetup,
LEFDefaultRouteSpec
3. User-defined constraint group(s)
Examples are unlimited: shieldTheseNets, wideWires
January 2011
12

There can only be one foundry constraint group, but there can be any number of applicationspecific constraint groups and user-defined constraint groups for routing specific nets or net
types.
Foundry, Application-specific and User-defined constraint groups may be created
automatically during a translation process such as cdb2oa or lef2oa, and are based on the
information in either the CDB techfile or LEF/DEF files. Other constraint groups may be
created by your CAD group, and still others created by the individual layout designer. Some
can be stored in a technology database and/or on the design itself.
In Virtuoso XL/GXL, you typically have the following three constraint groups as a required
minimum.
Foundry
virtuosoDefaultExtractorSetup
virtuosoDefaultSetup
Foundry Constraint Group

The foundry constraint group represents the absolute minimum rules (i.e. minWidth/
minSpacing, etc.,) which must be adhered to in order to manufacture the design. These are
commonly referred to as the base process rules and are stored only in the technology
database.
Define the complete set of process rules in the foundry constraint group. Do not depend on
a technology file translated from elsewhere to contain all needed rules. For example, a 65nm
tech file translated from CDB will not include all required rules because not all 65nm rules are
code able in CDB.
Creation and usage
Creating the Foundry Constraint Group

The foundry constraint group is created and populated with information during cdb2oa
translation or lef2oa translation. The translators get the information from sections within
the CDB techfile and the LEF file.
Alternatively, you can create the foundry constraint group by loading an ASCII
technology file containing the foundry constraint group information through the
Technology File Manager Toolbox, which you can invoke from the CIW.
Information in the foundry constraint group
January 2011
13

The foundry constraint group contains all of the information necessary to manufacture
the design. Everything from minSpacing/minWidth for layers, minEnclosure,
minStep, to via rules, to electrical constraints such as antenna rules.
Using the foundry constraint group in Virtuoso

The foundry constraint group is the final stop along the constraint precedence lookup
trail. If a constraint override is not defined elsewhere, the tools use the value(s) in the
foundry constraint group.
Most all functionality uses the foundry constraint group at some point. As the last stop
in constraint precedence lookup, the foundry constraint group is the final place and
many times the only place the value(s) for a constraint are defined.
The foundry constraint group is not typically writable for most users, but can be viewed
in the Process Rule Editor. You can launch the Process Rule Editor by clicking the RMB
in the Constraint Manager assistant or by clicking the PRE icon from the toolbar in the
Constraint Manger assistant. Within this dialog you can set the scope to Technology and
view the foundry constraint group.
Application Constraint Groups

An application constraint group is used to target a basic set of rules within a given application.
Although you can define numerous application specific constraint groups and switch between
them at any time, you can reference only one as the default by setting the Wire cyclic field in
the Layout Editor Options form (Options Editor...) at any given time. It is important to
note, however, that at any given time during routing or wire editing, the rules to apply to
specific objects may be derived from a number of different constraint groups, based on
specific constraint group lookup precedence.
Application-specific constraint groups can be stored within the technology database or
directly on the design itself (i.e. lib/cell/cellview).
Examples: virtuosoDefaultExtractorSetup, virtuosoDefaultSetup, LEFDefaultRouteSpec
Creation and usage
Creating the virtuosoDefaultExtractorSetup Constraint Group

The virtuosoDefaultExtractorSetup constraint group is created during cdb2oa
translation. The lxExtractLayers and lxNoOverlapLayers sections are converted
to layers belonging to a constraint group named virtuosoDefaultExtractorSetup.
January 2011
14

Alternatively, this constraint group may be created by loading an ASCII technology file
containing the constraint group section, or through the Process Rule Editor.
Information in the virtuosoDefaultExtractorSetup Constraint Group

The virtuosoDefaultExtractorSetup constraint group includes layers needed for
extracting connectivity, plus poly, all metal layers, and cut layers.
Using the virtuosoDefaultExtractorSetup Constraint Group in Virtuoso

A constraint group for extraction is required to specify the extractable layers for Virtuoso
XL/GXL.
Connectivity extraction gets the constraint group name from the value of the
setupConstraintGroup variable in your .cdsenv file. The default value is
virtuosoDefaultExtractorSetup. You can change the name of the constraint
group by resetting the value.
If the setupConstraintGroup variable has no value set, the extractor prompts you for
a constraint group to use for extraction.
Note: Cadence does not recommend using the virtuosoDefaultExtractorSetup
constraint group as the Wire constraint group in the Wire Editing section of the Layout
Editor Options form (Options > Editor...).The purpose of the
virtuosoDefaultExtractorSetup constraint group is to supply XL/GXL with the
layers from which to extract connectivity. Also, this constraint group will not contain any
validVias for the router to use. So, although it is technically possible to set the
virtuosoDefaultExtractorSetup constraint group as the Default Constraint
Group, which is used for default wiring, it serves a different purpose and will therefore
most likely contain validLayers not suitable for wire editing.
The purpose of the virtuosoDefaultSetup constraint group is to supply a default set of
constraints for both interactive and automatic routing.
Creation and usage
Creating the virtuosoDefaultSetup Constraint Group

The virtuosoDefaultSetup constraint group is created during the cdb2oa
translation using one of the following methods.
If the CDB techfile includes the iccRules section, the cdb2oa translator automatically
translates the rules from the iccRules section to create the virtuosoDefaultSetup
constraint group.
January 2011
15

If the ASCII VCAR rule file is available during cdb2oa translation, use the
-iccrulesfile option of the cdb2oa translator to create the
virtuosoDefaultSetup constraint group. The syntax is the following.
cdb2oa -iccrulesfile <vcarRuleFile>
Information in the virtuosoDefaultSetup Constraint Group

The virtuosoDefaultSetup constraint group contains validVias and
validLayers for routing (no cut layers), and possibly other rules such as minWidth
and minSpacing for the layers, overriding the foundry rules.
Using the virtuosoDefaultSetup Constraint Group in Virtuoso

The virtuosoDefaultSetup constraint group is typically used to defined a full set of
validLayers and validVias for the purpose of default interactive and automatic
routing.
For example, if any particular signal is selected for routing and does not have a constraint
group assigned to it, the constraints in the virtuosoDefaultSetup constraint group
apply. The contents of validLayers in virtuosoDefaultSetup are usually a subset
of those defined in the virtuosoDefaultExtractorSetup constraint group
because, while you may want to extract connectivity for non-metal layers, you do not want
interactive and automatic routing to use the non-metal layers.
The virtuosoDefaultSetup constraint group is the constraint group most commonly
used as the default constraint group for routing.
An application constraint group targets a basic set of rules within a given application.
Although you can define numerous application specific constraint groups and switch
between them, you can reference only one at any given time.
The name given the wire editing default constraint group can be anything you choose as
a standard. Cadence has chosen virtuosoDefaultSetup as the name of the
constraint group created by the cdb2oa translator. You can control the name of the
Default Constraint Group from the GUI or by setting an environment variable in the
.cdsenv file.
a. Wire constraint group in the Wire Editing section of the Layout Editor Options
form (Options > Editor...).
b. Environment variable wireConstraintGroup in the .cdsenv file.
Note: If the wireConstraintGroup variable is not set, interactive and automatic
routing use the value of the setupConstraintGroup as the default constraint
group. Because the constraint group specified in setupConstraintGroup is for
extraction, you do not want it used for routing. So, be sure to set a default constraint
group for routing purposes.
January 2011
16

LEFDefaultRouteSpec
The LEFDefaultRouteSpec constraint group contains rule definitions typically used in
digital standard cell applications or custom/mixed signal applications that require metal layers
only.
Creation and usage
Creating the LEFDefaultRouteSpec Constraint Group

The LEFDefaultRouteSpec constraint group is specific to a LEF/DEF design flow and
is created during lef2oa translation. Since a LEF file serves as the library source for
technology information, the lef2oa translator puts all the technology information into
the LEFDefaultRouteSpec constraint group.
All layers, via definitions, and layer rules also become part of the
LEFDefaultRouteSpec constraint group.
Note: The lef2oa translator translates any NONDEFAULTRULES in LEF as constraint
groups in the OpenAccess tech database.
Information in the LEFDefaultRouteSpec Constraint Group

The LEFDefaultRouteSpec contains layer and via definitions. The via definitions are
typically standard vias and several custom vias used by other routers such as
NanoRoute in the Encounter environment. The LEFDefaultRouteSpec also contains
process rules for metal shapes that are wide.
Using the LEFDefaultRouteSpec Constraint Group in Virtuoso

You can select the LEFDefaultRouteSpec as the default constraint group for
interactive or automatic routing in the Wire Editing section of the Layout Editor
Options form (Options > Editor...).
Taper Constraint Group

The taper constraint group can be used for several purposes. The primary purpose is to taper
the width of a wire to match the width of the pin to which it connects where there is not enough
room to connect to the pin with the specified wire width. You can also adjust the widths of
taper routing. Many different constraints can be included in the taper constraint group.
Another purpose is to restrict routing on the poly layer to the taper and set a taperHalo to
control the length of the taper routing. See Limiting routing on a layer for more explanation
and an example of the syntax.
January 2011
17

Note: Once you specialize the taper constraint group, for example to restricting routing on
poly, you cannot use the taper constraint group to also taper the widths of wires on other
layers.
How the Router Uses the Taper Constraint Group
When you invoke the design, there are three constraint groups the application searches for
by default. These constraint groups, whether they are defined in your technology library or
not, are specified in the default .cdsenv with the following environment variables.
layout setupConstraintGroup string "virtuosoDefaultExtractorSetup"
layout wireConstraintGroup string "virtuosoDefaultSetup"
layout wireTaperConstraintGroup string "virtuosoDefaultTaper"
First, the router attempts to route a net using constraints from the net constraint group, design
constraint group, and application default constraint group. The precedence order is
a. net constraint group
b. application default constraint group
c. design constraint group
d. foundry constraint group
If the router cannot connect to a pin for some reason, it attempts to connect using constraints
from the input/output taper constraint group, application default taper constraint group. The
precedence order is
a. input/output taper constraint groups
b. application taper constraint group
Some possible reasons the router may not connect to a pin are
a layer conflict. For example, a poly pin but, poly is not in the validLayers constraint
of the net, design, or application default constraint group
a spacing conflict. For example, the width + spacing of the net is larger than the
distance between the target pin and a neighboring pin or blockage
The taper constraint group is only used when the router cannot connect to a target pin using
the regular net/design/default constraints. If the router is able to complete a route using the
regular net/design/default constraints, it does not use the taper constraint group.
January 2011
18

Defining the Taper Constraint Group
When routing requires tapering, for best results define a virtuosoDefaultTaper
constraint group. Explicitly defining a taper constraint group ensures that the correct layers
and widths are being used for the tapered wires. You can control the global taper routing
mode using the environment variable setTaperMode.
When defining the validLayers constraint in your taper constraint group, it is best to
include all the layers defined in the validLayers constraint in the Wire constraint group
in the Wire Editing section of the Layout Editor Options form.
Note: If you include all the layers in the validLayers constraint of the taper constraint
group, but some of your nets require a more restricted layer set, use the input/output taper
constraint groups to reduce the validLayers list for those specific nets. Use the Process
Rule Editor to assign the validLayers constraint to the input/output taper constraint
groups.
In the event that the virtuosoDefaultTaper constraint group is not defined, the
application will derive a constraint group using values from the wireConstraintGroup which
defaults to virtuosoDefaultSetup. If the wireConstraintGroup is not defined, then the
application will derive a constraint group from the setupConstraintGroup which defaults to
virtuosoDefaultExtractorSetup. However, allowing a different constraint group to be used as
the default taper constraint group could result in unexpected results and inappropriate layers
or constraints for taper routing.
Note: If you have a taper constraint group attached to the net and the minWidth defined in
that constraint group is greater than the width of the pins, the router may taper down using
the minWidth defined in the wire constraint group when connecting to those pins. This
optimizes routing for pin connections. The router does not consider the behavior as a violation
of the net based constraint group. See the illustration below.
minWidth 0.20 in net-based
virtuosoDefaultTaper constraint group
pin width 0.14
minWidth 0.14 in
wiring constraint group
January 2011
19

User-Defined Constraint Groups

User-defined constraint groups are specific to the design or to objects in the design. You may
use any name as long as it has not already been used for another constraint group.
Examples are constraint groups for double width/double space rules, for shielding wires, for
setting symmetry constraints, or for a specific layer set.
Creation and usage
Non-default constraint groups defined in the technology LEF will be translated as userdefined constraint groups and stored in the technology database.
You can also create a user-defined constraint group by loading an ASCII technology file that
contains a constraint group section, or through the process rule editor.
You can have any number of user defined constraint groups and you can store them either in
the technology database (if you have write permissions) or on the design itself (i.e. lib/cell/
cellview). A common example of a user-defined constraint group would be for wide wire rules
for a particular set of signals. User-defined constraint groups can be used whenever particular
routing considerations need to be applied to signal(s).
Note: If you attach a constraint group to a net and the minWidth defined in that constraint
group is greater than the width of the pins, the router may taper down using the minWidth
defined in the wire constraint group when connecting to those pins. This optimizes routing for
pin connections. The router does not consider the behavior as a violation of the net based
constraint group.
Examples: wideWireCG, shieldedWiresCG, onlyM7M8layersCG, etc.
Storing Constraint Groups

The foundry constraint group is stored in the OpenAccess technology library database. You
can also store any user-defined constraint groups within the technology library database,
provided you have write permission to the technology library. This has the advantage of being
a centrally accessible location and provides added control over the definitions in the
constraint groups.
Note: Constraint groups defined within the technology library should be generally applicable
to any type of design derived from the specific technology.
Application-specific and user-defined constraint groups can also be stored on the design itself
and should be when constraints are not applicable to the entire technology.
January 2011
20

Storing user-defined constraint groups within the technology database enables reuse for
anyone accessing that particular technology library.
Note: You need to have write access to the technology library for setting foundry constraints.
An application constraint group can be stored within the technology database or directly on
the design itself (i.e. lib/cell/cellview).
Constraint Group Lookup Precedence

In Virtuoso, the foundry constraint group provides process rules for all objects. However,
you can override the rules in the foundry constraint group for specific objects or for the
design.
Multiple constraint groups defining the same constraints can exist in a single technology file.
When this is the case, the constraint groups are applied according to the following
precedence:
1. The default constraint group, which is the constraint group currently being referred to by
a command and currently applied to the window.
2. Any setup or other constraint group recognized as the constraint group of first
precedence by Virtuoso.
3. The foundry constraint group. This constraint group must be named foundry.
Virtuoso searches the constraint groups it recognizes in the order of precedence it has set. It
applies the first hard constraint it finds, or, if it searches all of the constraint groups without
finding a hard constraint, it applies the first soft constraint it finds.
January 2011
21

The following diagram shows the simplified constraint search hierarchy.
all constraints
Override
Region
Group Level
Interchild
TransReflexive
Object Level
oaPreferredRoutingDirection
minSpacing
crossTalkNeighborIndex
Reflexive
minSpacing
Shape
(blockage)
minSpacing
effectiveWidth
minSpacing
minWidth
validRoutingLayers
validRoutingVias
minNumCut
minDualExtension*
(*create_derived_vias only)
Route
Net
NetGroup
minSpacing
minWidth
validRoutingLayers
validRoutingVias
minNumCut
Global Net Default

(LEFDefaultRouteSpec)
oaPreferredRoutingDirection
minDualExtension*
(*create_derived_vias only)
January 2011
Design route spec
all constraints
Foundry route spec
all constraints
22

The following table shows constraint group lookup precedence in the Virtuoso Space-based
Router. Precedence starts with constraints attached to objects and ends with constraints in
the Foundry constraint group.
Entities
Examples
Net
Net group
reflexive, transreflexive, default
Application-specific constraint
group
virtuosoDefaultSetup constraint
group
Design
constraints specific to this design
Foundry
process technology rules
For more information, see Getting Started with Virtuoso Unified Custom Constraints
and Technology File Constraint Groups and Constraints in the Virtuoso Technology
Important
When routing a design, it is important to maintain the constraint group definition
used for specific nets throughout the routing process. Changing constraint groups
on a net can result in unpredictable layers and constraints being applied during
routing.
Scalar Versus Table Spacing Rule Precedence

When both scalar and table spacing rules exist in the technology database, the rules are
applied as follows.
When both are present in a single constraint group, the first spacing rule found is the one
applied. The second one is ignored. This precedence holds true regardless of whether
the value is a scalar spacing rule or a table spacing rule.
When each exists alone in its own constraint group, the scalar value is used as a default
regardless of the precedence order. The table values are also used, but only for the
larger widths, not the default.
January 2011
23

Virtuoso Space-based Router Supported Constraints

The following table shows the constraints supported by the Virtuoso Space-based Router.
Note: For information about constraints supported by DRD, see Supported Constraints
in the Virtuoso Design Rule Driven Editing User Guide. DRD includes options to check
for errors during interactive editing or to turn off checking during editing and check for errors
after editing the layout.
Technology Process Rule Constraints
Supported by
Create Wire/Bus
Supported by
Automatic Router
allowedWidthRanges
no
yes
cutClasses
no
yes
horizontalOffset
no
yes
horizontalPitch
no
yes
largeRectViaArrayAllowed
no
yes
maxDensity
no
yes
maxDiffDensity
no
yes
maxFloatingArea
no
yes
maxLength
yes
no
maxNumMinEdges
no
yes
maxWidth
yes
no
minArea
yes
yes
minAreaEdgeLength
no
yes
minCutClassSpacing(two layer)
no
yes
minDensity
no
yes
minDiagonalSpacing
yes
no
minDiagonalWidth
yes
no
minEdgeAdjacentDistance
no
yes
minEdgeAdjacentLength
no
yes
minEnclosure
yes
yes
January 2011
24

Supported by
Create Wire/Bus
Supported by
Automatic Router
minEndOfLinePerpSpacing
no
yes
minEndOfLineSpacing
no
yes
minEndOfLineExtensionSpacing
no
yes
minExtension
yes
no
minExtensionEdge
no
yes
minFillToFillSpacing
no
yes
minHoleArea
no
yes
minLargeViaArrayCutSpacing
no
yes
minLargeViaArraySpacing
no
yes
minLargeViaArrayWidth
no
yes
minLength
yes
yes
minNeighborViaSpacing
no
yes
minNumCut
no
yes
minOppExtension
yes
yes
minOppSpanSpacing
no
yes
minOutsideCornerEdgeLength
no
yes
minParallelSpanSpacing
no
yes
minParallelViaSpacing
no
yes
minParallelWithinViaSpacing
no
yes
minProtrusionNumCut
no
yes
minRectArea
no
yes
minSameMetalSharedEdgeViaSpacing
no
yes
minSameNetSpacing
yes
yes
minSpacing
yes
yes
minWidth
yes
yes
minViaExtension
no
yes
minViaSpacing
no
yes
January 2011
25

Supported by
Create Wire/Bus
Supported by
Automatic Router
minVoltageSpacing(two layer)
no
yes
redundantViaSetback
no
yes
stackable
no
yes
taperHalo
no
yes
verticalOffset
no
yes
verticalPitch
no
yes
viaSpacing
no
yes
viaStackingLimits
no
yes
Constraint Manager Constraints
Supported by
Create Wire/Bus
Supported by
Automatic Router
symmetry
yes
yes
diffPair
yes
yes
shielding
yes
yes
net priority
no
yes
process rule overrides
yes
yes
January 2011
26
3
Routing Your Design
This chapter describes the Virtuoso Space-based Router routing flow.
The following sections are included:
Router Features
Routing Flow
Engineering Change Order (ECO) Routing
Using the Automatic Routing Form
Design Rule Violations
Routing Scripts
Tie Shielding
Deleting Routes
Highlighting Locked Nets
January 2011
27

Routing Your Design
Router Features
Space-based Router provides many features for routing your placed design:
Gridded or Gridless
In gridless mode, the edges of all shapes must be on the manufacturing grid.
In gridded mode, the centerlines and endpoints of route segments must be on a

routing grid, and the origins of vias must coincide with the X and Y of a routing grid.
ECO Routing
You can perform a sequence of design changes, then use the router to make
connections.
You can select modified nets only for routing by the global and the detail router.
You can rerun routing after changing design rules for new technology rules.
Tapering
Space-based Router will taper when necessary to connect pins. Tapering can be
controlled independently by each constraint group.
Tie-up and Tie-down Routing for Power Connections
Connecting to a wide poly pin using a narrow metal wire. The full width of the poly pin is
used to place vias to reduce the resistance of the connection.
Data Model
It is important to note that running the automatic router will change an OpenAccess Data
Model 2 or 3 (DM2 or DM3) design to Data Model 4 (DM4).
January 2011
28

Routing Your Design
Routing Flow
The Space-based Router routing flow includes the following steps:
Preparation involves setting constraints, or rules, and options for features such as
blockages, tapering, and net priorities, to customize your environment.
Global Route replaces all opens with global routes and re-routes to reduce congestion.
Local Route escapes pins in the entire top cellview or in a given region or for nets in a set.
Conduit Route lays down as many wires as possible along routing conduits.
Detailed Route completes the routing of all nets and resolves violations.
Post-Route Refinement fixes some violations, re-routes short connections, and removes
unnecessary vias.
Global Route
The Space-based Router global router replaces all opens with global routes and reduces
congestion so that the resulting interconnection closely approximates a legally routed design.
The information from the global router can be used to seed the detailed routing stages and
provide a good estimation of the detailed routes.
To localize congestion problems, the design is divided into uniform square areas, called
global routing cells, or gcells. Three types of gcells are identified:
Cell gcells occupy an area of the design
Edge gcells represent the region between two cell gcells on the same layer
Down-via gcells represent the region between two cell gcells on different layers
A gcell is overcongested if the routing demand exceeds its available resources. The number
of overcongested gcells is crucial in determining whether the design can be routed without
design rule violations. While the goal for the global router is to have no overcongested gcells,
due to a variety of approximations and abstractions, it can be possible to route the design
when some gcells are overcongested.
The global router runs a sequence of passes, with a congestion analysis run at the start and
end of each pass. In the first pass, the congestion analysis divides the design into gcells and
analyzes the gcells to determine their blockages and capacity. Following this step, the router
updates the net connectivity of the design, creates guides where opens occur. Next, the
router replaces the guides with global routes comprised of route segments and vias. Finally,
the router will re-route global routes to reduce congestion in overcongested gcells. Detailed
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Routing Your Design
routes are not modified, but portions of detailed routes can be deleted to remove antennas
(dangling routes). For each pass, the routing summary reports guide lengths and wire lengths
for detailed and global routes. The congestion summary reports the number of gcells by layer
and gcell type, and the number of overcongested gcells.
The Space-based Router global router differs from other global routers in several ways. First,
it uses a detailed routing representation that provides very accurate estimations for via
counts and wire lengths. Global routes behave exactly like detailed routes, but global routes
can contain shorts. Second, the router uses a sophisticated resource model that accurately
measures resource usage and demand, which allows the router to handle incremental net list
changes without excessive detouring. Finally, the router was built to be incremental in every
way. Besides simply and naturally completing net list changes, it can work off of pre-routed
designs containing any mixture of global routes, detailed routes, and guides.
Local Route
In the local route step, Space-based Router escapes pins in the entire top cellview or for nets
in a set. Metal1 and poly pins are escaped to Metal2.Any disconnect between the ends of the
new connections and the existing global routes are connected with guides to keep the
connectivity legal.
Conduit Route
In the conduit route step, Space-based Router assigns tracks for the globally routed design
and, guided by the global routes, lays down as many wires as possible along routing conduits.
On completion of this step, guides indicate where connections need to be completed in the
detail route stage. Space-based Router strives to make these guides short in length and
ensure that spacing violations can be easily corrected in the final step.
Detailed Route
During detailed routing, Space-based Router runs multiple passes in cycles to complete the
routing of all nets and resolve violations. The initial passes of cycle one attempt to connect all
the unroutes and resolve certain violations (different net and same net spacing, minimum
area, grids and weak connects). Subsequent routing passes modify the routed wiring using
rip-up and retry methods that strive to continuously improve overall results. Additional cycles
deal with any remaining DRC violations including same net violations, minimum width,
minimum area and minimum enclosed area violations.
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Routing Your Design
Post-Route Refinement
In post-route refinement, Space-based Router checks for and attempts to fix specific types of
violations by ripping up wiring and re-routing. In addition, wiring can be improved by re-routing
short connections and removing unnecessary vias.
Engineering Change Order (ECO) Routing

ECO routing completes partial routes while maintaining the existing wire segments as much
as possible and is useful in cases such as the following:
The initial routing is completed and minor changes have been made to a design.
The design has general spacing or connectivity violations.
ECO routing does the following:
Deletes all shapes, but not nets, to resolve spacing violations, leaving guides for the
opens.
Completes routing on the nets to close the opens.
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Routing Your Design
Using the Automatic Routing Form
Choose RouteAutomatic Routing or the Automatic Routing icon from the Routing
toolbar.
The Automatic Routing form displays. The top-level form contains all the information that
a designer would require to set basic operations.
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Routing Your Design
Specifying General Options

1. Choose the area that you want to Operate On:
Cellview
Routes the entire design.
Selected Set
Routes the nets which are selected from the Navigator or the Search Assistant of
the type selected in the Route Nets of Type option.
Note: To perform routing operations within a block, first descend into the instance then select
the nets to route. The router recognizes nets selected in the descended cellview only.
2. Choose the routing style
Device
ASIC
Chip Assembly
3. Choose the default constraint group for routing. By default, the

virtuosoDefaultExtractorSetup constraint group is used, if defined inside the technology
file.
LEFDefaultRouteSpec
virtuosoDefaultTaper
VLMDefaultSetup
4. Choose the routing layer
Choose the Top Layer for routing from the drop-down list.
Choose the Bottom Layer for routing from the drop-down list.
The selected layers need to include the layers that are used for routing. These layers are
included in the taper constraint group (VirtuosoDefaultTaper). The routing layers need to set
up a taper constraint for the router to taper and adjust the halo. This will restrict how far the
poly can reach before creating a via to metal1.
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Routing Your Design
1. Choose the grid for routing. Choose Manufacturing for gridless routing or Routing for
gridded routing.
2. Choose the Special Blockage Treatment option to alter the treatment of the blockages.
Choose how to treat blockages that do not have preset effective minimum width or
minimum spacing properties
Note: When you use the Automatic Routing form to route your design, preset properties
on blockages and properties on nearby shapes are used to determine spacing
requirements.
Enable Treat as Minimum Width to treat these blockages as metal shapes with
minimum width.
Enable Treat as Minimum Space to enforce minimum space edge of the blockage
even if a wider metal shape is next to it.
Enable Ignore Blockage Spacing to ignore the blockage spacing properties set on
the blockage.
Enable Ignore Routespec Spacing to ignore the routespec spacing.
3. Choose the type of net you want to route. You can select Bus or Nets. The default option
is Nets.
4. Choose the nets to be locked after routing or unlock before routing and the nets to be
included/excluded. Click the Options button next to the Net Options field. To know more
about the net options, refer to the Net Options Form section Appendix A, Forms
Reference.
5. Choose Miscellaneous options.
Attempt to Use Double Cut Vias
Choose Attempt to Use Double Cut Vias option to allow pin escape and routing with
double cut vias.
Taper Pin Width
Choose Taper Pin Width to automatically set the routespec of the pin so that the route
will match the width of the pin.
6. Specify the extraction options. Click the Options button next to the Extraction field. To
know more about the options in the Extraction form, refer to the AutoRouter Extraction
Options Form section in Appendix A, Forms Reference.
7. Choose the Run Mode.
Initialize Route
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Routing Your Design
Initializes the setting for routing engine.
Global Route
Replaces all opens with global routes and re-routes to reduce congestion.
Local Route
Adds pin escapes.
Conduit Route
This option is greyed out in this release. It will be made available in a future release.
Detail Route
Completes the routing of all nets and resolves violations.
Post-Route Refinement
Checks for and attempts to fix specific types of violations by ripping up wiring and
re-routing. Can also re-route short connections and remove unnecessary vias.
8. Specify options for the routing steps. You can select the Run Mode, Checkpoint, and also
save the routing step. Each of the routing step displays a dialog box when you click the
Edit button.
Specifying Initialize Route Options
Specifying Global Route Options
Specifying Local Route Options
Specifying Detail Route Options
Specifying Refinement Options
The Run status dot, which has no fill means that the step will not be run. To run a step
that is not selected by default, double-click on the dot to turn it ON. For example, if you
have a Device Level design that is rather large or congested, you could turn on global
route.
Selecting the Checkpoint option for a routing step synchronizes the routing data back in
the Virtuoso Layout windows (in memory).
Selecting the Save option for a routing step saves the routing data to the disk. The data
will be saved to a view with the original view name and a suffix.
Initialize Route: <original view name>_init
Global Route: <original view name>_groute
Local Route:
<original view name>_lroute
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Routing Your Design
Conduit Route: <original view name>_croute
Detail Route:
<original view name>_droute
Refinement:
<original view name>_refine
9. Click Run to route your design.

1. Click the Edit button next to the Initialize step in the Automatic Routing form.
The Initialize form displays.
2. Click the Options button next to the Layer Map field to select a layer map.
The Layer Map form displays.
3. If you need to map layers, for example, diffusion:drawing to diffusion:blockage, click on

Add to create a new layer purpose mapping. This is not necessary unless you are viewing
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Routing Your Design
the data being interpreted incorrectly (such as in the above case, diffusion is being
recognized as a routing layer and is showing up as a short between source and drain)
and therefore can be left blank.
The Add New Layer Mapping form displays.
4. Select the layer from the Lpp field and the purpose from the Purpose field.
5. Click OK.
The inserted layer map and its purpose is displayed in the Layer Map form.
6. Select the layer and its purpose from the Layer Map form.
7. Click OK.
8. Click the Options button next to the Pre-load Environment Variables field to specify the
environment variable options.
A form is displayed allowing the user to select data initialization options. To know about
the options in the form, refer to the Pre-Load Environment Variables Form section.
9. Click OK.
10. Specify the TCL file in the Initialization Script field. This script will be sourced before
routing starts and is useful for additional setup that you need to do before routing.
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Routing Your Design
11. Click OK.

The Global route assigns layer densities based on db.design_type. If the design is too
congested, the layer densities can be changed by specifying the global route options. By
default, all layers will use the default densities determined by db.design_type and only
overwrite the values of the layers that have been changed from the default one. If all the layers
are changed, all layers that have Use Global will use the All Layers value. Again, if a particular
layer has been changed from Use Global, it will use that specific value for that layer.
1. Click the Edit button next to the Global Route step in the Automatic Routing form.
The GlobalRoute form displays.
2. Choose the Reset Global Route option to reset the congestion map.
3. Select the density of the layers. You can specify the density for one or all the layers in the
GlobalRoute form. This is useful if the layer is too congested for routing to complete. By
default (All Layers: Default and <Routing Layer>: Use Global), the default settings in
global route will be used. The override settings can be done for all layers at once.
All Layers
poly1
metal1
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80%
Use Global
Use Global
38

Routing Your Design
metal2
metal3
Use Global
Use Global
This will set the target density to 80% for all layers. You can set a global value and
override it for each individual layer.
All Layers
poly1
metal1
metal2
metal3
80
Use Global
70%
Use Global
Use Global
This will set the target density for all layers but metal1 to 80% and metal1 will be 70%.
4. Click OK.

1. Click the Edit button next to the Local Route step in the Automatic Routing form.
The LocalRoute form displays.
2. Select the Escape All Layers option to escape pins that are there on all routing layers.
3. Select the option Vias Must be Fully Enclosed in Pin Metals if you want the via metal to
be fully enclosed within the pin metal.
4. Specify the layer name if you want that only the pins on the specified layers should have
pin metal fully enclosing the via metal in the Vias Must be Enclosed on Layers field.
5. Click OK.
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Routing Your Design

1. Click the Edit button next to the Detail Route step in the Automatic Routing form.
The Detail Route form displays.
2. The Large Space Checking option is selected by default. To select the check level,
uncheck the Large Space Checking option. The Check Level field is enabled and you can
now select the check level. By default, the highest level of checking is selected.
3. Select the Test for Convergence option to debug the script and verify if constraints are
correct.
4. Select the Use Effective Width of Overlapping Shapes option to effectively merge the
shapes.
5. Select the Critic option if you want to straighten the wires by removing unnecessary same
layer jogs in the entire top cell.
6. Select the Check Antenna option if you want to check for process antenna violations for
the entire design, a specific net, or nets in a set, an area, or a set.
7. Select the Maximize Cuts option to attempt to pack more cuts in an overlap area.
8. Select the Prefer Violations over Opens option to route guides even if it creates a
violation while routing.
9. Select the Snap to Pin Center option to connect to the center of the pin.
10. Select the pin strapping layer. By default, the metal layer is selected.
11. Click OK.
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Routing Your Design

1. Click the Edit button next to the Refinement step in the Automatic Routing form.
The Refinement form displays.
2. Choose which Refinement Options you want to enable.

To work properly, the appropriate constraints must already be set for the error types you
want to fix.
3. Choose the Align Vias to Edges of Wires to align the edge of the via metal with
the edge of the wire metal.
4. Choose the Crossing option to have the router attempt to eliminate routes on the same
net from crossing over each other.
5. Choose the Minimum Area option to have the router to fix minArea rule violations.
6. Choose the Minimum Edge Length option to have the router attempt to fix
minEdgeLength violations.
7. Choose the Minimum Enclosed Area option to have the router to fix
minEnclosedArea rule violations.
8. Choose the Minimum Width option to have the router to fix minWidth rule
violations.
9. Choose the Minimum Number of Cuts option to have the router to fix
minNumCut violations.
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Routing Your Design
10. Choose the Port Shorts option to fix the port short violations. This option is
deselected by default.
11. Choose the Reduce Vias to have the router attempt to reduce the number of vias
by increasing the number of small same layer jogs. This option is deselected by
default.
12. Choose the Reduce Wire Notches at Pins to attempt to remove wire to pin
notches. This option is deselected by default.
13. Choose the Routing Grid option to fix the routing grid violations.
14. Choose the Fix Extensions option to fix the vias metal extension violations. This option
is deselected by default.
15. Choose the Minimum Spacing option to have the router attempt to repair spacing
violations.
a. Choose the Repair Opens option to attempt to close any opens caused by fixing
spacing violations. This may cause the rerouting of multiple nets and may leave
opens if the repair was not successful.
16. Choose Minimize Unprotected Vias option to improve manufacturability by
opportunistically adding multiple cut or large enclose single cut vias.
a. Choose the No Push option to keep the router from pushing wires in an attempt to
create space for a protected via (double-cut or larger enclosure single-cut via).
17. Click OK.
Design Rule Violations

Given the following choices
1. Complete a connection, but create a DRC violation.
2. Do not complete a connection and leave an open to avoid creating a DRC violation.
The router will prefer to leave opens rather than creating violations. The user can set the
option Prefer Violations over Opens in the Detail Router options form to direct the router close
opens at the expense of leaving violations. The Router will still leave opens for some
violations such as shorts or for blocked pins.
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Routing Your Design
Routing Scripts
An existing routing flow can be captured in the form of TCL routing commands within a TCL
script. You can run this TCL script to view the routing results. To execute a TCL script, perform
the following steps.
1. Choose the Route - Routing Scripts menu item. Alternatively, with the Route menu
displayed, you can press the R key on your keyboard to display the Routing Scripts
form. The Routing Script form is a routing script specification and execute form.
2. In the Routing Scripts form, specify the TCL script name that you want to execute. You
can select an existing TCL script by clicking the Browse button. The selected script will
be displayed in the Script field and in the box below the field.
The Routing Scripts form supports a search path mechanism. After entering the script
name and clicking OK or Apply, it will look for the script in the look-up hierarchy. The lookup will stop after finding the script. The look-up hierarchy is as follows:
Current Directory
Current Directory /rde
Current Directory /.cadence/dfII/rde
Home Directory/rde
$INSTALLDIR/samples/rde
When setting the INSTALLDIR environment variable, the INSTALLDIR environment

variable must be defined as <Virtuoso software installation directory>/
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Routing Your Design
tools/dfII. The provided sample routing scripts are located in <path to the
Virtuoso software installation>/tools/dfII/samples/rde directory.
There are six sample scripts which are provided:
template.routeMatchedLength.tcl
template.makeM1BlockageOverDevice.tcl
template.routeBus.tcl
template.routeShield.tcl
template.routeDiffPair.tcl
template.routeSymmetric.tcl.
The script names will not appear in the GUI. However, if the $INSTALLDIR is defined
then by typing the script name into the Script field it will be found, executed, and the full
path and script name will appear in the box below the Script field.
3. The Operate on Current Design option is selected by default. This option runs the
(rdeOpenCurrentDesign nil) SKILL command before the script is executed. The
script will use the current open design and ignores a read_db command in the TCL
script to open a design to operate on. However, if the Operate on Current Design option
is deselected and no design is open, the read_db command will be executed in the TCL
script to open a design. After the script has finished executing, you will see an (rdeEval
checkpoint nil) near the bottom of the CIW text output window.
4. Select the Checkpoint and Return option to run the script and close the routing session.
To run the script and leave the routing session open, select the Checkpoint option. This
is useful when you have multiple scripts to run sequentially and do not want to restart the
routing session every time. When sequential scripts are run, all scripts but the last should
be run with Checkpoint selected, and the last script should be run with Checkpoint and
Return selected.
5. Click OK. The routing commands contained within the specified routing script will be
executed.
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Routing Your Design
Tie Shielding
Ties shield wires to shield nets in the design and allows you to set the tie frequency. Tie
frequency is the distance between the ties. To specify the tie frequency, perform the following
steps.
1. Choose the Route - Tie Shield... menu item. The Tie Shield form is displayed.
2. In the Tie Frequency group box, specify the distance between the shield ties and the
distance between the coax shield ties in the Shield and Coax fields, respectively.
Note: The number to the right of the spin boxes is the largest minSpacing value in the
design. If the color of the number is red, the current setting in the spin box is smaller than
the largest minSpacing constraint value. You are then likely to violate the minSpacing
on layers with larger minimums. Best practice is to set a value greater than or equal to
this number, in which case the number is black.
3. Click OK.
Deleting Routes
To delete the routing information and shielding wires from your design, display the Route
menu as follows.
1. Choose the Route - Delete Routing menu item or the Delete Routing icon in the
toolbar.
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Routing Your Design
Alternatively, with the Route menu displayed, you can press the D key on your keyboard
to display the Delete Routing form.
2. The Delete Routing form allows you to keep the routed power nets by selecting the Keep
Routed Power Nets option.
Note: If you choose to delete power routes, multi-part paths (MPPs) are also deleted.
3. Click OK.
You can also access the Delete Routing command from the RMB menu in the Navigator
assistant. For more information, refer to Deleting Routing on a Net in the Virtuoso Layout
Suite XL User Guide.
Highlighting Locked Nets

To highlight the locked nets (associated shapes), click the highlight icon
on the Spacebased Router tool bar. Clicking the icon a second time removes the highlight.
When you select a net from the navigator window or from the layout canvas, you can Route,
Lock, or UnLock that net from the right mouse button options. For more information, refer to
Locking and Unlocking Nets in the Virtuoso Layout Suite XL User Guide.
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4
Congestion Analysis
Congestion analysis determines layer utilization after global or detailed routing. The analysis
is a ratio between the number of routed wires and the number of available tracks per grid cell
for each routing layer.
A congestion map is a two dimensional grid for each routing layer in the design. Each grid cell
is called a GCell. The gcells store the data used to compute the congestion of the design area
it covers. The following data are stored.
Demand - the number of tracks needed for routing
Blockage - the number of blockages that overlap the tracks in the gcell
Capacity - the maximum number of routing tracks
The congestion value at a given location is computed by taking the maximum congestion
value on the layers. For example, if at a grid location the following congestion data exist, M1
= 80%, M2 = 90%, M3 = 85%, M4 = 95%
The display congestion of M1 and M2 and M3 is 90%
The display congestion of M2 and M4 is 95%
When computing a layer maximum congestion value, only the vertical and horizontal data of
the gcell are taken into account.
Congestion Analysis Specification

1. Choose either the Route - Congestion Analysis menu item or the Congestion Analysis
icon in the toolbar.
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Congestion Analysis
Alternatively, with the Route menu displayed, you can press the c key on your keyboard
to display the Congestion Analysis form.
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Congestion Analysis
2. Choose Automatic or User Defined to define the size of the GCell.
Number of tracks/GCell determines the size of the GCell. Track pitch is defined by width
+ spacing in the foundry rules. Changing the number of tracks makes the GCell larger or
smaller.
Automatic allows the router to determine the optimal size of the GCell. User Defined
allows you to enter the number of traces to define the size of the GCell.
3. If you change the number of tracks, you can Re-Compute with the new value.
4. Select the View congestion in design checkbox to display the congestion map in the
design window. After you click Apply to calculate congestion, this field turns the
congestion map on or off.
5. The Display Color section shows the color and pattern associated with each percentage.
You can enter a different percentage to associate with any of the color/patterns.
6. Define where the 100% congestion falls in the scale by moving the slider bar.
7. You can limit congestion data considered when performing analysis to data in the
Horizontal direction, the Vertical direction, or consider both directions during analysis.
8. In the Layer Selection section, you can limit congestion analysis to any of the layers by
selecting/unselecting the check boxes.
9. Once the analysis is defined in the form, click the Apply button.
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Congestion Analysis
January 2011
50
5
This chapter describes how to set options for the Virtuoso wire editing capability and how to
create wire interconnect.
Introduction to Wires
Setting Up the Wire Editing Environment
Using Vias
Support for Voltage-Dependent Rules
Working with Wires
Creating a Wire
Creating a Diagonal Wire
Creating a Floating Wire
Creating Wires Snapped to Track Patterns
Editing Wires
Working with Buses
Creating a Bus Constraint
Autopicking Bus Bits
Creating a Bus
Restarting a Bus From Existing Routes
Using the Control Wire
Point to Point Routing
Guided Routing
Guided Single Wire Routing
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Guided Bus Routing
Smart Snapping in Interactive Wire Editing and Assisted Routing Commands
Finishing Connections
Finishing a Wire
Finishing a Net
Composing and Decomposing Trunks
Displaying Wire Summary
Selecting Wiring Objects
Connectivity For Top Level I/O Pins
Editing Routed Connections
Introduction to Wires
This section covers the following concepts:
Types of Wires
Wire Elements
Wire Parameters
Types of Wires
You can create a wire using Paths or Segments (pathSegs). The different types of wires you
can create include:
Geometric Wires
Symbolic Wires
For information about how to create these wires, see Creating a Wire. For information about
how to distinguish between the two types of wires, see Differentiating Between Geometric
and Symbolic Wires.
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Geometric Wires
Geometric wires are created using paths, pathSegs, and vias that are not contained within a
route. Paths cannot be placed in routes, therefore, paths are always geometric data.
Geometric wires can be created in L, XL, and GXL. Geometric wires are used for special
routing (power, ground, clock, and so on). Geometric wires can be used to create custom
interconnect that auto signal routers do not modify when re-routing, ripping-up, and pushing
wires. The autorouter does not create, delete, or re-route geometric data but it may connect
to geometric data.
Geometric wires correspond to the DEF SPECIALNETS statement definition.
Symbolic Wires
Symbolic wires are created using pathSegs and vias that are contained within routes. They
are not supported in L and can be created only in XL and GXL. Symbolic wires are typically
used for signal routing, which is the default for creating wires in Virtuoso. The Virtuoso Spacebased router only creates well-formed symbolic wires with matching end points.
Symbolic data can be modified by pushing wires by using DRD and automatic routing. The
Point to Point, Guided Routing and automatic router create symbolic wires. The Finish
Wire and the Finish Entire Net commands are available only for symbolic wires.
Symbolic wires correspond to the DEF NETS statement definition.
Differentiating Between Geometric and Symbolic Wires
In XL, if you enable DRD Mode and Enable Pushing in the DRD Options form (Options
DRD Edit), any geometric wires and shapes and fixed/locked wires (even if symbolic) are
dimmed if you start the Create Wiring Wire or the Create Wiring Wire command.
This is illustrated in the figure below. In the DRD Options form, DRD modes Enforce and
Notify and Enable Pushing are selected. The blue wire is a geomteric wire created on
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neta. If you try to create a symbolic wire on netb, represented by the red wire in the figure
below, the blue geometric wire is dimmed.
Wire Elements
Wire elements include paths, pathSegs, and vias. The description of each element as it is
used when creating wires is as follows:
Paths
Using paths to create wires creates geometric data. Paths support anyAngle mode.
When used to create non-orthogonal routing, paths can lead to off-grid vertices
depending on the width and angle being used. Paths are not supported by Encounter as
a route element. You must use pathSegs instead of paths when saving data to
Encounter.
PathSegs
When pathSegs are created in routes (in XL/GXL), the data is symbolic. When pathSegs
are not created in routes, the data is geometric. PathSegs can be used to create on-grid
45 degree wires. The width of a diagonal pathSeg is manipulated to force vertices of the
perimeter on grid. PathSegs cannot be used for any-angle routing and are limited to
orthogonal and diagonal routing.
Vias
Two types of vias are supported: standard vias and custom vias.
The standardViaDefs has a unique name and is associated with two layers and a list
of via parameters with default values. It is a predefined device, generated based upon
the value of its parameters. When creating wide wires, standard vias support via arrays.
Rows and columns of vias are placed based on the area of metal overlap. Standard vias
also allow you to edit the cut pattern of via arrays.
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The customViaDefs has a unique name and is associated with a master cellview and
two layers. A customViaDefs is a special purpose via. The lib/cell/view is
declared in the technology file for the custom via.
Wire Parameters
Width is one of the important parameters os a wire. The default wire width is determined from
the minWidth constraint that can be set in different types of constraint groups. For
information on constraint group precedence, see Constraint Groups.
When tapping a wire, if the Tap Attributes option in the Layout Editor Options form is on,
the width of the new wire is determined from the width of the wire being tapped, provided it is
compliant with the minWidth and maxWidth constraints.
For information about wire width when starting from pins, see Setting the Wire Width to Match
Pins.
This section covers the following topics:
Overriding Default Width Values For a Session
Overriding Default Width Values By Using a Constraint Group
Setting the Wire Width to Match Pins
Setting Up Fixed Width Wires
Overriding Default Width Values For a Session

You can override the default wire width for each layer for the current session by specifying a
value in the Width field of the Create Wire form. After the default value is overridden for a
specific layer, the specified width value is used throughout the session. You can click the
Defaults button on the Create Wire Form or select the Use Width Derived from
Constraints option from the Create Single Wire Context-Sensitive Menu to reset the current
wire width to the minWidth constraint as defined in the technology file. However, the override
value is still used for new wires that you create in the current session.
Caution
Clicking the Defaults button on the Create Wire form resets all the
override specified values in the form, so use it with extreme caution.
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To override the minWidth constraint and set the width of wires to a specified width for all the
layers, select the Fixed Width check box. For more information, see Setting Up Fixed Width
Wires.
Overriding Default Width Values By Using a Constraint Group
You can create a constraint group to override the default minWidth and minSpacing values
and attach the constraint group to a specific net or nets.
1. Create and load a constraint group.
The constraint group in the following example is called wide. The width and spacing
values in the wide constraint group are greater than the minWidth and minSpacing
values in the foundry constraint group.
;( group
[override] )
;( --------------- )
( "wide
"nil
spacings(
(
(
(
(
(
(
(
(
(
(
(
(
minWidth
minSpacing
minWidth
minSpacing
minWidth
minSpacing
minWidth
minSpacing
minWidth
minSpacing
minWidth
minSpacing
"Metal1"0.3 )
"Metal1"0.17 )
"Metal2"0.48 )
"Metal2"0.3 )
"Metal3"0.48 )
"Metal3"0.3 )
"Metal4"0.48 )
"Metal4"0.3 )
"Metal5"0.48 )
"Metal5"0.3 )
"Metal6"0.48 )
"Metal6"0.3 )
) ;spacings
2. In XL, choose Window Assistants Navigator.

This opens the Navigator assistant.
3. Select the net for which you want to override the default values.
4. Choose Window Assistants Constraint Manager.
This opens the Constraint Manager.
5. Click the Process Rules Editor icon
The Process Rules Editor window opens.

6. Ensure that the required net is selected in the Process Rule Editor.
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7. From the Apply Constraint Group list, select the constraint group that you created and
loaded earlier.
8. Click the blue arrow button to attach the constraint group to the net.
The window updates to show the User-Defined constraint group.
9. Click the plus sign to display the values in the constraint group.
10. Exit the Process Rule Editor.
The width and spacing values set on the selected net will be used when routing the net
interactively or automatically.
Setting the Wire Width to Match Pins
Right-click the mouse button when the Create Geometric Wire or the Create Wire
command is active. Select the Use Width command on the right-click context menu to display
the options. This command also appears on the Create Bus Context-Sensitive Menu.
Note: In VLS L, only Derived from Constraints and Last Specified options are available.
Choose a width option for the wire to match the required pin edge width or default the wire
width to the value defined in the constraint group. Matching the wire width to pin edge width
applies while creating either a single wire or multiple wires. The width change is not
implemented if it introduces a clearance violation. The new wire width will be used as you
continue to create the wire.
Setting Up Fixed Width Wires
The default width of the wire is determined from the constraint group selected in the Layout
Editor Options form. Using the Fixed Width option on the Create Wire form allows you to
create wires on multiple layers while maintaining the specified width. Specify the desired
width of the wire in the Width field.
Note: If you select the Use Width Derived from Constraints option from the right-click
context menu, it will unset the Fixed Width option.
While digitizing points to create the wire, add vias to change layers. When adding vias to
wires, an array of vias can be placed to equal the width the wire. Only standard vias can be
automatically arrayed to the width of the wire.
For information about changing layers, see Changing Layers and Selecting Vias. For
information about creating via arrays, see Creating an Array of Vias.
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Setting Up the Wire Editing Environment

This section describes the following,
Startup Warnings
Mouse Button Controls
Configuring Wire Editing Options
Layout Editor Options Form
Stretch Form Options
Tapping Wires
Tapping Internal Nets
Tapping Vias
Tapping Results Based on validVias and validLayers
Adding the lxStickyNet Property to Wires
Using Wire Editing Environment Variables and SKILL Functions
Startup Warnings
Warning or error messages may be issued when invoking a command for the first time due to
the loading of data into memory. These messages will appear only once and serve to indicate
the issues that have been found with the current data, such as technology file and design
constraint discrepancies.
Mouse Button Controls

Clicking the right mouse button opens a context-sensitive menu at the point of click. The
commands available on the context menu depend on the currently active command.
When the Create Wiring Wire or Create Shape Geomteric Wire command
is running, clicking the right mouse button opens the Create Single Wire ContextSensitive Menu. You can quickly select the required via, re-adjust the width for wire
creation, or fine-tune the wire options.
For information about bindkey controls that appear on the right of various commands on
the context menu, see Appendix C, Bindkey Keyboard Map in the Virtuoso Design
Environment User Guide.
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When the Create Wiring Wire or Create Shape Geomteric Wire command
is running:
Pressing the arrow keys allows you to pan across the cellview in four directions.
Pressing the space bar key places a via or opens the Select Via Form. If only one
layer and one via are available for selection, a via is placed and the layer is changed
to the only available layer. If the current routing layer has more than one layers
available for selection, the Select Via form opens so you can choose a layer or via
type.
When you are creating multiple wires, clicking the right button invokes the Create Bus
Context-Sensitive Menu for bus routing-specific options.
Configuring Wire Editing Options

You can set up wire editing options in:

Choose Options Editor to open the Layout Editor Options Form. The fields relevant for
creating and editing wires include options in the Wire Editing, Tap, and Snap to Track
sections.
The Wire cyclic field in the Wire Editing section allows the selection of one of the available
constraint groups, which may be defined at the technology or the design level. The constraint
group defines the appropriate layers and vias for the application being used. Only the layers,
vias, and any rules specified in the selected constraint group are used when creating wires.
Selection of a constraint group in the Wire cyclic field specifies the application default
constraint group for wire creation and editing commands.
Important
Existing wires are not adjusted based on changes to the constraint group in the Wire
Editing section. The recommended flow is to set the constraint group at the
beginning of a session and to not change the constraint group while you are working
on a design. To vary the constraints on different nets, set desired constraints on
specific nets by using the Process Rule Editor.
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If you update the constraint group while working on a design, remove the existing
results (delete all routing) that would be effected by the constraint group change and
re-route.
To override constraints in the application default constraint group at the design level,
1. Create a new design constraint group.
2. Inherit the application constraint group in the design constraint group.
3. Add new constraints (the ones that you need to override) in front of the linked application
constraint group.
4. Select the new design constraint group as the application default constraint group in the
Wire cyclic field.
All container objects in the database have a default constraint group associated with them.
Creating a rule override directly on a net or on the design requires adding that rule to the
default constraint group of the net or the design. CST is the constraint look-up mechanism to
determine the precedence of constraints applied at various levels. The precedence order
followed by the router is:
a. net default constraint group
b. global net default constraint group
c. design default constraint group
d. foundry constraint group
In VLS L, logical connectivity is not taken into account when stretching wires. If DRD is on,
DRD uses logical connectivity to flag or avoid shorts.
Choose Edit Stretch to open the Stretch Form.
Tapping Wires
For a description of the Layout Editor Tap options, see Layout Editor Options Form.
For more information about selecting the starting and target object layers, without tapping an
object, see Smart Snapping in Interactive Wire Editing and Assisted Routing Commands.
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When creating a wire, layers can be selected by clicking on an LPP in the LSW or by tapping
on objects. You can select to tap the objects layer and/or attributes. In the Layout XL or higher
applications, in addition to object attributes, an existing net name can be tapped.
Note: If a setup constraint group is being used, this constraint group will control which layers
can be tapped. Additional constraint groups that define interconnect layers must contain the
same layers or a subset of the layers as those in the setup constraint group.
There are two different tap options, one is used when creating shapes and the other is used
when creating wires.
Options Layout Editor Auto Tap - Wire

Turning on Auto Tap Wire will automatically tap an objects layers and attributes when
digitizing the first coordinate of a wire. Layers that can be tapped are determined from
the technology file.
When using the Layout L editor, available layers are determined from the viaDefs
statement. When using the Layout XL editor or higher applications, valid routing layers
should be specified in a setup constraint group. When tapping an object, only layers
specified in the setup constraint group can be tapped.
Options Layout Editor Auto Tap Shape

Turning on Auto Tap Shape will automatically tap an objects layers and attributes
when digitizing the first coordinate of a rectangle, polygon, path, circle, donut, and
ellipse. All layers can be tapped.
To tap an object or automatically set the layer when digitizing the first coordinate of a wire on
an existing wire or object, turn on Auto Tap Wire in the Layout Editor Options form.
The level of hierarchy that you are allowed to tap is dependent on the Display Levels set in
the Display Options form.
To tap specific layers purposes, create a prioritized list through the Tap Purpose List on the
Layout Options form, or through the environment variables, useTapPurposeList and
tapPurposeList. The default purpose is drawing, which can be overridden through Tap
Purpose List.
For example, when Tap Purpose List is:
drawing
net
The default purpose for metal1 is drawing.
When tapping an object on the LPP metal1 net, the active layer is changed to metal1
net.
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When tapping an object on an LPP which is not listed the Tap Purpose List, such as
metal1 pin, the active layer does not change. The last layer chosen remains the active
layer.
Once you have chosen a purpose for a layer, whether through the LSW or through tapping an
object, the purpose will be used for subsequent create commands. If the layer has not yet
been used in the current command, the current purpose will be used.
Tapping Internal Nets
When tapping on a pin that is at a lower level of the hierarchy, the connectivity must be
traceable to the top level in order for the connectivity to be applied. This corresponds to the
MUST connect relationship.
In Example 1 below, the pin gnd! at level 2 in the hierarchy is connected to net gnd!. At the
top level there is a net gnd! and a pin gnd! to which the lower level gnd! is connected. In
this case tapping on the pin at level 2 in the hierarchy will return correct net information.
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In Example 2 below, when tapping on one of the A pins in I1, which is connected by internal
net net5, the net information cannot be traced to a top level term/instTerm. In this example,
no net name will be given to the new object being created.
.
Example 1
I2
Pin:
gnd!
Net:
gnd!
Pin:
gnd!
I1
instTerm:
gnd!
Terminal:
gnd!
Pin being tapped
Example 2
I2
Pin:
gnd!
Pin:
A
I1
Net:
net5
Net:
gnd!
Terminal:
gnd!
Pin being tapped
If a net information can not be traced up to a top level net, then warning messages will be
output to the CIW. If the wire does not have a net name, the software is free to merge the wire
to another wire that does not have a net name at the top level. The result of such merge may
not be the desired results. Therefore, it is advisable to manually cancel out the command
when warning 105200 or 1050201 messages appear.
Tapping Vias
In Virtuoso L, when you click a via or a stacked via, you are prompted with the Choose object
to tap from form to choose a layer from which to extend a wire from the via.
In Virtuoso XL and GXL, when you click a via or a stacked via, if there is an existing segment
connected to one layer of the via, the resulting layer tap will be on the unoccupied layer of the
via. However, in some situations, you may want to tap on a via and create a T-junction, rather
than extend a wire from a dangling end of a wire.
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To change the default behavior of Virtuoso XL and GXL and be prompted with the Choose
object to tap from form when tapping a via, do the following.
1. Select Options Editor.
The Layout Editor Options form opens.
2. Select the Select from Overlaps and Include All (Wire) Via Layers check boxes.
The associated environment variables are:
envSetVal("layout" "layerTapPickWireVia" 'boolean t)
envSetVal("layout" "layerTapPick" 'boolean t)
Tapping Results Based on validVias and validLayers

When tapping on an object, any via listed in the validVias constraint can be placed in the
design and the resulting wire will be started on a layer that is listed in the validLayers
constraint.
For example, if the validLayers are M2 and M3, and the validVias are M1M2 and
M3M4, when tapping on a M1 or M4 shape, you must choose between M1 and M4 even
though the valid layers are M2 and M3. The router can drop either a M1M2 or M3M4 via
because they are both listed in the validVias constraint and the resulting wire would be
started on a valid layer. Layers are only auto selected when there is only one available option.
Stacked vias are also allowed. In the example above, if an M4M5 via was also included in the
validVias, then tapping on an M5 shape would be allowed.
In the same example of validLayers being M2 and M3, if two shapes were overlapping,
one on M3 and one on M4, then the wire would start on M3 shape without choice. The reason
is that it would require an M3M4 via to have the M4 shape on a legal layer, but doing so would
short with the existing M3 shape, hence M4 would not be an option.
Adding the lxStickyNet Property to Wires

The lxStickyNet property allows a shape to retain the assigned connectivity.
In the Virtuoso environment there are two types of nets, known and unknown nets.
known nets: nets that are defined by pins and components.

In the Virtuoso XL and GXL editors, if a shape which is not assigned to a net, touches a
shape on known net, the shape is assigned to that net. When the net assignment is
defined by pins and components (instTerms), the assignment can not be re-assigned.
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unknown nets: shapes that are not assigned to a net

When a shape touches nothing, it is considered a floating shape.
When specifying a net name for a floating shape in Virtuoso L, the shape is given
the lxStickyNet property and the property is displayed on the property form.
When specifying a net name for a floating pathSeg created in a route in Virtuoso XL
and higher, the route is given the lxStickyNet property and the property is not
displayed on the property form.
The autorouter will assign the lxStickyNet property to routes created as

pathSegs created in routes.
The power router does not create pathSegs in routes, however the shapes will be
assign the lxStickyNet property. When a shape is removed from connecting
shapes the net name is retained.
Only one element needs to be marked sticky on a floating island for all the elements
to retain the assigned net.
Not assigned
to a net
S-netA
D-vdd
G-netB
In this example, known nets are those of the device's

instTerms (component net assignments, netA, netB, and
vdd.
The unknown net is the power rail. The power rail is not
connected to the device, the layout editor extractor is free
to assign and reassign the shape to a net.
In the Virtuoso XL editor and higher, to manually assign
a net to the power rail shape and not allow the extractor
to re-assign to a net, first assign the lxStickyNet property
then assign a net name, The power rail will retain is
connectivity.
Using Wire Editing Environment Variables and SKILL Functions

For detailed information about environment variables, see Appendix B, Interactive Wire
Editing Environment Variables in this book and Appendix B, Environment Variables in the
Virtuoso Layout Suite L User Guide.
For wire editor-related environment variables, see Wire Editor SKILL Functions in the
Virtuoso Layout Suite SKILL Reference.
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Using Vias
This section describes,
Specifying a Valid Via List
Changing Layers and Selecting Vias
Fanning Out Wires to Vias
Using Via Assistance
Creating an Array of Vias
Stacking Vias
Specifying a Valid Via List

The vias that are available for wire editing and creation are determined from the Via
constraint group specified in the Create Via section in the Layout Editor Options form.
Only the vias specified in the validVia list in the selected constraint group will be used when
creating wires. See Constraint Groups for more information about defining constraint groups.
In addition to standard and custom viaDefs, the interactive and automatic wire editing
commands, including Create Wire, Point to Point, Guided Routing, Finish Wire, and
Finish Entire Net support standard and custom via variants.
Note: Interactive wire editing does not support table-based validVia constraintS.
For information about adding customized vias to the technology file, see Technology File Via
Definitions and Via Specifications in the Virtuoso Technology Data ASCII Files
Reference.
Changing Layers and Selecting Vias

For more information about creating wires, see Creating a Wire.
To change the wire layer while creating a wire:
I) By using the Via Up and Via Down commands on the Create Single Wire Context-Sensitive
Menu when the Create Geometric Wire, Create Wire or Create Bus command is active:
1. Start the Create Wire or the Create Geometric Wire command.
2. Start creating the wire by digitizing the wire points.
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3. Right-click to select Via Up or Via Down to change the wire layer to a higher or lower
layer, respectively.
4. Continue digitizing points on the new layer.
1
10
11
12
1-12 represent the digitized points of the wire.

4, 7, and 9 represent the via digitization points, where the wire changes to a different layer.
5. Complete the command by pressing Esc.

Notice that the center of layer enclosures of the created vias coincides the intersecting
centerlines at the endpoints of the two wire pathSegs on different layers. This is shown
in the figures below. The first figure shows a zoomed-in view of point 7 of the wire above
and the second figure shows the zoomed-in view of point 9.
Center of the via layer enclosures overlapping the

intersecting endpoints of the two pathSegs
II) By using the Select Via command on the Create Single Wire Context-Sensitive Menu when
the Create Geometric Wire, Create Wire or Create Bus command is active:
1. Start the Create Wire or the Create Geometric Wire command.
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2. Start creating the wire by digitizing the wire points.
3. Right-click to select Select Via or press the Spacebar key.
The Select Via Form appears.
4. In the first column, click the target layer button to select the layer you want to change the
wire to.
The via in the second column is selected by default when you click the corresponding
target layer.
Note: If you select a different via from the cyclic field, click the target layer again to
confirm the layer selection.
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If you move the pointer to the layout window now, a preview of the via appears. The
Select Via form remains open until you digitize the via.
5. While the Select Via form is open, you can click other target layers.
Clicking more than one target layer until a via is digitized creates a via stack. At this point,
you can do one of the following:
a. To change the vias in the via stack, click other target layers.
b. To remove the via stack, click the current layer button. All vias from the pathSeg end
being dragged are removed.
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6. In the Select Via form, click the Rotate Via(s) Cut Pattern button to rotate the via
shape.
7. In the Via Alignment section, select the Automatic check box. The Via Alignment
options are also available on the right-click context menu.
Notice that the via now aligns to one side of the existing pathSeg.
8. In the design window, click at a point to digitize the via location.

The Select Via form closes. Notice the change in the via alignment with respect to the
existing pathSeg when you move the pointer to either direction of the pathSeg.
9. Digitize a few wire points.
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10. Right-click to select Select Via or press the Spacebar key.
The Select Via Form appears.
11. In the first column, click the target layer button to indicate the layer you want to change
the wire to. In the second column, select one of the available vias from the cyclic field.
12. In the Override section, click one of the custom alignment buttons. The Via Alignment
options are also available on the right-click context menu.
13. In the design display area, click at a point to digitize the via location.
The Select Via form closes. Notice the via alignment stays constant with respect to the
existing pathSeg when you move the pointer to either direction of the pathSeg.
14. Digitize a few wire points.
15. Complete the command by pressing Esc.
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The figure below shows the resultant of using automatic and custom via alignment
options.
Via Alignment: Automatic
Via Alignment: Override (Top Right)
If only one layer and one via are available for selection, you can press the Spacebar key to
place the vias. The layer changes to the only available layer. If the current routing layer has
more than one layer available for selection, the Select Via Form opens where you can choose
a layer or via type.
Fanning Out Wires to Vias

When wires are at the minimum wire spacing but the via spacings are larger, the wires can
either be fanned out to connect to the vias in the specified pattern or can be back tracked to
intersect the previous segment in the wire. This is controlled by using the Fan Out to Vias
command on the Use Spacing sub-menu on the Create Bus Context-Sensitive Menu.
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Using Via Assistance

Via assistant helps determine a legal via site location where you can add a via during routing
and not violate design clearance rules.
To enable via assistance:
The Create Via constraint group in the Options Editor form must contain the
constraints horizontalPitch and verticalPitch. For example,
routingGrids(
( horizontalPitch
( verticalPitch
"metal1"
"metal1"
2.4 )
2.4 )
Interactive Mode must be set to Enforce in the Options DRD Edit form.
Both Place Via(s) at Last Click and Enable Via Assistance must be selected in the
Create Wire form (Create Geometric Wire form in XL/GXL).
The last digitized point of the wire being routed must be off the routing grid.
Note: Via assistance does not apply to multiple wire editing and is available only to pathSegs
in XL/GXL (Create Geometric Wire and Create Wire commands).
Creating an Array of Vias

The spacing of cut layers and the minimum number of cuts allowed in a via array can be
defined in the technology file. For more information, see viaSpacing and minNumCut.
Only standard vias can be automatically arrayed to the width of the wire. The number of rows
and columns in the array are determined by the width of the wire. The following example
display standard via arrays placed on wires.
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The figure below shows an array of standard vias placed at a ninety degree intersection of
layers.
The software determines the number of cuts that are required based on the width of the wire.
The technology file standard via definition allows you to specify the default number of cuts for
a via, however, this value is overridden by the number of columns and rows needed for the
width of the wire currently being created. For example, if the default number of cuts is 2x2 but
the wire width is less than the width of a 2x2 via array, a single via cut is placed on the wire.
Stacking Vias
Note: To move individual vias in a stack you must use the Move command. The Move
command un-stacks vias.
The via stacking limit for specified layers and the minimum area allowed for stacked vias can
be defined in the technology file. For more information, see viaStackingLimits.
To stack vias, do the following:
1. Choose Create Wiring Wire.
2. From the right-click context menu, choose Select Via.
The Select Via form appears, which displays all the available vias and routing layers
that can be reached from the current routing layer.
3. Set the default via for each layer. For each layer, choose the desired via for a target layer
from the cyclic field beside each layer.
You can change any number of defaults before clicking on a layer button. You can also
raise the Select Via form, change the default vias and click OK without selecting a via.
Note: In most cases your design rules require you to place vias with extended overlaps
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when stacking vias. If the minArea constraint is set in the technology file, the via that
meets the constraint requirements will be placed. See Minimum Area Rules on page 75.
4. From the Select Via form select the desired nonadjacent layer.
To cancel any pending vias, click on the current layer button. You can rotate pending vias
by pressing the right mouse button. This is reflected in the button prompt text in the CIW
and on the layout window.
5. Move the pointer and click to place the via stack.
Via stacking adheres to the stack via depth rule, maxStackVias.
Minimum Area Rules
Extended overlaps (vias with the area of the bottom layer expanded) for stacked vias are used
to satisfy minimum area rules (MAR) for intermediate metal.
m4 is the top layer of m3-m4 via instance
via cut of m3-m4 via instance
m3 is the enlarged bottom layer

m2 is the enlarged bottom layer
Metal 4
Metal 3
Metal 2
m1 is the bottom layer
Metal 1
Support for Voltage-Dependent Rules

Voltage-dependent rules are critical for design processes at 45 nm and less. The support for
these rules is based on the ability to use user-defined layer purposes that represent voltage
ranges and to define design rule constraint groups within these voltage ranges.
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To support these rules, you can define purpose-aware constraints, such as those for width,
spacing, and clearance, in the technology file. Purposes are used to propagate the voltage
information, though without any connectivity; nets drawn on such purposes are, therefore,
called pseudo nets.
The wire editor and the Wire Assistant support the voltage-dependent rules. You can use
the voltage-aware, non-drawing layer purposes to create wires, buses, and vias. If you add a
via and switch to a higher or a lower layer, the voltage-specific purpose is propagated to the
higher or lower layer as you continue the wire or bus creation. The pseudo-net wires you
create comply with the voltage-related spacing rules.
You can tap a wire on a voltage-specific layer-purpose pair and create new elements on the
same voltage-specific layer-purpose pair.
Note: The purpose-aware constraint groups are not supported by the assisted routing
commands, such as Point to Point Routing, Guided Routing, Finish Wire, and Finish
Entire Net.
The following figure shows a section from a sample technology file where the voltage-related
purposes are defined along with the parent purposes from which they are derived.
techPurposes(
;( PurposeName Purpose# Abbreviation [Attributes]
;( ----------- -------- ------------ ------------
;User-Defined Purposes:
( lowVoltage
12
lv
'parent "drawing" 'voltageRange (0.0 1.8)
( highVoltage
13
hv
'parent "drawing" 'voltageRange (1.8 18.0) )
) ;techPurposes
For more information about the techPurposes section of the technology file, see the
Virtuoso Technology Data ASCII Files Reference.
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The figure below shows these voltage-specific purposes appearing in the Layers assistant:
The section below from the sample technology file sets up a voltage-related constraint group.
;( group
[override] )
;( -----
---------- )
( "LPPtestSetup"
nil
interconnect(
( validLayers ( ( Metal1 highVoltage) ( Metal2 highVoltage)
( Metal3 highVoltage) ( Metal1 lowVoltage) ( Metal2 lowVoltage)
( Metal3 lowVoltage) ( Via3 all) ( Metal4 all) ( Via4 all) ( Metal5
( Via5 all) ( Metal6 all) ) )
( validVias
(M3_M2_new
M2_M1_new
all)
M3_M2_std M2_M1_std) )
) ;interconnect
);LPPVolatgeSetup
For more information about the purpose-aware validLayers constraint of the technology
file, see the Virtuoso Technology Data ASCII Files Reference.
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From the Seed Attributes From a Constraint Group list on the Wire Assistant toolbar, you
can select the voltage-related constraint group so that the voltage-related layer-purpose pairs
from only that constraint group can be set in the Override Constraints section.
The following sections from the sample technology file illustrate the voltage-related rule
setups.
spacings(
( minWidth
"Metal1"
( minWidth
("Metal1" "lowVoltage") 0.33 )
0.3 )
( minWidth
("Metal1" "highVoltage") 0.34 )
( minWidth
"Metal2"
( minWidth
( minWidth
( minWidth
"Metal3"
( minWidth
( minWidth
0.4 )
0.5 )
);spacings
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spacingTables(
;( constraint
layer1
;(( index1Definitions
[layer2]
[index2Defintions]) [defaultValue] )
;( table) )
;( ---------------------------------------------------------)
( minVoltageSpacing
(( "voltage"
"Metal1"
nil
nil ))
(
0.0
0.38
1.8
0.39
3.3
0.4
)
)
( minVoltageSpacing
(( "voltage"
"Metal2"
nil
nil ))
(
0.0
0.48
1.5
0.49
3.3
0.5
)
)
( minVoltageSpacing
(( "voltage"
"Metal3"
nil
nil ))
(
0.0
0.58
1.5
0.59
3.3
0.6
)
)
);spacingTables
For more information about the minVoltageSpacing rule, see the Virtuoso Technology
If there are voltage-dependent rules defined in the technology file, the wire editor applies
them based on the following precedence, in the order specified:
Layer rule with voltage-dependent purpose > Voltage spacing rule with spacing dependent
on the voltage values specified for one layer or two layers > Layer rule with parent purpose >
Layer rule
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The override value specified in the Create Wire or the Create Bus form takes precedence
over the value specified in the technology file if the override value complies with the rule.
For example, for Metal1, the technology file contains the following spacing rules:
minVoltageSpacing
minSpacing (Metal1 0.3)
minSpacing [(Metal1 drawing) 0.35]
minSpacing [(Metal1 lv) 0.33] and minSpacing [(Metal1

hv) 0.35]
In addition, the Bit Spacing value (distance between the centerlines of bus wires) specified
in the Create Bus form is 0.
In the absence of any override value, the wire editor derives the spacing between the bus
wires as per the following lookup precedence:
For lowVoltage (lv) layer purpose:

minSpacing (Metal1 lv) > minVoltageSpacing > minSpacing (Metal1
drawing) > minSpacing (Metal1)
For highVoltage (hv) layer purpose:

minSpacing (Metal1 hv) > minVoltageSpacing > minSpacing (Metal1
drawing) > minSpacing (Metal1)
Consider a cdsVia device with a Contact Layer purpose, such as open, that does not have
a parent purpose defined in the technology file and the purpose is not voltage-related. If you
instantiate this cdsVia to change a wire from one layer to another, the purpose of the cdsVia
master device is retained. You can verify this by checking the Cut Purpose field in the Edit
Via Properties form for the cdsVia. For example, the following cdsVia device is installed in
the technology file:
name: M1_M2_Via1
layer1 purpose1: Metal1 drawing
cutLayer cutPurpose: Via1 open
layer2 purpose2: Metal2 drawing
Create a wire on Metal1 drawing and create the cdsVia M1_M2_Via1 to switch to Metal2
drawing. If you check the properties of the created cdsVia, you will notice the following:
Metal Purpose: drawing
Cut Purpose: open
Other Purpose: drawing
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For information about installing and creating cdsVias, see Support for Voltage-Dependent
Rules in Virtuoso Layout Suite L User Guide.
Working with Wires

The Create Geometric Wire enables you to create paths, pathSegs, and vias that are not
in routes. The Create Wire command enables you to create pathSegs and vias that are in
routes. You can define the wire characteristics by using the Layout Editor Options Form and
the Create Wire form. You can also define wire characteristics by using the Wire Assistant
while creating the wire. All these settings override the values in the application constraint
group that you specify in the Wire Editing section of the Layout Editor Options form. The
override values are persistent in the current session.
Before creating wires, ensure that the following requirements are satisfied:
The required layer and via definitions exist in the technology file. For more information,
see Technology File Requirements.
The required settings for wires are configured. For more information, see Setting Up the
Wire Editing Environment.
This section covers the following topics:
Creating a Wire
Editing Wires
Creating a Wire
You can create two Types of Wires: geometric and symbolic.
1. To create geometric wires in L, XL, or GXL, select Create Shape Geometric Wire.
Press F3 to open the Create Bus Form.
To create symbolic wires, supported only in XL and GXL, select Create Wiring Wire.
Press F3 to open the Create Wire Form.
You can use one of the following alternative methods to invoke the command and then
press F3 to open the respective form:
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Click the Create Wire icon
Right-click at any free space in the design canvas to display the Layout context
menu and select Create Wire.
on the Create toolbar.
Note: The above alternative methods in XL and GXL open the Create Wire Form.
2. (Geometric only) Select Paths or Segments from the Create Geometric Wire form to
specify the type of wire element to be used for creating wires. For more information, see
Wire Elements.
(Symbolic) The Create Wire form, by default, uses pathSegs in route for creating wires.
3. (Optional) In the Net Name field, specify a net name for the wire.
The wire being created is assigned to the specified net. If the specified net does not exist
in the design, the net is created.
4. To change the width of the current wire, type the desired width in the Width field.
The default width displayed in the Width field is determined from the minWidth
constraint. For information about overriding the default value, see Overriding Default
Width Values For a Session.
If the command is active but the form is hidden, you can use Use Width option on the
Create Single Wire Context-Sensitive Menu to change the width of the wire or open the
form to specify a value. See Setting the Wire Width to Match Pins.
5. (Optional) Turn on Fixed Width to create wires across multiple layers with a value
specified in the Width field. For more information, see Setting Up Fixed Width Wires.
6. (Optional) Turn on Justification to control which direction to offset the path or pathSeg
from the digitized points of the path or pathSeg.
7. (Optional) To offset the wire from the pointer by a specified distance, type the offset
amount in the Offset field.
Note: Fields that expect a numeric value do not allow a blank entry. When an entry other
than a numeric value is given, a warning is issued and the offset is set to the previous
value.
8. Select the beginning and ending extension style.
(Geometric only) If you use paths to create a wire, choose truncate, round,
extend, or variable.
(Geometric and Symbolic) If you use pathSegs to create a wire, set the Begin Style
and End Style to one of truncate, extend, variable, or custom.
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The default extension is truncate for path or pathSeg endpoints, and variable for
paths or pathSegs ending on a via.
Note: The begin and end style that are finally applied to a pathSeg depend on the begin
and end extension values you specify for them. For example, if you choose custom as
the Begin Style and End Style but the extension value corresponds to that of extend,
the pathSeg created will have extend begin and end styles. You can view the begin and
end style of the pathSeg created in the Property Editor assistant.
9. (Geometric only) Specify a ROD name if you want to create the geometric wire as a ROD
object. This is applicable only for Paths.
10. Choose a value from the Snap Mode cyclic field. If set to anyAngle or diagonal, you can
choose to create acute angled-wires. PathSegs do not support anyAngle snap mode.
11. Specify the via placement location.
12. Specify if you want the wire to snap to the center of rectangular pins.
13. (Only in XL/GXL - both Geometric and Symbolic) Select Enable Via Assistance for
guidance in determining legal via locations. This option requires routing grid constraints
to be defined in the technology file.
14. (Only in XL/GXL - both Geometric and Symbolic) Select Auto Terminate while creating
a wire(s) for terminating the wire(s) with a single click.
15. (Only in XL/GXL - both Geometric and Symbolic) You can choose to Probe Nets.
16. To start creating a wire, do one of the following:
In the Net Name field, specify a net name to start creating a wire in empty space in
the design display area. See Creating a Floating Wire.
Pre-select an I/O pin before starting the Create Wire command and then digitize
subsequent points.
Area select a pin (I/O pin or Soft Block pin), via, path, or wire to tap the layer and
attributes to define the starting point of the wire. Digitize the wire. For more
information about tapping objects, see Tapping Wires.
(Only in XL/GXL) To use the smart snapping feature of wire, switch on the Smart
Snapping command on the Create Single Wire Context-Sensitive Menu.
For more information, see Smart Snapping in Interactive Wire Editing and Assisted
Routing Commands.
Note: While creating a wire from a top-level pin, the smart snapping feature ignores
the access direction of the pin. When starting a wire from an instPin, the smart
snapping feature respects the access direction of the instPin. If the access direction
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of the instPin is nil, all directions (top, bottom, left, right) are available for starting
the wire.
During the Create (Geometric) Wire command, flightlines are displayed between
current net targets. The flightline from current the pointer position to the closest
target dynamically updates as the pointer moves.
Starting
Pin
Target
Pin
Flightline
Wire Creation
Pointing to the in Progress
Target Pin
Flightline
Target
Pin
For floating wires, select a layer from the LSW. For more information, see Creating
a Floating Wire.
In Virtuoso Layout Suite XL and higher, when starting a path or pathSeg from an
existing path or pathSeg, the starting point is snapped to the centerline of the tapped
path or pathSeg. In Virtuoso Layout Suite L, the starting point remains as digitized.
17. For information about changing layers, see Changing Layers and Selecting Vias.
18. To remove the last segment of a wire, use Backspace.
Multiple wire editing supports Undo, Redo, and Backspace.
19. To finish the wire, see Finishing Connections.
You can use Smart Snapping on the Create Single Wire Context-Sensitive Menu to snap
the wire to the target pin. The wire snaps only to pins that are on the current layer and
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on the same or an unassigned net. If the pin is on the same net as the wire, smart
snapping auto-terminates the wire by adding a segment to the snapping point.
The Create (Geometric) Wire command allows starting or finishing wires in open space, at
locations in the design where there are no objects. The Create (Geometric) Wire command
also allows starting or terminating wires on existing pathSegs to create "T" connections.
Note: In the DRD Options form (Options DRD Edit), if DRD is enabled and Interactive
Display is set to Halos, a halo is created around a wire that is being created or edited if the
wire violates a spacing constraint. The halo created around the wire is not uniform. If there
are 2D spacing tables in the technology file, the halo spacing on the edges of the wire is
based on the length of the wire, whereas the spacing on the ends of the wire is based on the
width of the wire.

When creating geometric wires, you have the option of using paths or pathSegs as elements
of the wire. Using Segments (pathSegs) allows you to create a string of joined path-like
objects with the assurance that the mask outline of the wire is on the manufacturing grid,
including points where adjacent pathSegs join. Using paths to create wires does not assure
that the paths are on grid, since paths can be created in anyAngle mode.
PathSeg end styles are automatically adjusted so that they are in accordance with the
manufacturing grid. End styles are adjusted to extend style. When reshaping a pathSeg the
same adjustments occurs; the resulting pathSegs will be adjusted to adhere to the
manufacturing grid.

To create a wire in the empty space in the design display area:
2. Press F3 to open the form.
The Create Wire Form appears.
3. In the Net Name field, type in a net name for the wire.
4. In the Layers assistant, select a layer for creating the wire.
5. Digitize points where you want to route the wire.
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Snapping wires to track patterns is supported in Virtuoso Layout Suite L, XL and GXL. When
Snap To Track is on in the Layout Editor Options form, you are allowed to create wires
only in the area where there are intersecting horizontal and vertical tracks. When stretching
wires, if more than one linear section is selected, snapping to track is disabled.
The objects that are snapped to grids include wires, paths, and pathSegs. The following
commands support track pattern snapping:
Create Wiring Wire
Edit Stretch
Edit Move
For displaying and creating track patterns, see the Virtuoso Layout Suite L User Guide.
To snap wires to track patterns, do the following:
1. Choose Options Layout Editor.
2. In the Layout Editor Options form, select the Snap To Track check box.
3. Select the desired routing layer and choose Create Wiring Wire.
The pointer snaps to the closest track or track intersection. All wire elements snap to
tracks; paths, pathSegs and vias.
If existing wires are snapped to tracks, the wires can be edited and snapped to tracks using
the Move and Stretch commands.
Editing Wires
This topic covers the following sections:
Editing Wire Properties
Editing Via Properties
Editing Cut Patterns
Multiple Wire Editing
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Editing Wire Properties
To display or modify a wire element, follow these steps:
1. Select wire element you want to edit and choose Edit - Properties [q].
The attributes of the selected wire element display in the form. If all elements of the wire
are selected, they can be accessed using the Next and Previous buttons on the Edit
Properties form.
2. Click the Next or Previous buttons to choose a specific element of a wire.
3. Type or select new values for the wire element and click OK.
For information about editing properties, see Editing and Defining Properties, in the Virtuoso
Layout Suite L User Guide.
The following tables shows the attributes of wire elements, which can be modified.
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PathSeg Element Attributes
Attribute
Modifiable
Layer
Yes
bBox
No
Width
Yes
Begin Point
Yes
End Point
Yes
Begin Style
Yes
End Style
Yes
Begin Extension
Yes
End Extension
Yes
Constraint
No
Route Status
Yes
Part of a Route
No
Connectivity
Net Name
No
Net Criticality
Yes
Property
propertyName
Yes
Path Element Attributes

Attribute
Modifiable
Layer
Yes
bBox
No
Points
Yes
Width
Yes
Type
Yes
Route Status
Yes
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Attribute
Modifiable
Part of a Route
No
Connectivity
Net Name
No
Net Criticality
Yes
Property
propertyName
Yes
Editing Via Properties

For information about editing properties of vias, see Editing and Defining Properties in the
Editing Cut Patterns
Only standard vias are supported when editing the cut pattern of a via array.
To modify a cut pattern, follow these steps:
1. Select standard via array you want to edit and choose Edit Properties [q].
The Edit Via Properties form appears.
2. Click on Edit Cut Pattern.
The Edit Cut Pattern form appears and the current pattern for the via array is displayed.
3. Select one of the following:
Click Quick Edit and select a predefined pattern from the Patterns cyclic field.
Click Wall Paper and select a predefined pattern from the Patterns cyclic field.
Further edits can be made by turning on or off the buttons of the pattern to edit the
array.
Click Manual Edit and turn on or off the buttons of the entire array pattern.
4. Click OK in the Edit Cut Patterns form to update the data of the via array.
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Multiple Wire Editing
Multiple wire editing is allowed in Virtuoso Layout Suite XL and higher tiers.
Each net involved in multiple wire editing can have its own constraints. If a net is part of a bus
or bundle, constraints can be specified on the bus or bundle to share the same constraints.
Net-based constraints are supported, providing the ability to have different widths in the wires
in a bus, or different spacings between different pairs of adjacent wires in the bus.
Wires created follow the applicable constraints for the nets to which each individual wire
belongs.
If two adjacent wires in the bus have different spacing requirements, the larger value is
used.
If there is a taper rule constraint specified on a terminal, a wider or narrower wire width
will be routed within the specified taper window.
If there is a minimum extension constraint, wire ends connecting to vias are adjusted
appropriately.
For information about finishing multiple wire connections automatically, see Finishing
Connections.
Working with Buses

You can create a bus in L, XL and GXL tiers of the Virtuoso Layout Suite by using the Create
Wiring Bus command. All wires of the bus, referred to as bus bits, are created on the
same layer. When you change the bus layer, all bus bits change to the same layer.
For creating a bus, ensure that the technology file contains the minimum information, such as
complete foundry rules, and that the non-default or override constraint groups, if any, are
specified in the Wire Assistant or in the Create Bus Form. A wiring constraint group
(virtuosoDefaultSetup or LEFDefaultRouteSpec) that defines the valid layers and
the vias allowed for routing must be present in the technology file.
Note: In some cases, the pointer is prevented from moving to a location where the bus would
necessarily have violations. This is because the wires within the set are intended to be correct
by construction.
You can either directly refer to the procedure described in Creating a Bus or go through the
following topics sequentially:
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Creating a Bus

You can create a bus constraint by using the Constraint Manager and the Search assistant.
The bus constraint helps to group all nets to be routed as a bus. The Create Bus command
recognizes the bus constraint. The Create Bus command starts routing the bus if you start
digitization from any one of the bus pins. This feature is also known as autopicking the bus
bits. For more information, see Autopicking Bus Bits.
The Constraint Manager is available only XL tier onwards. So you can use the bus
constraint for creating a bus only XL tier onwards. For information about how to create a bus
in L tier, see Creating a Bus.
To create a bus constraint in XL and GXL by using the Constraint Manager:
1. From the layout cellview, choose Window Assistants Constraint Manager.
The Constraint Manager assistant opens.
2. From the layout cellview, select Window Assistants Navigator.
The Navigator assistant opens.
3. From the Navigator assistant, select several nets that you want to route as a bus.
Alternatively, you can also search for nets in the design by using the Search assistant.
4. In the Constraint Manager assistant, click on the arrow next to the Constraint
Generator icon.
Constraint Generator
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5. Select Routing Bus.
6. Expand the created constraint to verify the selected nets are part of the bus.

When a selected net is part of a bus constraint, autopick determines the other nets of that bus
constraint on the same layer as the picked net and adds one object of each net to the pick
set. If there are pre-routed nets from pins and instPins, autopick picks these wires as well and
creates duplicate wires on top of the pre-existing wires.
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Note: Autopick does not support pre-existing wires or dangling wires even if the associated
nets are part of the bus constraint.
For information about how to create a bus constraint, see Creating a Bus Constraint.
If you start the Create Bus command and click a single pin that belongs to a bus constraint,
the command automatically enables bus mode. In the example below, a bus constraint is
defined on neta, netb, and netd.
neta, netb, and netd

Part of a Bus Constraint
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After starting the Create Bus command, if you click on pind, autopick adds pina and pinb
to the pick set.
If you area select pind, pinc, and pinb, then pind and pinb, being part of the bus
constraint, start routing in the bus mode. pinc is not picked even though it was included in
area selection because it does not belong to the bus.
Autopick does not pick instPins that belong to different instances. For example, nets A, B and
C are part of a bus constraint. Nets A and B have associated instPins on the instance I0 and
net C has the associated instPin on the instance I1. In this case, autopick on net A from
instPin on instance I0 will pick and draw wire for net B on instance I0. Autopick will not pick
instPin on net C as it belongs to a different instance I1, even though net C belongs to the
same bus constraint as nets A and B.
To remove nets from an autopicked bus while the Create Bus command is running, keep the
Ctrl key pressed and click on the required pins. To add nets to a bus while the Create Bus
command is running, keep the Shift key pressed and click on the required pins. In the above
example, to route only neta and netb, keep the Ctrl key pressed and click on pind to
remove it from the pick set.
Note: You cannot run he Finish Entire Bus command if you pick and route only a subset of
the bus nets. For information about the Finish Entire Bus command, see Finishing a Net.
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The Create Bus command uses the following criteria to determine the objects that are
autopicked:
Autopicked instance or top-level pins have the following same parameters as the clicked
instance or top-level pin:
Direction in, out, or inout
instTerms on different nets
Autopicked objects are on the same LPP as the clicked object.
In a set of objects that can be autopicked, preference is given to objects in the following order:
Aligned instPins (x or y axis)
Closest instPins
instPins with the same access direction (top, bottom, left, right)
If autopick fails to find adequate objects, you might need to complete the pick set manually.
Creating a Bus
You can start creating buses from the following starting points:
From a point in free space
From existing pins
From pre-existing bus pre-routes (see Restarting a Bus From Existing Routes)
To create multiple floating wires, see Creating a Floating Wire.

To create a bus:
1. Launch L, XL, or GXL tier of the Virtuoso Layout Suite.
2. Select Create Wiring Bus or click on the icon
3. Press F3.
The Create Bus Form opens.
4. From the Layers assistant, select a layer on which you want to create the bus.
5. Specify the values in the Number of Bits, Bit Spacing, and Width fields.
6. To start creating a bus in the empty space in the design display area:
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a. Click at a point in the design display area to digitize the bus.
b. Continue to digitize the bus and create bends.
c. Press Enter to finish creating the bus.
7. To create a bus that has connectivity in the empty space in the design display area:
a. In the Create Bus form, in the Net Name field, specify the list of net names
separated by commas or spaces.
You can also specify net names in bus notation. For example, if you specify
bus<0:3> in the Net Name field and start bus creation in free space, the bus wires
are created on the nets bus<0>, bus<1>, bus<2>, bus<3>.
If the nets specified in the Net Name field do not exist in the design, the nets are
created. Using this method, you can create floating buses.
b. Select the Create Bus Constraint check box if you want a bus constraint to be
created automatically for the picked or the specified nets.
c. Click at a point in the design display area to digitize the bus.
d. Continue to digitize the bus and create bends.
e. Press Enter to finish creating the bus.
8. To start creating a bus from existing pins, use one of the following methods to select
multiple pins:
Note: In XL and GXL, if you select the pins in one of the following ways and start the
Create Wire command, the command starts in the bus mode.
a. Selecting Multiple Pins
When you area-select multiple pins that are on the same layer but different nets, the
pin nets are used for creating the bus wires; the pin nets are populated in the Net
Name field in the Create Bus form.
The starting pins can be I/O pins or Soft Block pins. You can area-select level-0 pin
shapes or visible level-1 instPins (The Instance Pins check box should be selected
on the Display Options form). You can also start routing related nets in bus mode
when top-level pin shapes are pre-selected.
If the pins are on different layers, the Create Bus command begins wires from the
routing layer that has the most number of pins. If some of the selected multiple pins
are on the same net, then routing begins from only one pin on the net.
b. Adding Pins to the Selection
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Select a single pin and Shift + click to add additional pins to the selection.
In both the above methods, you can use the Ctrl and Shift keys to remove
objects from the selection.
Note: The pin is removed only from the picked set; the originally selected set
remains intact. You can use the Ctrl and Shift keys only before the first digitized
point. To modify the selected set after the first point is digitized, press Esc.
c. Autopicking Pins Belonging to a Bus Constraint (in XL and GXL)
By creating a bus constraint, you can define the nets to be routed as a bus. Clicking
one of the bus pins starts routing all the bus nets in bus mode. For more information,
see Creating a Bus Constraint and Autopicking Bus Bits. Even pre-selecting a bus
pin that belongs to a bus constraint and then starting the Create Bus command
starts routing all the bus pins that belong to the same bus constraint. For more
information about creating a bus from existing routes, see Restarting a Bus From
Existing Routes.
Note: The bus wires start at pin centers.
9. Right-click to display the Create Bus Context-Sensitive Menu.
If required, choose Cycle Control Wire from the context-sensitive menu to switch the
control wire function to one of the extreme wires or the center wire of the bus. For
information about control wires, see Using the Control Wire.
10. You can change width and spacing overrides at any time while creating or reshaping a
bus. Starting from the pins, wires that are not at minimum spacing are gathered to the
minimum separation at the first bend that is introduced. The default width is based on the
minWidth and the default spacing value is based on the minSpacing constraint for
each layer that can be used for routing.
Note: Routing bus bits with different widths is not supported when the Fixed Width
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check box is selected.
Bus
Cursor
11. Right-click and select Gather/Spread Bus from the Create Bus Context-Sensitive Menu
to gather or spread bus wires before the first bend of wires.
If you select Gather/Spread Bus, the bus wires are surrounded by a dotted box called
the bus cursor. Individual wires are gathered or spread inside this box, which can be
moved to any desired location. Jogs are added and the wires are gathered to the
minimum spacing rule or specified spacing value. The command on the context-sensitive
menu toggles to Ungather/Unspread Bus.
When routing a bus, each time you move the pointer, the locations of the last pathSeg
leading up the pointer are computed. If you select Ungather/Unspread Wires and the
wires are not fanned out to a via pattern, only one segment leads to the pointer for each
wire. If you select Gather/Spread Bus, jogs are added to the pathSegs to bring them
closer together if they are spaced farther than the minimum spacing.
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Pressing Backspace removes the jogs and the wires are not gathered or spread.
12. To change the spacing between multiple wires, press F3 to open Create Wire form. In
the Spacing field on the Bus tab, specify the new spacing value.
The spacing is updated from the last digitized point.
13. If required, change the bus wire width in the Width field in the Create Bus form or select
the appropriate option from the Use Width menu on the Create Single Wire ContextSensitive Menu.
The width is updated from the last digitized point.
Bus editing supports Undo, Redo, and Backspace.
Note: Do not draw wires back over previously drawn wires.
15. To change layers and add vias or to fan vias out to connect to the vias, see Changing
Layers and Selecting Vias.
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16. You can finish creating the bus at any point by double clicking or by pressing Enter. The
bus ends at the pointer location.
You can check the connectivity of the bus bits by using the Edit Properties form or the
Property Editor assistant.
For finishing the bus connections automatically, see Finishing Connections.
Restarting a Bus From Existing Routes

You can use the Create Wire or the Create Bus command to restart a bus by picking the
end-point of any of the floating bus wires that are on nets belonging to the same bus
constraint.
To restart an existing bus, where the bus wires belong to a bus constraint:
1. Choose Create Wiring Wire (XL/GXL) or choose Create Wiring Bus (L/XL/
GXL).
Note: In L, you can autopick nets of a bus constraint that has been created in XL.
2. Click at the end-point of any of the bus wires.
All the bus wires start routing on the same layer.
To restart an existing bus, where the bus wires do not belong to a bus constraint, use the wire
tie-out method, as described below:
1. Choose Create Wiring Wire (XL/GXL) or choose Create Wiring Bus.
2. Pick bus wires by area-selecting all the wires of the bus.
The Select Via Form opens.
3. Select the appropriate via for changing the bus to the required layer.
4. Specify the required via alignment.
5. Digitize the via.
The Select Via form closes.
6. Continue routing and digitizing the bus.
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The following figures shows a wire tie-out.
Note: Wire tie-out works only if the distance between the centers of consecutive wires
is large enough to create the required vias without creating a spacing violation.
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In the set of multiple wires, one of the wire segments is called the control wire. In a bus, it
stands out as being the probed/highlighted wire segment with a small yellow box at the end
of the wire segment. By default, the center wire is the control wire.
Flightline to Target Net
Probed Wire Segment: Control Wire

Yellow Box at the End of Control Wire
The control wire serves as a pivot point as the multiple wires are dragged into routing position.
The other wires of the selected bus set follow the control wire at appropriate spacing.
You can toggle the control wire role to one of the extreme wires of the selected bus. When
creating or editing multiple wires, you can cycle the control wire role to the Top-Middle-Bottom
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(in a horizontal bus) or Left-Middle-Right (in a vertical bus) wires by selecting the Cycle
Control Wire option from the Create Bus Context-Sensitive Menu.
The wire segment assigned as the control wire continues to function as the control wire even
if you select the Backup point option from the context menu during multiple wire editing. The
control wire, however, defaults to the middle wire if you add or remove (Ctrl + click) any wire
segment to/from the bus.
For example, in the following figure, the middle wire is the control wire.
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Right-click to select the Cycle Control Wire option from the context menu or press Control
+ Shift + X. The probing/highlighting and the yellow box passes on to the next possible control
wire, which is the bottom one here.
Again, select the Cycle Control Wire option from the context menu or press the combination
Control + Shift + X. It probes/highlights the top wire as the control wire.
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When multiple wires are turned on the same layer, the control wire serves as the pivot point
for turning the bus and determining the route. The following figures illustrate this.
Middle Wire Segment is the Control Wire
Point where you click and turn the wires
For best results, move the pointer over the yellow box at the end of the control wire when
digitizing points for multiple wires. This reduces conflicts and allows better control of wire
placement.
Flightlines are drawn from the current edited or created wires to the closest targets. Flightlines
in a bus are controlled by the flightline starting from the control wire. The flightline from the
control wire always targets the closest object, called the control target. Flightlines from other
bus wires target pins that belong to the same instance and are of the same type or LPP as
the control target. If no preferred choice target can be determined based on the control target,
the closest object is chosen as the target.
In the example below, wire on netc is the control wire and its control target is an instPin of
the instance busSub. Instance pins on neta and netb of the instance busSub are not the
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closest targets for the wires on neta and netb but they belong to the same instance as the
control target. Therefore, flightlines of wires on neta and netb are also drawn to busSub
instead of being drawn to I1.
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If, however, wire on netb is the control wire, as shown below, the only appropriate targets for
wires on neta and netc are their respective closest targets. For wire on neta, it is the instPin
a of instance I1. For wire on netc, the closest target is the instPin c of instance busSub.

Point-to-point routing is available in Virtuoso Layout Suite XL and GXL.
The Point to Point command is an interactive routing command that automatically generates
routing between two digitized points in a given cellview. The two specific locations can be the
two click points. The two points can overlap a pin, instPin, pathSeg, path, existing wires or
vias, or be in empty space. The Point to Point command uses the second digitized point to
start the consecutive Point to Point command. A point-to-point route completes only when
you double-click or press Enter.
Point-to-point routing is an acceleration of interactive wire editing when creating short local
connections, while also allowing you to maintain tight control of the routing. Long connections
can be broken down into several shorter point-to-point connections or can be completed
automatically using the Automatic Routing command to create routing that is optimal in a
global perspective.
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The Point to Point routing command generates only orthogonal wires, which includes
pathSegs and vias created in routes. Diagonal routing is not supported.
Note: You can use the point-to-point router to make a connection to geometric data (paths
or pathSegs not in routes).
Important
The Display Levels settings Start and Stop control the hierarchy depth for pointto-point routing.
To create point-to-point wiring:
1. Launch the XL or GXL level of the layout suite.
2. From the design window, select Create Wiring Point to Point or click on the icon
You are prompted to click at the first location.
3. Press F3 to open the Point to Point Form.
4. Specify a net name for the wire if you are starting from a point in open space.
When starting from a pin or shape that has connectivity, the net name of the pin or shape
is automatically picked.
For more information about selecting the starting and ending targets, see Smart
Snapping in Interactive Wire Editing and Assisted Routing Commands.
You can use the options on the context-sensitive menu to change the width of the wire to
match the width of the starting pin. Right-click in the cellview to display the Point to Point
Context-Sensitive Menu. See Setting Point to Point Wires to Match Pins.
You can also configure Point to Point settings using options in P2P Connection Type
and Assisted Routing sections in the Wire Assistant.
5. If required, you can override the default width by specifying a new value in the Width
field.
6. Use the Top and Bottom cyclic fields in the Routing column to limit the routing layers
to a subset of the full range of metal and poly layers.
Note: Taper layers can be excluded or included in the routable layer range. However, if
a layer, such as poly, is excluded and a poly pin is set up in such a way that the router
cannot ascend to metal1 immediately at the pin through a metal1-poly via, the router will
fail to connect to the poly pin. For more information about taper layers, see Taper
Constraint Group.
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7. Set up the valid and taper vias using the Vias buttons.
8. Select the Connection Type. Exact Location creates routing between the digitized
points. Shortest Connection creates routing as the shortest connection between the
digitized points using any pre-existing wires.
9. In the cellview, click on a pin or a routing element such as a pathSeg, path, or via.
Optionally, you can click in an empty area of the design. You are prompted to click at the
next location.
A flightline is drawn from the clicked point to the closest target on the specified net.
10. Click on subsequent points.

Routing is generated between consecutive digitized points.
After you digitize the second or more points:
The Net Name field in the Point to Point Form becomes uneditable.
You can edit Routing Layers. If editing the layer limit results in making the previous
point-to-point route invalid, the Point to Point command creates stacked vias
between the previous click point and the valid routing layer.
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You can edit the Fixed Width value. The updated value affects only the new
pathSegs created after changing the value.
11. To specify the ending location of the wire, double-click or press Enter. The ending
location can be a pin or a routing element such as a pathSeg, path, or via. Optionally, you
can click in an empty area of the design. A highlighted line is displayed to show the
connection between the first clicked point and the current pointer location.
This completes a point-to-point route. You are prompted to specify a new starting location
for the Point to Point command.
Note: Ensure that the start and end points of the route are within the P&R boundary
because routing is not allowed outside the P&R boundary.
The Point to Point command automatically stops for the route if:
While routing an incomplete net, you tap a shape (pin/route) that completes the net.
While routing a complete net, you tap a shape on the net.
No net is being routed (starting from empty space or unassigned shapes) and you
tap a shape on a complete net.
Routing paths are found in empty areas around objects with valid spacing rules. No
pushing is performed to make room for routing.
12. To end the command, press Esc or click Cancel in the Point to Point Form.
Note: The point-to-point router does not follow minEndOfLine spacing in cases where the
wire is floating and consequently forms an incomplete connection, as the data is still in the
midst of changes.
If the point-to-point router cannot complete a route and the Interactive Edit mode is set to
Post-edit or Notify in the DRD Options form, the router forces a route creation with
violations. The router also issues a warning message to indicate that there were violations
and that you can run Verify Design to view the markers for the violations. This enables you
to analyze the problem areas where the router could not produce a clean route.
If the point-to-point router cannot complete a route and DRD Interactive Edit mode is set to
Enforce, a warning message is issued to indicate if the router is stuck at the start or end point
or pin or if there is insufficient space to complete routing.
Setting Point to Point Wires to Match Pins

You can use the options on the Use Width command on the Point to Point Context-Sensitive
Menu to set point-to-point wire widths to match pins. The selected match pin width applies to
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all applicable routing layers of the current effective constraint group, where it does not violate
the corresponding minWidth and maxWidth constraints. The width change is not
implemented if it introduces a clearance violation.
The point-to-point pin matching option remains effective throughout the entire layout session.
Point-to-point requires two clicked points. When the pin matching option is on, the width of the
first pin selected is used. The object selected must be a pin, otherwise the width constraints
in the current effective constraint group are applied.
Guided Routing
The support for guided routing is available in VLS XL/GXL. You can use the Guided Routing
command to route a single wire as well as a bus. For more information, see Guided Single
Wire Routing and Guided Bus Routing.
The Guided Routing command enables you to specify the path a net should follow inside an
envelope. The routing envelope is created by a series of clicked points and the router
operates within this envelope. The routing envelope represents the available routing area for
the wire. You can control the routing envelope by using the pointer. From the first digitized pin,
this command creates a solid, orange-colored line to serve as a visual aid for defining the
envelope. After you digitize the end point, the command automatically routes the net inside
the envelope. Existing pre-routes (wire, bus, or vias) are valid start and end points for the
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Guided Routing command. You can start a guided route for a single wire in empty space in
the design and end a guided route for a single wire and bus in empty space.
Starting
Click Point
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Solid Line to Serve as

Visual Aid
Routing
Envelope
112
Flightline

If you perform guided routing for a wire or a bus inside a block that is enclosed by a P&R
boundary, the guided routing envelope clips to the P&R boundary. This helps to provide visual
feedback of the actual routing area being used.
P&R
Boundary
Routing Envelope Clipped to

the P&R Boundary
To perform guided routing for a wire or a bus, ensure that the technology file contains the
minimum information, such as complete foundry rules, and that the non-default or override
constraint groups, if any, are specified in the Wire Assistant or in the Guided Routing Form.
A wiring constraint group (virtuosoDefaultSetup or LEFDefaultRouteSpec) that
defines the valid layers and the vias allowed for routing must be present in the technology file.
If the router cannot complete the route and the Interactive Edit mode is set to Post-edit or
Notify in the DRD Options form (Options DRD Edit), the router forces the route creation
with violations. The router displays a warning message in the CIW to indicate that there were
violations and that you can run Verify Design to view the markers for the violations. This
allows you to analyze the problem areas where the router could not produce a clean route.
If the router cannot complete a route and DRD Interactive Edit mode is set to Enforce, a
warning message displays in the CIW to indicate whether the router is stuck at the start or
end point or pin or if there is insufficient space to complete the routing.
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Comparing Guided Routing with Point to Point Routing

The Guided Routing command is similar to Point to Point Routing. In addition to automatically
generating routing between the specified points, the Guided Routing command enables you
to specify a routing envelope. Unlike the Point to Point command, Guided Routing is not
consecutive. Single clicks in guided routing only define the intermediate points of the
envelope. You can perform consecutive guided routing operations only after committing the
command by double-clicking or pressing Enter.
In the Guided Routing command, the snap mode of the envelope is set to either L90 X First
or L90 Y First and you can toggle the envelope orientation between the two. The command
uses the Tap settings specified in the Layout Editor Options form.

To create a wire interactively, see Creating a Wire.
To perform guided routing for a single wire:
1. In XL or GXL, choose Create Wiring Guided Routing or click on the icon
Create toolbar.
on the

2. Press F3.
This opens the Guided Routing Form.
Note: You can also use the options in the Guided Routing Envelope and Assisted
Routing sections in the Wire Assistant to configure Guided Routing settings.
3. Specify the net name to use for creating the wire.
4. Specify the wire width, spacing, routable layers, and taper layers as required.
5. In the Number of Additional Tracks cyclic field, specifying the required value for
controlling the width of the routing envelope.
You can change the width of the envelope at any time while performing the guided
routing.
6. Click or area-select a pin.
After you pick the required pin, the following three are drawn:
A solid, orange line extending from the point of the click
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An envelope around the pin and enclosing the solid line
A dynamic, dotted flightline that extends from the solid line to the closest target
You can start and end a guided route in empty space in the cellview. You can also start
or end a guided route on an existing pathSeg to create a T connection.
For more information about selecting the starting and ending targets, see Smart
Snapping in Interactive Wire Editing and Assisted Routing Commands.
7. As you move the pointer and click to define intermediate points, the routing envelope, the
solid line and the flightline update dynamically.
You can click within the envelope around the starting pin. If the routing envelope is
beyond the viewing area, a visual aid displays in the artwork as an indication of the
envelope.
8. Right-click to display the Guided Routing Context-Sensitive Menu. Using the options on
the context menu, you can invoke the Options form at any time to reconfigure width or
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track settings. You can also change the orientation of the routing envelope by using the
Toggle L90 X/Y option on the context menu, as shown in the figure below.
When the pointer overlaps a target pin on the same net, the width of the last section of
the routing envelope enlarges around the pin.
9. To complete the command, double-click at the target or press Enter at the pointer
location.
The route is created within the envelope. The envelope itself is removed from the final
display.
10. The Guided Routing command remains active after you route a net. You can select a new
starting object to generate another guided route by following the above steps. The options
specified in the Guided Routing Form remain valid for the next guided routing operation.
You can update the settings if required.
11. Press Esc or click Cancel in the Guided Routing Form to finish guided wire routing.
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Guided Bus Routing

To create a bus interactively, see Creating a Bus.
To perform guided routing for a bus:
1. In XL or GXL, choose Create Wiring Guided Routing or click on the icon
Create toolbar.
on the

2. Press F3.
This opens the Guided Routing Form.
Note: You can also use the options in the Guided Routing Envelope and Assisted
Routing sections in the Wire Assistant to configure Guided Routing settings.
3. Specify the wire width, spacing, routable layers, and taper layers as required.
4. In the Number of Additional Tracks field, specify the required value for controlling the
width of the routing envelope.
You can change the width of the envelope at any time while performing the guided
routing.
5. To start digitizing the guided bus routing envelope, do one of the following:
In the Net Name field in the Guided Routing form, specify the net names in bus
notation to start creating the guided bus in empty space in the design display area.
For example, if you specify bus<0:3> in the Net Name field and start bus creation
in empty space, the bus wires are created on the nets bus<0>, bus<1>, bus<2>,
bus<3>.
Select existing pins.

You can select a single pin that is on a net belonging to a bus constraint. The
remaining nets of that bus constraint are autopicked for guided routing.
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To start routing from multiple pins whose nets are not part of a bus constraint, areaselect all the pins.
Guided bus routing started from pins
Select pre-routed buses.

You can select a bus wire that is on a net belonging to a bus constraint. The
remaining wires of that bus constraint are autopicked for guided routing.
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To start routing from multiple pre-existing bus wires whose nets are not part of a bus
constraint, area-select the bus wires. The bus wires on the same net are picked for
guided routing.
Guided bus routing started from existing

buses
After you pick the required pins or bus wires, the following three are drawn:
Multiple solid, orange lines extending from each of the selected pin or bus wire
An envelope around the pins or bus wires enclosing the solid, orange lines
Dynamic, dotted flightlines extending from the solid, orange lines to the closest
targets
6. As you move the pointer and click to define intermediate points, the routing envelope, the
solid, orange lines and the flightlines update dynamically.
7. Right-click to display the Guided Routing Context-Sensitive Menu.
Using the options on the context menu, you can open the Guided Routing Form at any
time to reconfigure width or track settings. You can also change the orientation of the
routing envelope by using the Toggle L90 X/Y option on the context menu.
When the pointer overlaps a target pin on the same net, the width of the last section of
the routing envelope enlarges around the pin.
8. In the form, select the Gather At Bend check box.
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The first and last segments of the guided bus envelope match the width of the pin
envelope they connect to. The first and last segment expand or shrink to match the
respective pin envelop width, as shown in the figure below.
Last segment
matching the
ending pin
envelope width
Click Point
First segment
matching the
starting pin
envelope width
As shown above, the pins are covered by the envelope of the connected segment. This
enables the router to route straight out of the pin.
Note: Currently, the router can gather anywhere within the wide envelope, not
necessarily at the click point. The gather frequently happens near the pins.
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If you switch off the Gather At Bend check box, the first and last segment do not match
the pin envelop width and assume the usual envelope width, as shown below.
Ending pin
envelope
Starting pin envelope
In this case, the pins are not covered by the envelope of the connected segment. This
forces the router to gather to get to a valid location within the connected segment's
envelope.
9. To complete the command, double-click or press Enter at one of the following targets:
Target pins
Pre-routed buses
Empty space in the design
The bus is created within the envelope. The envelope itself is removed from the final
display.
10. The Guided Routing command remains active after you route a bus. You can select a
new starting object to generate another guided route by following the above steps. The
options specified in the Guided Routing Form remain valid for the next guided routing
operation. You can update the settings if required.
11. Press Esc or click Cancel in the Guided Routing Form to finish guided routing for buses.
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Smart Snapping in Interactive Wire Editing and Assisted

Routing Commands
When you start Creating a Wire, you can switch on Smart Snapping on the Create Single
Wire Context-Sensitive Menu to enable snapping to the starting and target pins. You can use
the smart snapping feature with vias as well (only starting vias) when snapToViaCenter is
off (default). By default, Smart Snapping is on. To turn it off, switch off Enabled on the
Smart Snapping sub-menu on the Create Single Wire context-sensitive menu.
By using the Cycle Edge command from the Smart Snapping sub-menu, when you bring
the pointer close to the potential starting pins, the edge of the pin within the Aperture
distance of the pointer highlights. You can cycle through the available edges by pressing
Ctrl and Spacebar keys or by using Cycle Edge. Each time you press the key combination
or choose Cycle Edge, the next possible target within the Aperture distance highlights. The
length of the highlight indicates the width of the wire to be created and depends on the Use
Width option selected from the Create Single Wire Context-Sensitive Menu. To select a
highlighted edge for wire creation, click at the pointer location. Digitize subsequent points of
the wire.
You can toggle to the Use Current Position mode by pressing together the Ctrl, Shift, and
Spacebar keys or by choosing Use Current Position from the Smart Snapping submenu. In this mode, you can start or end a wire in empty space as well as from or at a pin.
Tip
To configure Aperture, change the value in the Gravity Controls section of the
Layout Editor Options form.
While creating a wire, if Smart Snapping is on and the Snap to Via Center check box in
the Create Wire Form or in the Wiring section of the Wire Assistant is selected, you can
cycle through the available via shapes by pressing Ctrl and Spacebar keys successively.
You can toggle to the Use Current Position mode by pressing together the Ctrl, Shift, and
Spacebar keys or by choosing Use Current Position from the Smart Snapping submenu. In this mode, smart snapping is turned off and you select a via by using the Choose
object to tap from form (see Tapping Vias for more information).
Note: If you select a layer from the Layers assistant before clicking a via, you can start wire
creation on the layer selected from the Layers assistant and bypass the Choose object to
tap from form. The wire snaps to the via center if the Snap to Via Center check box is
selected.
You can use the smart snapping feature while using the assisted routing commands, Point
to Point routing and Guided Routing. The smart snapping feature, while using these
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assisted routing commands, enables you to select a starting and ending layer, without
bringing up the Choose object to tap from form.
Finishing Connections
You can finish wires and buses manually by double-clicking or pressing Enter. The wire and
the bus finish at the pointer location. In XL and GXL, the Auto Terminate check box, if
selected in the Create Wire Form and the Create Bus Form, enables you to complete the
creation of the wire or the bus, respectively, on the same net object with a single click.
To complete creating the wire or bus automatically, use the Finish Wire or Finish Bus
commands on the Create Single Wire Context-Sensitive Menu and the Create Bus ContextSensitive Menu, respectively.
To use the commands for finishing a wire or net, ensure that the technology file contains the
minimum information, such as complete foundry rules, and that the non-default or override
constraint groups, if any, are specified in the Wire Assistant. A wiring constraint group
(virtuosoDefaultSetup or LEFDefaultRouteSpec) that defines the valid layers and
the vias allowed for routing must be present in the technology file.
Finishing a Wire
The Finish Wire command is available in XL and GXL on the Create Single Wire ContextSensitive Menu if you are creating a wire by using the Create Wire. The Finish Bus
command is available in XL and GXL on the Create Bus Context-Sensitive Menu if you are
creating a bus by using the Create Bus command. The command is available on the contextsensitive menu only after you digitize at least one point of the wire or the bus or after you
select the pins for the wire or bus creation.
By using the Create Wire or Create Bus command, you can digitize critical parts of a wire
or a bus manually and then run the Finish Wire or Finish Bus command to finish the rest of
the wire or bus automatically.
Note: The Display Levels settings on the Display Options form, Start and Stop, control
the hierarchy depth for the Finish Wire command.
The Finish Wire command requires a net otherwise the corresponding commands are
greyed out. The Finish Wire command attempts to complete the connection of the current
wire or bus while the Create Wire or the Create Bus command is running. The Finish Wire
command accelerates interactive wire editing while completing short-distance wires from
target pins or terminals, and at the same time, maintains control over routing by following the
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default rules. To complete long-distance wire connections automatically, use the Route
Automatic Routing command to create routing that is optimal in a global perspective.
For information about finishing a single or all the picked nets automatically instead of
completing only a wire or a bus, see Finishing a Net.
To complete a wire connection automatically:
2. Start the wire creation from level 0 pin shapes or visible level 1 instPins (Instance Pins
should be selected on the Display Options form) or from pre-existing wires.
3. Digitize some points of the wire.
If you move the pointer around, a connection that can be completed is displayed by a
flightline. This is the connection from the pointer to a single destination pin, instPin, or
existing pre-route belonging to the same net.
4. Right-click to display the Create Single Wire Context-Sensitive Menu
5. Select Finish Wire.
The Finish Wire command uses the pointer drag point as the starting point for finishing
the connection. The command calls the point-to-point router to complete the wire
connection. The control then returns to the Create Wire command and you can start
creating new wires.
6. Press Esc to finish creating a wire.
You can use similar steps to use the Finish Bus command while creating a bus.
Note: The Finish Wire command and Point to Point Routing create pathSegs in routes.
However, you can use Finish Wire and Point to Point routing to make a connection to
existing pathSegs not in routes or even to paths (geomteric wires). For information about
geometric and symbolic wires, see Types of Wires.
If the point-to-point router cannot complete a route and the Interactive Edit mode is set to
Post-edit or Notify in the DRD Options form (Options DRD Edit), the router forces a
route creation with violations. The router also issues a warning message to indicate that there
were violations and that you can run Verify Design to view the markers for the violations.
This enables you to analyze the problem areas where the router could not produce a clean
route.
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If the point-to-point router cannot complete a route and DRD Interactive Edit mode is set to
Enforce, a warning message is issued to indicate if the router is stuck at the start or end point
or pin or if there is insufficient space to complete routing.
The Finish Wire command follows the default constraints and also complies with the
overrides that have been set in the Create Wire Form or in the Wire Assistant (Override
Constraints and Assisted Routing). It also follows constraint group lookup in context.
Finishing a Net
The Finish Entire Net command is available in Virtuoso Layout Suite XL and GXL when you
are creating a wire or a bus by using the Create Wire or Create Bus command and when
one or more edited nets are incomplete.
If you are creating a single wire, the Finish Entire Net command is available on the Create
Single Wire Context-Sensitive Menu; if you are creating a bus, the Finish Entire Bus
command is available on the Create Bus Context-Sensitive Menu. The commands are
available on the context-sensitive menus only after you digitize at least one point of the wire
or bus or after you select the pins for the wire or bus creation.
The Finish Entire Net command calls the automatic router to finish all the connections of
the currently edited net. You can run the Finish Entire Bus command on a set of nets while
performing interactive bus editing to route them as a bus even if they do not belong to a bus
constraint. The Finish Entire Net command can modify any nearby net artwork that is not
locked down. When rerouting this neighboring artwork, it uses the looked-up constraint
values. Any prior override values are lost.
Note: You cannot run the Finish Entire Bus command if you pick and route only a subset
of the bus nets.
For information about finishing one connection of a single wire automatically instead of all
connections on a net, see Finishing a Wire.
To complete an edited net connection automatically:
2. Start the wire creation from level 0 pin shapes or visible level 1 instPins (Instance Pins
should be selected on the Display Options form) or from pre-existing wires.
3. Digitize some points of the wire.
4. Right-click to display the Create Single Wire Context-Sensitive Menu.
5. Select Finish Entire Net.
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The automatic router completes the connections of the edited nets. The automatic router
may remove unnecessary existing pre-routes by default. However, you can unselect the
option Remove Preroute Dangles in the Wire Assistant to avoid removing any portion
of pre-routes.
Note: The Finish Entire Net command does not comply with all the option settings in
the Create Wire form (such as Fixed Width) or on the Create Single Wire context
menu.
The control then returns to the Create Wire command and you can start creating new
wires.
6. Press Esc to finish routing nets.
You can use similar steps to use the Finish Bus command while creating a bus.
The Finish Entire Net command follows the default constraints and also complies with the
overrides that have been set in the Create Wire Form or in the Wire Assistant (Override
Constraints and Assisted Routing). It also follows the constraint group lookup in context. The
Finish Entire Net command supports the routing of diff pair, symmetry and shield nets.
Composing and Decomposing Trunks

The Compose Trunks and Decompose Trunks commands are available in VLS XL in the
Edit Wiring menu. You can also access these commands from the Shape and Multiple
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context-sensitive menus that display if you right-click in the design display area after selecting
one or more objects.
Use the Compose Trunks command to convert the selected set of shapes into a trunk
object. A message in the CIW summarizes the objects that are converted to form a trunk. This
trunk object can then be used to perform pin to trunk routing. The pin to trunk router is started
by default when you run the route command from the Net context-sensitive menu after
selecting the trunk net in the Navigator assistant.
Use the Decompose Trunks command to convert the selected set of shapes that comprise
the trunk to the original shapes from which the trunk was formed. A message in the CIW
summarizes the objects that are converted to original shapes. If the selected shapes are not
part of a trunk and you run the Decompose Trunks command, the number of converted
objects reported in the CIW is 0.
Displaying Wire Summary

To display a summary of the contents of the cellview,
Choose File - Summary.
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A window containing the summary appears.
Selecting Wiring Objects
Object Definitions
Selecting a Single Object or Via
Routing Granularity Options
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Object Definitions
Segment
(pathSeg)
A pathSeg is a shape used to realize physical routing that can either be

orthogonal or diagonal. A pathSeg has a start point and an end point.
Starting point
Ending point
Contiguous
pathSegs
Two pathSegs are contiguous when they are on the same layer and when
they have an overlapping point (start or end).
Contiguous pathSegs
Non-continuous pathSegs
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T-junction
A T-junction is a point where there are more than two contiguous pathSegs.
T-junction
Not a T-junction
Selecting a Single Object or Via

Full or partial selection (press F4) selects a single wire element or via.
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Partial selection (press F4) selects a single vertex of a wire element.
Routing Granularity Options

For selecting routing objects, you can specify Routing Object Granularity in the Selection
Options (Options Selection) form. The granularity options are supported only in the
current hierarchy and in the applications Virtuoso XL and GXL. The granularity options
include:
Shapes or Vias
Entire Wire
Connected Shapes
All Shapes on a Net
Net
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Shapes or Vias
In Shapes and Vias mode, when a via or shape that is used to make a wire is selected, only
the single object is highlighted.
Entire Wire
In Entire Wire mode, when a shape or a via is selected, the selection is extended to select
all the objects forming the wire.
Contiguous pathSeg
T-junction
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Connected Shapes
In the Connected Shapes mode, when a shape or a via is selected, the selection is
expanded to select all the objects that form a physical connection. This mode does not take
into account net assignment on shapes and vias. The selection expansion stops if more than
1000 objects are found. In the case of more than 1000 objects, only the object under the
mouse is selected.
All Shapes on a Net

In All Shapes on a Net mode, when a shape or a via is selected, the selection is expanded
to select all objects assigned to the same net. The selection expansion stops if more than
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20,000 objects are found. In the case of more than 20,000 objects, only the object under the
mouse is selected.
Net
In Net mode, the net object is selected. If a shape has no assigned net, the shape will not be
highlighted.
The net is selected in the Navigator assistant and is probed in the layout window. The method
in which the net is displayed (probed) in the layout window is determined by the Highlight
Options form. Shapes assigned to the net can be highlighted or flightlines can be displayed.
There is no limit on the number of shapes that can be highlighted.
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In Net mode, a net in the current edited cellview can be selected by clicking on any pin of an
instance, which is hierarchically connected to this net.
In Example 1: clicking on Pin A or Pin B selects the net X. Note that when net X is selected,
only the pins on level-1 are highlighted
In Example 2: clicking on Pin A selects nothing because the pin does not have a direct
connection to a top level net.
.
Example 1
I2
Pin A
Pin B
I1
Net B
Net X
instTerm A
Terminal B
Net A
Terminal A
Example 2
I2
Pin B
Pin A
I1
Net B
Net X
Net C
instTerm A
Terminal B
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Terminal A
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In Net mode, when clicking on an instance all the nets connected to the instance are selected
if there is no pin at the mouse click location. In the example below, clicking on the instance
selects the nets X, Y and Z.
.
Net X
A
C
Net Y
Net Z
Connectivity For Top Level I/O Pins

Top level I/O pins, regardless of whether they are defined to be strongly connected or weakly
connected, must be connected at current level of the design. Flight lines will show an open
between unconnected top level I/O pins.
For information about connectivity, see Using Connectivity in the Virtuoso Layout Suite L
User Guide.
Editing Routed Connections
Stretching Wires and Vias
Pushing Wires and Vias
Moving Wires
Copying Wires
Re-routing a Wire
Reshaping Wires
Removing Loops From Wires
Self-intersecting Objects
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Merging Wires
Deleting Wires
Stretching Wires and Vias

Variables that Control Stretch
Controlling the Angle of Wires
Using the Stretch Command
Preserving Paths
Stretching Wires Connected to Pins
Stretching Wires Connected to Vias
Variables that Control Stretch
Keep Connected option

The Keep Connected option on the Stretch form will allow wires that are stretched to
remain connected. See Stretch Form.
Angles of segments
Often determines when an extra segment is needed. See Controlling the Angle of Wires.
Selection of objects
Selecting one vertex in a segment leaves the other vertex alone. Selecting both vertices
in a segment causes the segment to move.
The length of attached segments may change to keep segments connected or segments
may be added to keep segments connected.
Selecting a via may cause the addition of a segment.
See Selecting Wiring Objects for more information.
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Controlling the Angle of Wires
To control the angle of wires during stretch, turn Lock Angles on to preserve the angle of
existing objects during stretch. See Stretch Form for more information. Set the Snap Mode
to Orthogonal or Diagonal, to control the permitted angles of wire objects being added.
Using the Stretch Command
The Stretch command can be used to stretch diagonal edges, intersecting wires, and
pathSegs or paths by changing the vertices XY locations. When an isolated fully selected via,
pathSeg, or path is stretched, the object is moved to a new location similar to using the Move
command.
Note: PathSegs are supported by advanced features. Advanced features such as Push are
activated when using pathSegs. Path objects are not supported by advanced features. When
stretching a path that is created by using Create Geomteric Wire, then the following
message is given:
*WARNING* (LE-105065): Advanced features will not be available because the selected
set contains one \w or more non-wire objects.
To stretch a wire, follow these steps:

1. Choose Edit Stretch.
The layout window prompts you to select a figure to be stretched. Press F3 to open the
Stretch form.
2. Select the desired Snap Mode.
Snap Mode will enforce restrictions on the movement of the pointer. For example, if one
end of a diagonal segment in a wire is stretched when the snap mode is horizontal, that
end will move only horizontally.
3. (Optional) Select Keep Connected.
When Keep Connected is on, all paths, pathSegs, and via vertices coincident with a
selected vertex will be stretched as a set.
4. (Optional) Turn Lock Angles on to preserve the current angles of pathSegs and path
elements.
Turn Lock Angles off to allow the angles to change. Path elements may be oriented to
any angle, but pathSegs can only be orthogonal or diagonal.
5. Click or area select the wire or portion of wire you want to stretch.
For more information about selection, see Selecting Wiring Objects on page 128.
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6. Move the pointer and click to place the wire element.
The Stretch command does not keep overlapping wires connected if they are on
different nets. In VLS L, overlapping wires on different nets are kept connected when
stretched if their endpoints meet exactly.
If DRD is enabled, the placement of stretch wires is verified that the resulting geometry
will follow the technology rules. This applies to via stacking as well. If DRD is not enabled,
the Stretch command will allow vias (as well as other objects) to be moved to any
location.
In the Layout L editor, logical connectivity (nets) is not taken into account when stretching
wires. When DRD is on, DRD can use net information to flag or avoid shorts.
Preserving Paths
When wires are created using paths, the stretch command will preserve the path objects and
not split the paths into separate paths when ever possible. However, there are cases when it
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is necessary to split path objects. The following examples show situations where paths will
be split due to stretching of the paths.
One continuous path.
path 1
path 2
path 3
When path 2 is stretched to the right, the top path (path 1) is split
into three separate paths.
path 1
path 3
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Path 1 is one continuous u-shaped path.
path 1
u-shape
path 2
When path 2 is stretched outside of the u-shape, path 1 is split into separate paths.
path 1
u-shape
path 2
Stretching Wires Connected to Pins

When a wire connects to a pin, the end of the wire is considered to be fixed. To disconnect a
wire from a pin, turn Stretch Keep Connected off. This will release the end of the wire
and allow you to disconnect from the pin while stretching the wire.
When a segment that is attached to a non-wire object such as a pin, and the pin is not also
being stretched, a segment is added from the end of the stretched segment back to the
original connection point in the pin only if it is necessary to maintain connectivity.
Stretching Wires Connected to Vias
Wires will remain connected to vias when the Stretch Keep Connected option is on,
whether it is a single via or a stack of vias. To move individual vias in a stack you must use
the Move command.
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When stretching a via attached to a pathSeg, the pathSeg is also stretched and the endStyle
of the pathSeg at the overlap with via is recomputed. This may result in the end styles of
pathSegs being changed.
Pushing Wires and Vias

Enabling design rule driven (DRD) along with push functionality enhances correct by
construction design. Enabling Pushing controls whether the existing wires and vias are
pushed aside while routing to maintain current clearance rules.
Static objects such as instances and blockages cannot be pushed.
Wires that are created with paths, pathSegs in routes or pathSegs not in routes, can all
push neighboring wires. However, only pathSegs and vias in routes can be pushed.
The commands Create Wire, Reshape, and Stretch will push aside existing regular
wires (pathSegs in routes) and vias.
Stretching object types such as paths, rectangles, polygons, MPPs, pcells, and so on
cannot push aside paths or wires.
If there is no P&R boundary, objects are pushed outside of the bounding box.
To turn on enable pushing functionality:

1. Select Options DRD Edit.
2. Set DRD Mode to Enforce.
Enforce stops the pointer movement when a design constraint violation threshold is
reached. When Enforce and Enable Pushing are turned on, wires are pushed aside.
3. Set the Hierarchy Depth to the level of hierarchy that you want considered during
checking.
For example, if you want DRD to consider the artwork inside a via that is being pushed,
set the Hierarchy Depth to Current & Below.
4. Turn on Enable Pushing.
5. Optionally, turn on Push Vias.
When this box is checked, pushing of vias as well as pathSegs is enabled.
6. Optionally, turn on Cleanup After Push.
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When this box is checked, objects that are modified as a result of pushing are cleaned
up to reduce the number of bends. When the box is not checked, this clean-up process
is omitted, saving time.
Note: When pushing wires where there are shielded wires, it is possible that the shielded
unit will be broken apart by the push operation. To avoid pushing apart shielded units,
lock the shielded unit (both shielded and shielding wires) by using the Lock command.
For information about setting rules for both batch checking and DRD, see DRD Options
Form in the Virtuoso Design Rule Driven User Guide. The number of rules you
check affects DRD performance.
Moving Wires
Fully selected wires or wire elements can be moved by the Move command. Wires can also
be rotated, reflected, or changed to a different layer by using Move form.
Copying Wires
Fully selected wires or wire elements can be copied by the Copy command. Wires can also
be rotated, reflected, or changed to a different layer by using Copy form.
Currently the net information is discarded when copying wires.
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Re-routing a Wire
A re-route is a type of wire editing where a new wire is started from a point along an existing
wire, and eventually reconnects to another portion of the existing wire. The portion of the
original wire made redundant by the new wire is removed.
Reshaping Wires
To reshape a wire, follow these steps:
1. Choose the type of Routing Object Granularity from the Options Selection form.
2. Select the wire to be reshaped.
3. Select Edit Advanced Reshape.
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4. Click on a segment of an existing wire to select the wire.
The existing wire is automatically tapped for layer information and attributes.
The initial starting point is the first point of the wire to be reshaped. The initial point is
snapped to the begin/end points, center-line of a segment, or to the origin of a via:
5. Digitize points where you want to create a wire and double click.
This will highlight the option of the new wiring.
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6. Middle click toggles between wire reshape options.
7. Press Return or double click to finish the desired reshape of the wire.
Removing Loops From Wires

The option Allow Loops is supported in Virtuoso L, XL and GXL.
By default, loops are removed from wires created as pathSegs. When creating or editing a
wire, a preview of the intended wire is shown. Once the intended wire segment attempts to
produce a loop, the resulting loop is removed. When editing a wire which contains a loop, the
entire wire may be removed due to loop removal.
Note: All Create and Edit commands remove loops from wires created as single path
objects.
You can allow loops in pathSegs by turning on Allow Loops in the Layout Editor Options
form. The following commands and options support loop removal.
Create Wiring Wire
Edit Stretch
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The following graphics show the loop removal when creating wire using pathSegs.
With Allow Loops off, the loop
is not allowed.
If the intended wire segment

attempts to produce a loop,
when Allow Loops on, the loop
is allowed.
With Allow Loops on, loops are allowed in the following circumstances.
Behavior
Loops are allowed
Interconnecting wires:
Creating a wire on interconnecting layers
Branching wires:
Reshaping an existing wire that contains a
branch.
In the case of a branching wire or wires, the loop is
not removed because it can not be determined
which side of the loop to remove, or removing the
loop can disconnect the wire from an intended
connection to pins or same net wires.
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Self-intersecting Objects
A single database object is not allowed to intersect itself. Paths are shaped based objects
represented by a point array and are not allowed to become self-intersecting during creation
or editing.
When an object is self-intersecting, an error message dialog box appears and the object is
not allowed to be drawn.
A single pathSeg consist of a two-point segment and cannot be drawn in a manner that would
allow self-intersection.
When creating or editing wires using paths, the edges of a path can be coincident, but not
overlap. When creating or editing wires using pathSegs, a series of pathSegs can be
stretched to cross over other pathSegs or overlap.
By default, in the cases where the pathSegs would create a loop, the loops are removed. See
Removing Loops From Wires for more information.
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The following image shows how a u-shaped path is not allowed to be stretched over itself and
self-intersect.
When the same u-shape wiring is created with multiple pathSegs, the segments of the
pathSegs are allowed to be stretched to cross over each other or overlap.
Merging Wires
The following types of conditions are supported by the Merge command. Only wires on the
same layer can be merged. Merging at segment ends which have a via is not allowed.
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Collinear Abutment or Overlap of PathSegs
Collinear abutment of pathSegs is when two pathSegs meet end to end in a straight line at
the same end point. Collinear overlap of pathSegs is when two pathSegs overlap in a
straight line.
When two collinear pathSegs are merged, the elements are converted one continuous
pathSeg. The resultant pathSeg will have the same end styles as the respective ends before
merging.
Coincident Abutment or Overlap
Coincident abutment of pathSegs is when two pathSegs meet at an angle, or in at a
T junction. Coincident overlap of pathSegs is when two pathSegs overlap at an angle.
Elements are converted to a path or polygon depending on overlap and end styles of
pathSegs.
The following table lists the combinations of end styles possible by merging pathSegs that
abut or overlap at an angle. Also stated is the situations in which merging the pathSegs
results in a polygon.
End Style of the Second PathSeg
End Stye
of the
First
PathSeg
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Truncate
Variable
Extend
Custom
Truncate
Truncate
Variable
Variable
Polygon
Variable
Variable
Variable
Variable
Polygon
Extend
Variable
Variable
Extend
Polygon
Custom
Polygon
Polygon
Polygon
Polygon
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Examples of Coincident Overlap
Resultant Path
pathSegA
Begin style: extend
End style: truncate
pathSegB
Begin style: truncate
End style: extend
pathC
style: extend
Resultant Polygon
pathSegA
Begin style: extend
End style: extend
pathSegB
Begin style: extend
End style: extend
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Merging a Pathseg with a Path
Merging a pathSeg with a path may result in either a path or a polygon.
The following table describes the combinations of path styles possible by merging a pathSeg
and a path. Also described is the situations in which merging a path and pathSeg result in a
polygon.
Style of the Path
End Stye
of the
Pathseg
Truncate
Variable
Extend
Round
Truncate
Truncate
Variable
Variable
Polygon
Variable
Variable
Variable
Variable
Polygon
Extend
Variable
Variable
Extend
Polygon
Custom
Polygon
Polygon
Polygon
Polygon
Example of Merging Paths and PathSegs
Resultant Path
pathSeg
Begin style: truncate
End style: extend
path
style: extend
path
style: extend
Deleting Wires
The Delete command can be used to delete an entire wire when the wire is fully selected.
Wires that are created on the same layer using path elements are created as a continuous
path, without intersecting vertices at corners. When deleting wires created with path
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elements, sections of the wire on the same layer can be deleted without breaks or gaps being
created.
Wires that are created on the same layer using pathSegs as wire elements are created with
intersecting vertices at corners. When deleting wires created with pathSegs as wire
elements, selected sections can be removed, breaking the wire into multiple wires if interior
pathSegs are removed.
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6
Specialty Routing
This chapter describes,
Symmetry Routing
Differential Pair Routing
Shield Routing

Constraints can be created in the schematic or layout view. For information about how to
create constraints see Creating Constraints, in the Virtuoso Unified Custom Constraints
User Guide.
When creating a constraint in the schematic view, the constraint can be transferred to the
layout view automatically or manually. See Constraint Transfer in the Virtuoso Layout XL
User Guide.
The Create Wire command does not support retroactive application of constraints (e.g.
shielding, symmetry, differential pair) after the first digitized point.
For constraints to be applied properly, a net name must be provided at the first digitized point
The net name can be supplying at the first click by clicking on a shape stamped with the net
name or by entering the name of the net in the Create Wire form before the first click.
Symmetry Routing
Types of Symmetry Routing
Defining a Symmetry Constraint
Automatic Symmetry Routing
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Interactive Two Net Symmetry and Self Symmetry Routing
Types of Symmetry Routing
Mirrored Symmetry
Mirrored symmetry involves two nets mirrored over an axis.
Self Symmetry
Self Symmetry involves a single net that is mirrored over an axis. The entire geometry
can reside on the symmetry line, in which case there are no symmetric objects.
Cross Symmetry
Cross symmetry involves two nets that are allowed to cross the symmetry line using one
or more instances of crossover cells. This type of symmetry is comparable to two
separate cases of mirror symmetry involving two pairs of nets which are part of the
original nets.
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Crossover cells are created automatically by the Analog Placer when a need for such a
cell is detected. This happens when IO pins and instTerms associated with the
symmetric net pair are placed such that a crossover can not be avoided.
Partial Symmetry
Partial symmetry can apply to nets that are mirrored symmetric, self symmetric, or cross
symmetric. Two nets that do not have the same number of terminals are considered
partially symmetric. Partial symmetry also applies when a portion of the wires are unique
on either side of the axis.
Checks are not implemented to determine if every geometry in a symmetric net has a
symmetric counterpart. Also, checks are not implemented as to whether corresponding
pieces of geometry are symmetric.
An asymmetric geometry in a symmetric net may cross the symmetry line or reside on
the opposite side of the line because there are no symmetric counterparts to cause
conflict.
The parts of a net that have symmetric counterparts can be connected with symmetric
wiring. The parts that are unique to one side of the symmetry line must be connected
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with wiring that is not symmetric, as shown in the graphic below. To route an extra
terminal, specify the specialty routing constraints in the Constraint Aware Editing mode.
Defining a Symmetry Constraint

The following steps describe how to create a basic symmetry constraint in the layout view.
These instructions assume that there is a schematic view or connectivity source associated
with the layout view.
1. From the layout cellview, select Window Assistants Constraint Manager.
3. From the Navigator assistant, select one net or pin for self symmetry routing, or two nets
or pins for mirrored symmetrical routing.
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For mirrored symmetry, select the second net by pressing the Control key and clicking
on the net or pin name. See Types of Symmetry Routing for a description of mirrored and
self symmetry constraints.
4. In the Constraint Manager assistant, left click on the arrow next to the Constraint
Generator icon and select Routing Symmetry from the pop-up window.
A symmetry constraint with default values is created.
5. You can confirm the members of the constraint by hovering the cursor over the
Symmetry constraint in the Constraint Manager window.
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6. In the lower section of the constraint manager window you will see the default symmetry
constraint.
7. Click on the + sign next to Axis to update the default constraint values.
a. Specify the axis direction for the constraint; horizontal or vertical.
b. Set the axisLocation to fixed.
c. Specify the axis coordinate parameters for the constraint.
Note: The steps 7(b) and 7(c) are required only if user wants to specify an axis that
is not the default, which runs through the centerline of the prBoundary.
For a mirrored symmetric constraint, the axis coordinate value must be determined
by calculating the center coordinate between the two symmetric pins.
For a self symmetry constraint, the axis coordinate value is the center of the self
symmetry pin.
8. In order to route wires that are partially symmetric, specify the specialty routing
constraints in the Constraint Aware Editing mode.
Automatic Symmetry Routing

When using automatic symmetry routing, it is important that your axis coordinate be correct.
In addition, the surrounding shapes, such as instances, must be symmetrical.
Use the Detailed run mode to route symmetry constraints with the automatic router.
Symmetry constraints are not supported in the global, local, conduit, and power routers.
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Be aware that the Display Levels settings start and stop control hierarchy depth for
automatic routing.
See Defining a Symmetry Constraint for information about how to create a symmetry
constraint.
Interactive Two Net Symmetry and Self Symmetry Routing

The Create Wire, Reshape, and Stretch commands support symmetry. The point-to-point
router also supports symmetry constraints.
To create symmetrical wires, follow these steps.
2. Make sure the Enable Symmetry option is turned on in the Layout Editor Options
form.
3. Generate a symmetry constraint.
See Defining a Symmetry Constraint.
4. Select Create Wire.
5. Select a pin from which you want to start the symmetrical wires.
If you need to highlight the pin, making it easier to see the correct pin to begin routing,
highlight the pin(s) using the Navigator assistant. Then, from the design window, select
the highlighted pin.
6. Digitize points for the symmetrical wires over the vertical or horizontal axis.
For self symmetry, a single wire is digitized over the axis. As the wire is digitized on
either side of the axis, another wire is created that is associated with the same net.
Both wires are simultaneously generated over the axis.
Note: When routing a self symmetric wire, enable Snap to Pin Center in the
Create Wire form. Otherwise, two wires instead of one can be generated from the
pin.
For mirrored symmetry, selecting one of the pins automatically selects the
associated pin of the symmetry constraint. As you digitized one wire, the associated
wire is digitized; simultaneously generating wires on either side of a mirror axis.
7. To finish routing the wires, you can manually digitize the wires to the destination pin, or
click right and select Finish Wire.
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Defining a Differential Pair Constraint
The following steps describe how to create a basic differential pair constraint in the layout
view.
3. From the Navigator assistant, select two nets for the differential pair.
Select the second net by pressing the Control key and clicking on the net name.
Only nets are allowed as members of Diff Pair constraints.
4. In the Constraint Manager assistant, left click on the arrow next to the Constraint
Generator icon and select Routing Diff Pair from the pop-up window.
A differential pair constraint with default values is created.
A Diff Pair constraint with default values is created. The Diff Pair constraint appears in
the constraint browser tree under Type.
5. You can confirm the members of the constraint by hovering the cursor over the Diff Pair
constraint in the Constraint Manager window.
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Changing Diff Pair Values in the Process Rules Editor

Once a Diff Pair constraint is defined you can optionally assign additional attributes in the
Process Rule Editor.
Note: It is now possible to assign Constraint Groups to a differential pair net, 'Within Group'
and 'Group to outside Group' rules, directly in the Constraint Manager that supports these
parameters. You can simply specify the layers and spacings, without using Process Rule
Editor. It is also possible to automatically generate Constraint Groups for this purpose.
To set or change the values,
1. Select the diff pair constraint In the Constraint Manager window and click on the
Process Rules Editor icon.
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The Process Rule Editor form opens and the diff pair constraint is displayed in the
browser window.
2. In the Create Process Rule field, select the type of rules and attributes you want to
override or set. For example,
a. To change the gapSpace for a diff pair,
b. Select Within Group:: Constraint: Constr_Name
c. Select gapSpace from the Create Process Rule cycle field.
d. From the Layer field, select the layer of the pair.
e. From the minSpacing field, select the gap spacing for the pair.
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f. Click the Update button at the bottom of the form.
The value of Diff Pair is updated in the Browser window.
3. When you are done setting attributes, click the Close (X) button.
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Interactive Differential Pair Routing

To create a differential pair, follow these steps.
2. Generate a Diff Pair constraint.
See Defining a Differential Pair Constraint.
3. If the Navigator window is not open, from the layout cellview, select Window
Assistants Navigator.
4. In the Navigator assistant, click on the name of the net that is a member of the Diff Pair
constraint to highlight the associated pin in the layout.
5. Select Create Wire.
6. To maintain the width of the differential pair throughout the routing, select Fixed Width
from the Create Wire form.
7. To set the width of the wire to match the pin width, see Setting the Wire Width to Match
Pins.
8. In the design window select the highlighted pin.
When starting a differential pair, the wires are temporarily snapped to the origin of pins.
When a pin is selected that is on a net with a differential pair constraint, the editor
searches for a nearby pin on the same layer as the paired net. When the pin is found, the
differential pair is started. If a pin cannot be found, a message is issued to the CIW and
the operation will not be started.
9. To gather diff pair wires before the first bend of wires, click right to open the Create Pair
pop-up menu and select Gather Wires.
The cursor changes and is surrounded by a dotted box called the bus cursor. The two
wires are gathered together into this box, which can be moved to any desired location.
The wires are gathered to the minimum spacing rule or specified spacing value.
10. To change the spacing of the differential pair,
a. Right click to open the Create Pair pop-up menu and select Spacing.
The Differential Pair Spacing menu opens.
b. In the Differential Pair Spacing menu, specify the new spacing value.
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The change in spacing will occur at the next bend if Gather Wires is off, or
immediately if Gather Wires is on.
Diff pair routing supports Undo, Redo, and Backspace.
12. To change layers and add vias, or to fan vias out to connect to the vias, see Changing
Layers and Selecting Vias and Select Via Form.
13. To finish the wires, see Finishing Connections.
Shield Routing
Defining Shield Constraints
Shield Styles
Default Shielding Types
Changing Custom Shielding Values in the Process Rules Editor
Tying Shield Wires
Pin escapes
Defining Shield Constraints

3. In the Navigator assistant, select a net by clicking on the net name.
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4. With the net selected, create the shield constraint by selecting Routing Shielding
from the Constraint Manager pull-down menu.
A shielding constraint is created. The Shielding constraint appears in the constraint

browser tree under Type.
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5. In the lower section of the constraint manager window you will see the parameters of
shielding constraint.
6. For information about the attributes used to create different types of shield constraints,
see Shield Styles.
7. For information about how to generate default shielding constraints, see Default
Shielding Types.
8. For information about how to change values in the Process Rules Editor, see Changing
Custom Shielding Values in the Process Rules Editor. You can even change values using
the Constraint Manager.
Note: When pushing wires where there are shielded wires, it is possible that the shielded
unit will be broken apart by the push operation. To avoid pushing apart shielded units,
lock the shielded unit (both shielded and shielding wires) using the Lock Navigator Nets
command.
Shield Styles
There are three types of shielding styles available depending on which attributes you choose
to set in the Process Rule Editor.
Parallel
Without adding any additional attributes in the Process Rule Editor, the default shield
type is a basic parallel shield with a shieldGap equal to the applicable layers
minSpacing and parallel shieldWidth equal to the applicable layers minWidth.
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The default values for shieldGap and shieldWidth are not displayed in the Process
Rule Editor. Once the default value is overridden with different values, they are displayed
as an attribute.
Tandem
A tandem shield (metal above and/or below shield net) can be created by setting the
tandemLayerAbove and/or tandemLayerBelow attributes along with the
tandemWidth attribute in the Process Rule Editor.
Note: If shieldGap and/or shieldWidth are also set, the result will be a coaxial not a
tandem shield.
Coaxial
A coaxial shield is the combination of a parallel and tandem shield (metal above and/or
below the shield net along with same layer shielding along side the shielded net).
Note: In order to achieve coaxial shielding it is necessary to define the shieldGap and
shieldWidth even if the values are equal to the default minSpacing and minWidth
values.
Important
In all cases, do not define shield values below a layers minWidth value. If you do
so, the shield may not appear and no warning message is given.
Default Shielding Types

Default shield types of parallel, tandem, and coaxial can be generated based on rule values
set in the technology file.
To generate and modify default shielding constraints, follow these steps.
1. Select the Shielding constraint in the In the Constraint Manager constraint browser tree
under Type.
2. In the lower Constraint Manager parameters window, click on the Shielding pull-down
window and select the desired type of shielding constraint.
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The Generate label indicates that the predefined constraint group that has not yet been
generated for the selected shielding constraint.
3. Open the Process Rules Editor to view or change the default values.
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4. The default values are displayed for each type of shielding constraint that has been
defined.
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5. To edit values, click on the Design button in the Process Rules Editor.
6. You can edit the constraint group values directly or use the copy and paste functions to
make the predefined constraint group more specific for your design.
Once a shielding type has been selected and applied, you can change the constraint type
by clicking on the constraint in the Constraint Manager constraint browser tree under
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Type. Click on the Shielding pull-down window and select a different type of shielding
constraint to be applied.
Changing Custom Shielding Values in the Process Rules Editor

Once a Shielding constraint is defined you can assign attributes in the Process Rule Editor.
To set or change the shielding style and values,
1. Select the shielding constraint In the Constraint Manager window and click on the
Process Rules Editor icon.
The Process Rule Editor form opens and the shielding constraint is displayed in the
browser window.
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2. In the Create Process Rule field, select the type of rules and attributes you want to
override or set. For example,
a. To change the shieldGap for a parallel shield, select shieldGap from the Create
Process Rule cycle field.
b. Leave distance as the value and click the blue + button to add the attribute to the
shield constraint.
c. From the Layer field, select the layer of the shield.
d. From the minSpacing field, select the gap spacing for the shield.
e. Click the Update button at the bottom of the form.
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The value of shieldGap is updated in the Browser window.
3. When you are done setting attributes, click the Close (X) button.
For information about what values to set to create different types of shielding constraints,
see Shield Styles.
If you have many nets in your design that require shielding, you can optionally create a
shielding constraint group in the technology file and apply the shielding constraint group,
using the process rules editor, to the nets requiring the same set of constraints. See Applying
a Constraint Group for more information.
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To remove or copy attributes of a shielding constraint in the Process Rules Editor, click the
right mouse button over the attribute to bring up the context sensitive form.
For more information about how to copy constraints, see Copying an Existing Process
Rule.
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Tying Shield Wires

Shield nets are not tied into power/ground by default. Once shield routing (automatic or
manual routing) is complete, use the Power Router Via options to add vias and wires to tie
in the shields.
Pin escapes
The router models a net with shielding as having a wide spacing requirement, as it takes the
widths of the shields into account. When the router tries to escape from a pin, wide spacing
is required if you do not specify a taper constraint group. If the neighboring pins have tighter
spacing than is required by the shielded net, minimum spacing for example, the router has
trouble escaping from the pin based on the default behavior of needing the wider spacing
clearance.
To work around this default behavior, define a taper constraint group with a different name
than the default constraint group used by the wire. The router will then use the spacing
specified in the taper constraint group for pin escape rather than the wide spacing of the
shielded net.
The following is an example of a taper constraint group.
constraintGroups(
;( group [override] )
;( ----- ---------- )
( "virtuosoDefaultTaper" nil "taper"
interconnect(
( validLayers (Poly Metal1 ) )
( validVias (M1_PO ) )
) ;interconnect
spacings(
( taperHalo 1.4 )
) ;spacings
) ;virtuosoDefaultTaper
;constraintGroups
Use the Technology File Manager to load the constraint group.
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7
Space-based Router Batch Checking
This chapter describes the batch checking capabilities that are available in Virtuoso XL and
GXL.
Batch Checking
Finding Violations
This chapter also covers the following checking capabilities:
Fixing Violations
Optimize Routing
Batch Checking
The batch checker offers different types of checking.
A shape-based checker that verifies the shapes against process rules specified in the
technology file, design, and object level. For more information, refer to Virtuoso Spacebased Router Supported Constraints.
A connectivity checker that verifies the design for shorts, loops and dangles.
A constraints checker that verifies the specialty routing constraints such as Diff Pair and
Symmetry.
A placement checker that verifies the placement constraints.
A routability checker that verifies the routing problems in the design.
A Fabrication checker that verifies the antenna violations in the design.
Using the Batch Checker

To open the Batch Checker form, choose Verify Design. The Batch Checker form
appears as shown in the following figure. This form has a tree widget in the left panel for the
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checks that can be performed using this form. Selecting a check in the left panel will display
its form in the right panel. By default the Process Rules check is selected.
Routability Checking
Routability checking is performed before routing. This verification is done to check the design
for the issues that can cause potential routing problems. Design rule checks applied to pins
and some routability checks are performed to determine the accessibility of pins.
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1. To perform routability checks on a design, select the Routability option. The routability
checks are displayed in the right panel of the form as shown in the following figure.
2. In the Check group box, select the check boxes for the checks you want to do.
Blockage
Checks for pins blocked by top-level blockage or blockage of another instance.
Minimum Space
Checks for pin to pin spacing less than minimum pin spacing.
Minimum Width
Checks for pin dimension(s) less than minimum pin width.
Via
Checks for pins that cannot be escaped using available vias. For more information,
refer to Check Routability commands.
3. Optionally, you can limit the number of markers for each violation type by specifying the
limit in the Markers Limit Per Type field. Alternatively, you can set the
checkRoutabilityMarkersLimit environment variable.
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The checker outputs a Routability Report that summarizes the issues found to the CIW. For
example,
Use the Annotation Browser to view the violations. Issues such as DRC violations should be
dealt with before attempting to route the design.
Process Rule Checking
Process rule checking offers a set of options that allow you to specify which portions of the
design to verify, or to specify the types of rules you want to verify. Process rule checking can
be set to check the following:
The current cellview
An area of the current cellview
A specified hierarchy depth
A selected set of process rules
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1. The Process Rules check is selected by default when the Batch Checker form is
opened. In the right panel of the form, the Process Rules form is displayed as shown in
the following figure.
2. From the Scope group box, choose whether to check the entire cellview or limit the
checking to a specific area.
3. In the Filter Options group box, set the Hierarchy Depth to the Top Level or Current
& Below.
4. In the Check For group box, select the check boxes for the process rules that you want
to check. You can limit the process rules checker to check a subset of process rules.
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When you place the mouse pointer over the check box of a rule type, you can view the
list of supported rules for that rule type, as shown in the following figure.
Info
Balloon
displaying
the
This is the same rule checking that is performed by DRD.
All
Checks for all the constraints mentioned in the process rule categories in the Check
For group box.
Spacing
Checks for the spacing constraints, such as minVoltageSpacing,
minCutClassSpacing, and so on.
Via
Checks for via constraints, such as viaSpacing, minViaSpacing, viaStackingLimits,
and so on.
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Width
Checks for width constraints, such as minWidth, maxWidth, and so on.
Area
Checks for area constraints, such as minArea, minRectArea, and so on.
Complex Spacing
Checks for complex spacing constraints, such as minEndOfLineSpacing,
minOppSpanSpacing, and so on.
Edge Length
Checks for edge length constraints such as, minLength, maxLength, and so on.
Extension
Checks for extension constraints, such as minViaExtension, minExtensionDistance,
and so on.
Num cut
Checks for num cut violations, such as minNumCut and minProtrusionNumCut.
Misc
Checks for miscellaneous constraints, such as errorLayer.
Density
Checks for density constraints, such as minDensity. maxDensity, and
maxDiffDensity.
For more information about each of the process rule category, refer to the Virtuoso
Routing IDE Command Reference.
Connectivity Checking
The connectivity verification can be limited to specific set of violation checking. You can check
for the following:
Current cellview
A selected set of nets
Exclude selected nets
Loops and dangling wires
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Exclude power and ground nets
1. To perform connectivity check on a design, select the Connectivity option. The

connectivity checks are displayed in the right panel of the form as shown in the following
figure.
2. From the Scope group box, select:
Current Editable Cellview

Checks the current cellview.
Selected Net
Checks only the nets that you currently have selected.
Exclude Selected Nets

Checks all the nets except those selected.
3. The Check For group box checks for the dangling wires and wires with loops.
4. The Filter Options group box allows you to choose whether or not to check cellview for
shorts and opens that involve power and ground nets.
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Speciality Routing Checking
Note: Geometric shapes (e.g. paths, pathSegs/vias not in a route) are not checked. A
warning will be issued when checker detects geometric shapes.
1. To perform special routing checks on a design, select the Speciality Routing option.
The special routing checks are displayed in the right panel of the form as shown in the
following figure.
2. In the Specialty Routing group box, select the type of constraint checking to be
performed.
Symmetry checks whether a symmetry axis is defined and whether the position of
the axis is correctly defined. If the axis is not considered well defined, a marker will
be generated at the location of the axis. Only routed portions of the symmetric nets
are checked and only shapes on metal and poly layers are checked.
Diff Pair checks the percentage of unpaired lengths for each net in of a diff pair.
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Placement Checking
1. To perform placement checks on a design, select the Placement option. The message
to check for the placement constraints is displayed in the right panel of the form as shown
in the following figure.
2. Check all the placement constraints that are defined for the design, which is being
verified.
Fabrication Checking
This check verifies the process antenna violations for the entire design, selected nets, or
except selected nets.
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1. To perform fabrication checks on a design, select the Fabrication option. The fabrication
checks are displayed in the right panel of the form as shown in the following figure.
2. From the Scope group box, select:
Current Editable Cellview

Checks the current cellview.
Selected Net
Checks only the nets that you currently have selected.
Exclude Selected Nets

Checks all the nets except those selected.
3. From the Antenna Oxide Models group box, select which oxide model(s) to use: First,
Second, Third, Fourth. By default, the First oxide model is selected.
Finding Violations
The Annotation Browser assistant is used for viewing and managing violation markers in your
design.
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The command relies on violation markers. For information about running violation checks,
see Using the Batch Checker.
To check for process rule violations, shorts, opens, and illegal overlap markers,
1. Run the batch checker on the design if required by choosing Verify Design.
2. Choose Window Assistants Annotation Browser or click on the Annotation
Browser icon.
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3. Click the Annotation Browser assistants Connectivity tab to view connectivity marker
violations.
The tab label indicates the total number of connectivity violations in the design. These
are separated into different categories for Illegal Layer Overlaps, Opens and Shorts
in the browser pane.
4. Click the Annotation Browser assistants Constraints tab to view process rule violation
markers.
The tab label indicates the total number of marker violations in the design. These are
separated into different categories for each type of design rule violation.
3. Click the Set Highlight State column for the entry whose flight line you want to see.
4. Click the Set Highlight Color column to set the color used to draw the corresponding
marker in the design window. Choose cycle to select the color automatically by cycling
through a predefined list.
5. Click the Set Marker Check State column to set the Checked state of the
corresponding marker. When a marker is set to Checked, you can use the Hide button
to hide it in the Annotation Browser without deleting the marker from the design window.
Note: Clicking in these columns for a particular node applies the setting for all the entries
under that node. Clicking in these columns next to the Opens entry shows all the
incomplete net flight lines in the design.
For more information on the Annotation Browser, see Annotation Browser in the Virtuoso
Layout Suite XL User Guide.
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Fixing Violations
Using the Fixing Violations option, you can perform all spacing related checks including
merged shapes and fix the violation operations for a selected area or the entire cell view.
To fix the routing violation operations,
1. Choose Route Fix Violations Options or Options Layout GXL. The Layout
GXL Options form is displayed. By default, the Fix Routing Violations tabbed page is
displayed as shown in the figure below.
You can fix any of the following routing violation operation.
Crossing - uses the setting of the fixErrorsErrorTypesCrossing environment

variable.
Minimum Area - the minimum area allowed for a shape on a specific layer. It uses
the setting of the fixErrorsErrorTypesMinArea environment variable.
Minimum Edge - uses the setting of the fixErrorsErrorTypesMinEdge

environment variable.
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Minimum Enclosed Area - The minimum area allowed for a hole in the specified
layer. It uses the setting of the fixErrorsErrorTypesMinEnclArea environment
variable.
Minimum Spacing
Repair Opens - attempts to fix the opens that were caused by spacing
violations.
Minimum Width - the minimum width for any shape on the layer. It uses the setting
of the fixErrorsErrorTypesMinWidth environment variable.
Number of Cuts - uses the setting of the fixErrorsErrorTypesNumCut environment

variable.
Port Shorts - uses the setting of the fixErrorsErrorTypesPortShort environment

variable.
Routing Grid - uses the setting of the fixErrorsErrorTypesRGrid environment

variable.
Extensions - attempts to fix all extension violations based on the extension

constraints defined in the design. For example, minOppExtension and
minExtensionEdge constraints.
The environment variable settings determine the violation types fixed. These violation
types are the same as in the Refinement tab in the Automatic Routing form. However,
settings in the Automatic Routing form have no affect on this standalone implementation
of Fix Violations.
Note: Running the Automatic Routing Refinement step sets the fixErrorsErrorTypes
environment variables according to the settings in the Refinement form. However, setting
or deselecting error types in the Refinement form without running the Refinement step
has no effect on the environment variables. For more information on environment
variables, refer to Appendix B, Environment Variables.
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Optimize Routing
Using the Optimizing Routing option, you can optimize routing in the design.
1. Choose Route Optimize Route Options. The Optimize Routing tabbed page is
displayed as shown in the figure below.
You can also open the form by choosing or Options Layout GXL. The Layout GXL Options
form is displayed. Click the Optimize Routing tab.
To optimize routing, you can select any of the following options.
Align Via to Wire Edge - moves vias such that the edge of the metal layers in the
vias overlap/align with the edges of the wires. This can reduce the number of small
notches around vias. This functionality is applicable only to vias that exist over route
segments.
Note: The stacked vias can become unstacked after via alignment.
Reduce Jogs - attempts to change nearby routing to reduce the total number of jogs.
Reduce Vias - attempts to change nearby routing to reduce the total number of vias.
Reduce Wire Notches at Pins - removes any small metal notches located near pins
by shifting the wires slightly.
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Use Double Cut Vias - tries to opportunistically replace single cut vias with double
cut vias wherever it can without creating a violation.
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A
Forms Reference
This chapter describes the forms in the Virtuoso Space-based Router.
Automatic Routing
General Options
Initialize Route
Global Route
Local Route
Detail Route
Refinement Route
Net Options Form
AutoRouter Extraction Options Form
Pre-Load Environment Variables Form
Batch Checker Form
Routability Tab
Process Rules Tab
Connectivity Tab
Speciality Routing Tab
Placement Tab
Fabrication Tab
Congestion Analysis
Differential Pair Spacing Form
Forms Related to Creating and Editing Wires
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Create Bus Form
Create Bus Context-Sensitive Menu
Create Geometric Wire Form
Create Wire Form
Create Single Wire Context-Sensitive Menu
Point to Point Form
Point to Point Context-Sensitive Menu
Guided Routing Form
Guided Routing Context-Sensitive Menu
Select Via Form
Stretch Form
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Automatic Routing
General Options
Operate On
You can select the area that you want to operate on.
Selected Set - routes the nets which are selected from the Navigator or Search
assistants.
Cellview - routes the entire design. This option is selected by default.
Style
The three routing styles that are available: Device Level, ASIC, and Chip Assembly.
Specifying the routing style will determine which steps in the sequencer will run and also set
one of the Initialize step Pre-load environment variables. Specifying the design type affects
the heuristics of global route and detail route. Therefore the value of design type needs to
reflect the type of design you are routing.
Default Constraint Group
Defines the default constraint group for the router for nets with no constraint group assigned.
The selected constraint group will be used in automatic routing.
Routing Layers
The top and bottom layers are used to set a limitRoutingLayer constraint. The intersection of
the limitRoutingLayers and validRoutingLayers constraint determine which layers will be used
for routing. The resultant routing layers will be an and of the layers in the net constraint
groups. An example for this would be if your net group constraint had M2-M4 as valid routing
layers and in the routing GUI, you specified M1-M3, the effective valid layers would be M2 and
M3. M1 is not included because it is not a part of the net group constraint. If that same net
group had a taper constraint that had a valid routing layer of M1, then for tapering you would
only have M1 as the valid routing layer, not M2 or M3.
Top Layer - the top routing layer.
Bottom Layer - the bottom routing layer.
Use Grid
Allows the router to select Manufacturing for gridless routing (independent of routing grid)
or Routing for gridded routing. The routing data will still be created on the manufacturing grid.
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Special Blockage Treatment
All the blockages have proper spacing properties and the blockages model the metal on the
edge of the block properly. To alter the treatment of blockages, select any of the following
option.
Note: When you use the Automatic Routing form to route your design, preset properties on
blockages and properties on nearby shapes are used to determine spacing requirements.
Treat as Minimum Width - treat these blockages as metal shapes with minimum width.
Disable Use Min Width to treat unassigned blockages as metal shapes and use their
actual width to calculate spacing requirements.
Treat as Minimum Spacing - enforces minimum space edge of the blockage even if a
wider metal shape is next to it.
Ignore Blockage Spacing - ignores the blockage spacing properties set on the
blockage.
Ignore Routespec Spacing - ignores the routespec spacing.
Route Nets of Type
You can select the type of net that you want to route in the selected set or the cellview. It will
route all the nets of that type. You can either select Bus or Nets. The Nets are the nets that
are not in a net group. The Bus is a net group with a type of net_bundle. It calls for a special
command called bus_route, which deals with the bus routing.
The sequential run with different types of selected net will route the other net type. The
differential pairs and matched length net group constraints will not be able to be routed with
the Automatic Router GUI. They should be routed in RIDE.
Note: The shielded nets are not routed in automatic routing GUI. It will be supported in a
future release.
Net Options
The Net options are optional and allows you to lock nets and which nets to lock prior to routing
or exclude from routing. You can import net locking from a file. The file format is a single
column of net names. To specify the nets that are to be locked, click the Options button. This
will display the Net Options form. To know more about net options, refer to Net Options Form.
Miscellaneous
Attempt to Use Double Cut Vias - sets the use double cut vias option for local route
and detail route. If you want to insert double cut vias wherever it is possible and not
everywhere, select the Attempt to Use Double Cut Vias option. Using this option
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allows pin escape and routing with double cut vias. However, if you want to insert double
cut vias everywhere, then use the minNumCut constraint added in constraint manager.
Taper Pin Width - automatically sets the routespec of the pin so that the route will match
the width of the pin.
Autorouter Extraction
Extraction is necessary for the connectivity based routing environment, if you do not have
connectivity that is assigned properly, throughout the design hierarchy. You can specify the
extraction options by clicking the Options button next to Extraction. This will display the
Autorouter AutoRouter Extraction Options Form.
Sequence
You can select the Run Mode, Checkpoint, and also save each of the routing step. The Run
status dot, which has no fill means that the step will not be run. To run a step that is not
selected by default, double-click on the dot to turn it ON. For example, if you have a Device
Level design that is rather large or congested, you could turn on global route. Each routing
step displays a form when you click the Edit button.
Initialize Route - allows the user to map layer purpose pairs into a router understood
layer-purpose pairs. Also, it allows you to set the environment variables before the
routers are run or run an arbitrary TCL script before the routers are run. Any RIDE
environment variables are also allowed to be set at this step.
Global Route - replaces all opens with global routes and re-routes to reduce congestion.
Local Route - adds pin escapes.
Conduit Route - this option is greyed out in this release. It will be made available in a
future release.
Detail Route - completes the routing of all nets and resolves violations.
Refinement Route - checks for and attempts to fix specific types of violations by ripping
up wiring and re-routing. Can also re-route short connections and remove unnecessary
vias.
Related topics
Specifying General Options
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Initialize Route
Layer Map - sets up the layer mapping options. The Options button next to the Layer Map
field invokes the GUI to set the layer purpose map. This is only necessary if there are
false shorts through the diffusion layer.
Pre-load Environment Variables - sets up the environment variable options before the
design is loaded into the Virtuoso Routing IDE virtual memory. For more information on
environment options, refer to the Pre-Load Environment Variables Form section.
Initialization Script - sources a TCL file shown in the text field before routing and allows
you to setup and run user functions. You can even specify the TCL file by clicking the
Browse button.
Related topics
Global Route
Reset Global Route- purges an existing global route results and starts afresh.
Normally it will incrementally improve on existing global routes.
Routing Layer - mentions the name of the routing layer.
Density - defines the density of the routing layer.
Related topics
Local Route
Escape All Layers - escapes pins that are there on all routing layers. By
default, only the bottom layer is escaped.
Vias Must be Fully Enclosed in Pin Metals - escapes the pin only if via metal
is fully enclosed within the pin metal.
Vias Must be Enclosed on Layers - if this field is blank, all pin layers must be
fully enclosed. However, if the metal layers are specified, only pins on those
layers will be required to have pin metal fully enclosing the via metal.
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Note: The Vias Must be Enclosed on Layers field is enabled only if the Vias Must be
Fully Enclosed in Pin Metals option is selected.
Related topics
Detail Route
Large Space Checking - sets some large non-symmetric spacing rules.
Check Level - sets the check level for detail routing. This means how detailed a check
should be performed when routing. By default, this option is set to 3. This means that a
detailed check will be performed while routing.
Test for Convergence - used to debug constraints. It allows for a quicker run time by not
hitting the most optimal routing result. This option is useful if you have lot of violations
that cannot be fixed.
Use Effective Width of Overlapping Shapes - merges the shapes effectively to see
what width the combined shapes have as compared to evaluating each shape
individually.
Critic - smoothens the wires by removing unnecessary jogs in the entire top cellview.
Check Antenna - checks for process antenna violations for the entire design, a specific
net, or nets in a set, an area, or a set.
Maximize Cuts - enables a post processing step to attempt to pack more cuts in an
overlap area than the minimum normally selected. This is done only if it does not add
additional metal to the overlap area.
Prefer Violations over Opens - route guides even if there is a violation present.
Snap to Pin Center - snap wires to the center of rectangular pins or pins that are
created as a polygon and have a rectangular shape. When selected, Snap to Pin Center
snaps wires to the starting and ending pins.
Pin Strapping Layer - adds a strapping between gates of a multi-fingered device in
metal (dropping a contact as close as possible to the gate and connecting metal between
the fingers from that point) or poly (connecting all gates to poly with one contact up to the
metal layer). You can choose the strapping layer from Poly and Metal. This option helps
to minimize the use of Poly while performing device-level routing of multi-finger devices
that have Poly layer pins.
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Related topics
Refinement Route
Align Vias to Edges of Wires - allows to move vias such that the edge of the metal
layers in the vias overlap/align with the edges of the wires. This can reduce the number
of small notches around vias.
Crossing - eliminates routes on the same net from crossing over each other.
Minimum Area - fixes minArea rule violations.
Minimum Edge Length - fixes minEdgeLength rule violations.
Minimum Enclosed Area - fixes minEnclosedArea rule violations.
Minimum Width - fixes minWidth rule violations.
Minimum Number of Cuts - fixes minNumCut violations.
Port Shorts - fixes multiple connections to multiple ports on a cell.
Reduce Vias - attempts to reduce the number of vias by increasing the number
of small same layer jogs. This option is deselected by default.
Reduce Wire Notches at Pins - attempts to remove any small metal notches located
near pins by shifting the wires slightly.
Routing Grid - fixes routing grid violations.
Fix Extensions - fixes all extension violations based on the extension constraints
defined in the design. For example, minDualExtension constraints, and
minExtensionEdge constraints.
Minimum Spacing - fixes minimum spacing violations.
Repair Opens - allows you to do localized changes to fix the opens that were caused by
spacing violations.
Minimize Unprotected Vias - Minimizes minimum enclosure single cut vias and
remasters to double-cut via and larger enclosure single cut vias.
No Push - allows you to remove (unlocked/not fixed) vias by localized re-routing and
improves manufacturability. It does not allow pushing during the fixing step.
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Forms Reference
Related topics
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Forms Reference
Net Options Form

In the Net Options form, you can specify the nets that are to be locked or select the nets that
should be excluded from routing.
Lock Existing Routing - locks all pre-existing routing information before attempting to
route any opens. It will not reroute preroutes with violations.
Unlock Before Routing - unlocks the nets in the selected set or all nets in the cellview
before routing.
Lock After Routed - locks the nets in the selected set or all nets in the cellview after
routing.
Lock Types - lock the nets with signal type power or ground and or clock before routing.
You can either select Power and Ground nets or Clock nets.
Net Lock File - imports a file for net locking. The net lock file contains only a list of net
names, where one net name is displayed per line.
Exclude Types - specify the names of the nets that you want to exclude from routing. It
prevents power and ground nets or clock nets from being processed.
Net Exclude File - specify the name of a file that contains names of nets in the design
to exclude. The net exclude file contains only a list of net names, where one net name is
displayed per line. You can use the Browse button to locate the filename in your
hierarchy.
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Forms Reference
AutoRouter Extraction Options Form

Extraction is necessary for the connectivity based routing environment, if you do not have
connectivity that is assigned properly, throughout the design hierarchy. The Autorouter
Extraction form contains almost all the arguments for the command
extract_net_connectivity. The top group button enables the command. It is turned
on by default for Device Level. However, for ASIC and Chip Assembly, it can be manually
enabled.
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Extract Net Connectivity - allows you to specify the routing extraction options. You can
specify the routing extraction options only when the Extract Net Connectivity option is
selected.
Start Extraction at Level - the level at which you want to start extraction. The start
extraction level can be 0 or 1. In most cases, the extraction level will be 0. By default, the
start extraction level is set at 1.
Stop Extraction at Level - the level at which you want to stop extraction. You can stop
extraction at different levels. By default, all levels are extracted.
Levels after Flattening - the number of levels that should be left after flattening. This
option allows you to model a flat or a 2 level hierarchy for routing. This is useful when the
lower level cells contribute to legal connection regions.
Flatten Cells - performs extraction on the cells in the given list. Cells are given using the
format lib/cell/view. Wildcards are accepted.
Ignore Cells - ignores layout in the given cells. Wildcards are accepted.
Clock Net Names - recognizes names in the list as clock nets in the design. If the
extractor creates a net with one of these names, the signal type of the net will be set to
"clock".
Power Net Names - recognizes names in the list as power nets in the design. If the
"power".
Ground Net Names - recognizes names in the list as ground nets in the design. If the
"ground".
Net Name Prefix - specifies a prefix string for names of nets created by the extractor that
are not named with a label from text or property. The extractor will create a unique name
for each net by appending a number at the end of the prefix.
Net Name Property - names extracted nets using the value of this property attached to
at least one of the net shapes.
Net Name File - specifies the name of the file to be used for net name mapping.
Layer Precedence - an ordered list of layer names that determines the layer to which
the net name will be attached if the text is over multiple layers. The layer precedence is
used with -text_layer, but must not be used with -text_layer shape_layer.
Pin Style - controls which shapes become pin shapes. It modifies the routers legal
connection regions by setting the pin style. By default, the drawn pin shape is the only
legal point of connection.
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Text Layer - specifies the layer(s) on which the extractor looks for text objects to name
nets.
Text Purpose - specifies the name of the layer purpose to use to search for text objects
in the layout.
Save Lib Name - saves the layout with the extracted nets to the given library. By default,
no save occurs.
Save View Name - saves the layout with the extracted nets to the given view. It has the
same function as -view. Both the arguments cannot be given in the same command. By
default, no save occurs.
Apply Pin Style to Top Cell - specifies whether or not the pin style setting should be
applied to the top cell. If you do not want all of the top cell shapes to be made into pin
shapes, deselect the Apply Pin Style to Top Cell option.
Resolve Shorts - merges nets that are shorted.
Flatten All LPPs - when this option is selected, the shapes on all layer purposes are
copied up the hierarchy during the flattening process. If this option is deselected, only
interconnect objects are copied.
Extract Poly - extracts shapes on the poly layer.
Save Flattened Cells - saves cell views after extraction, overwriting current views. By
default, no save occurs.
Prepare for Routing - organizes the route segments and vias into routes and creates
the necessary route objects in preparation for routing.
Use Layout Text - specifies the name to extracted nets using text objects in the layout.
Nets not named with text or properties are named using a prefix and a number.
Note: The extraction options specified in the Layout XL Options form can also be searched
using the Search Assistant. When an option is specified in the Search Assistant and search
is performed on the specified option, the Layout XL Options category is added in the Search
Assistant pane and the searched option name is displayed below the Layout XL Options
category.
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Pre-Load Environment Variables Form

The Pre-load Environment Variables form allows you to set the environment variables for
routing purposes.
Database User Namespace - allows you to select the database name that will be used for
routing purposes. It informs whether the net names are CDB syntax or DEF syntax
Design Type - allows you to select the design type, which will determine the steps in the
sequencer that will run. Specifying the design type affects the heuristics of global route and
detail route. Therefore the value of design type needs to reflect the type of design you are
routing, whether you are routing devices, standard cells, or macro blocks.
Allow Pin to Pin Spacing Check - checks the spacing between pins too.
Make Paths into Route Segments - breaks up the path into route segments.
Check Constraint Basics - allows you to check the constraints that are available in the
technology file. This check is done during loading time.
Route Connections Between IO Pins - allows you to specify the route connection between
two IO pins.
Make Halo Blockage Around prBoundary - allows you to make a blockage coincident with
the prBoundary to enforce a DRC spacing to the boundary.
Load Unplaced Instances - allows you to load unplaced instances from the design. You can
use -resetplacestatus unplaced with cdb2oa if your design contains unplaced
instances.
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Batch Checker Form

Routability Tab
Check
Blockage - checks for blockage violations
Minimum Space - checks for minimum pin spacing violations
Minimum Width - checks for minimum pin width violations
Via - checks via escapes
Markers Limit Per Type - specifies the limit on the number of markers for each type of
violation that can be created.
Process Rules Tab

Scope
Current Editable Cellview - checks shapes in the entire design for process rule
violations.
Area - checks shapes in the selected area.
Select Area - allows you to select an area within the current cellview.
Filter Options
Hierarchy Depth - sets the Hierarchy Depth to the Top Level or Current & Below
Check For
The options in this group box allows you to select the check boxes for the process rules
that you want to check.
Connectivity Tab
Scope
Current Editable Cellview - checks shapes in the entire design for shorts and opens.
Selected Nets - checks only the currently selected nets for shorts and opens.
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Exclude Selected Nets - checks all nets except the currently selected nets for shorts
and opens.
Check For
Loops and Dangles - checks for dangling wires and wires with loops.
Filter Options
Exclude Power and Ground Nets - when this option is on, power and ground nets are
not checked for connectivity errors.
Speciality Routing Tab

The batch checker only checks specialty routing constraints that are created with
pathSegs and vias that are in routes.
Symmetry - checks whether a symmetry axis is defined and if so whether it's position
is correctly defined. As long as one pair of symmetric pins can be identified, the axis is
considered well defined, otherwise a marker will be generated at the location of the axis
with a message about the incorrectly assigned location. Only shapes on metal and poly
layers are being checked and only the routed portions of the symmetric nets are
checked. Geometric shapes (e.g. paths, pathSegs/vias not in a route) are not checked.
A warning will be issued when checker detects geometric shapes.
Diff Pair - the percentage of unpaired length is compared for each net in of a diff pair.
Placement Tab
Placement
Check all the placement constraints - checks for all the placement constraints in
the design.
Fabrication Tab
Scope
Current Editable Cellview - checks shapes in the entire design for process rule
violations.
Selected Nets - checks only the currently selected nets for shorts and opens.
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Exclude Selected Nets - checks all nets except the currently selected nets for shorts
and opens.
Antenna Oxide Models
In this group box, you can specify which oxide model(s) to use: First, Second, Third,
Fourth. By default, the First oxide model is selected.
Related topics
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Congestion Analysis
Number of tracks/GCell - determines the size of the GCell. Track pitch is defined by width
+ spacing in the foundry rules. Changing the number of tracks makes the GCell larger or
smaller.
Automatic - allows the router to determine the optimal size of the GCell.
User Defined - allows you to enter the number of tracks to define the size of the GCell.
Re-Compute - re-compute with the new value if you change the number of tracks.
View congestion in design - displays the congestion map in the design window. After you
click Apply to calculate congestion, this field turns the congestion map on or off.
Display Color - the color and pattern associated with each percentage. You can enter a
different percentage to associate with any of the color/patterns.
Slider bar - redefine where the 100% congestion falls in the scale.
Horizontal - limit congestion data considered when performing analysis to data in the
Horizontal direction.
Vertical - limit congestion data considered when performing analysis to data in the Vertical
direction.
Layer Selection - limit congestion analysis to any of the layers by selecting/unselecting the
check boxes.
Related topics
Congestion Analysis Specification
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Differential Pair Spacing Form

Spacing is the value of the spacing gap between differential pairs.
Related topics
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Create Bus Form

You can create a bus in the L, XL, and GXL tiers of the Virtuoso Layout Suite.
Create Bus Form in L
Create Bus Form in XL and GXL
Create Bus Form in L
Connectivity
Net Name enables you to specify the net names for creating a bus. You can specify the
net names in one of the following ways:
By specifying a bundle name, such as netA, netB, netC<1>, netD, where the
net names are separated by commas.
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By using the bus notation, such as net<0:3>. If you specify the net names in bus
notation, the notation expands to display individual net names, such as net<0>,
net<1>, net<2>, net<3>, in the Net Name field when you move the cursor to
another field in the form. The number in the Number of Bits cyclic field updates
based on the number of nets specified in the Net Name field. For example, the
Number of Bits cyclic field updates to 4 for the bus notation net<0:3>.
By specifying a bus base name, such as netA or myBus, and additionally setting up
the bus cardinality in the Number of Bits cyclic field. The bus base name expands
to display individual net names in the Net Name field only after you start creating
the bus. For example, if you start creating a bus by specifying the bus base name as
netA and setting the Number of Bits cyclic field to 10, the bus creation begins with
10 wires that are assigned to the netA<0>, netA<1>, netA<2>, ... ,
netA<10> nets.
New nets are created if the ones specified do not already exist. If you start creating a bus
from existing pins, the net names are automatically picked from the net of the pins. If you
create the bus in free space without specifying any net names, the bus created is not
assigned to any net and therefore, does not have any connectivity.
Environment variable: netName
Width enables you to specify the width of each wire in the bus. You can increase or decrease
the wire width by pressing Ctrl + Shift keys and scrolling the mouse wheel up or down,
respectively.
Environment variable: wireWidth
Fixed Width specifies to use the same bus wire width on all layers. The value specified in
the Width field is used for the bus wires on all layers.
Environment variable: fixedWidthPaths
Bit Spacing specifies the distance between the centerlines of the bus wires. If no value is
specified in this field, the minSpacing value is considered.
Keep Bit Spacing maintains the same bit spacing on all the layers. The value specified in
the Bit Spacing field is used for spacing the bus wires. If this check box is selected, the
spacing between the wire centerlines is maintained after you add a via or bend the wires. If
this check box is not selected and you add a via or bend the wires, the spacing between the
wire centerlines changes to the minSpacing of the layer or the specified bit spacing,
whichever is greater.
Environment variable: weKeepBusWireSpacing
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Create Bus Constraint creates a bus constraint automatically, if one does not already exist,
for the nets you specify in the Net Name field or for the ones you pick by area-selecting
multiple pins or instPins. You can view the created bus constraint in the Constraint Manager
in XL or GXL.
Environment variable: weCreateBusConstraint
Fan Out to Vias spreads bus wires for via placement. When wires are at the minimum wire
spacing but the via spacings are larger, the wires can either be fanned out to connect to the
vias in the pattern or can be back tracked to intersect the previous segment in the wire.
Environment variable: fanOutToVias
Number of Bits enables you to specify the number of wires in an unassigned bus.
In the Net Name field, if you specify net names as a bundle name or by using the bus
notation, the value in the Number of Bits cyclic field automatically updates to match the
number of nets specified. If net names are specified in the Net Name field and you
manually update the value in the Number of Bits cyclic field, the net names specified in
the Net Name field are removed.
In the Net Name field, if you specify the net names by using the bus base name, you
can set up the cardinality of the bus by using the Number of Bits cyclic field. The bus
base name expands to display individual net names in the Net Name field only after you
start creating the bus.
Note: If you update the Number of Bits cyclic field after starting bus creation, the net
names are removed from the Net Name field.
The default value is 2.

Environment variable: weBusNumBits
Justification controls the direction in which to offset the wires from the digitized points.
Environment variable: pathJustify
Offset creates wires at a specified distance from the digitized point with respect to the
centerline of the control wire, in the direction specified by Justification. The default is 0.
Environment variable: wireOffset
Begin Style controls how the beginning wire segment ends are created.
Environment variable: pathSegBeginStyle
truncate creates wires with no beginning extension.
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extend creates wires with the default beginning extension value.
variable uses the value specified in the Begin field for the beginning extensions of
wires.
custom creates wires in which the vertices are constrained to the current grid.
Begin allows a value to be specified for the beginning extensions of wires. This field is
available if the Begin Style list is set to variable.
Environment variable: pathSegBeginExt
End Style controls how the ending wire segment ends are created.
Environment variable: pathSegEndStyle
truncate creates wires with no ending extensions.
extend creates wires with the default ending extension values.
variable allows a value to be specified in the End field for the ending extensions of
wires.
End allows a value to be specified for the ending extensions of wires. This field is available if
variable is selected from the End Style list.
Environment variable: pathSegEndExt
Snap Mode controls how the cursor snaps to the grid when you create a bus.
Environment variable: snapMode
diagonal creates wires parallel to the X or Y axis or at a 45-degree angle to the axes.
orthogonal creates wires parallel to the X or Y axis.
L90XFirst creates orthogonal two-segment wires and creates the first line in the X
direction.
L90YFirst creates orthogonal two-segment wires and creates the first line in the Y
direction.
Acute Angle enables the creation of acute angle buses. If this check box is not selected,
which is the default, you can create bus wires only between 90 degree to 180 degree angles.
The Acute Angle check box is available only when Snap Mode is set to diagonal.
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Environment variable: acuteAnglePath, acuteAngleWire
Place Via(s) at Last Click creates vias at the last click location. Via location is digitized
before the selection of the via. When this check box is not selected, vias float as the pointer
moves, ready to be placed at the next click.
Environment variable: usePrevPointForVia
Snap to Pin Center snaps wires to the center of rectangular pins or of pins that are created
as polygons and have rectangular shapes. When this check box is selected, bus wires snap
to the starting and ending pins centers. By default, the Snap to Pin Center check box is not
selected.
Environment variable: snapToPin
Create Bus Form in XL and GXL
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Connectivity
Net Name enables you to specify the net names for creating a bus. You can specify the
net names separated by commas or spaces or specify them in bus notation, such as
net<0:3>. New nets are created if the ones specified do not already exist. If you start
creating a bus from existing pins, the net names are automatically picked from the net of
the pins.
Probe Nets creates probes for the autopicked, selected, or specified nets.
Width enables you to specify the width of each wire in the bus. You can increase or decrease
the wire width by pressing Ctrl + Shift keys and scrolling the mouse wheel up or down,
respectively.
Fixed Width specifies to use the same bus wire width on all the layers. The value specified
in the Width field is used for the bus wires on all layers.
Create Bus Constraint creates a bus constraint automatically, if one does not already exist,
for the nets you specify in the Net Name field or for the ones you pick by area-selecting
multiple pins or instPins. You can view the created bus constraints in the Constraint
Manager in XL or GXL.
Environment variable: weCreateBusConstraint
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Number of Bits specifies the number of wires in the bus.
Environment variable: weBusNumBits
Justification controls the direction in which to offset the wires from the digitized points.
Offset creates wires at a specified distance from the digitized point with respect to the
centerline of the control wire, in the direction specified by Justification. The default is 0.
truncate creates wires with no beginning extension.
extend creates wires with the default beginning extension value.
variable uses the value specified in the Begin field for the beginning extensions of
wires.
Begin allows a value to be specified for the beginning extensions of wires. This field is
available if the Begin Style list is set to variable.
truncate creates wires with no ending extensions.
extend creates wires with the default ending extension values.
variable allows a value to be specified in the End field for the ending extensions of
wires.
End allows a value to be specified for the ending extensions of wires. This field is available if
variable is selected from the End Style list.
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Snap Mode controls how the cursor snaps to the grid when you create a bus.
direction.
direction.
Acute Angle enables the creation of acute angle buses. If this check box is not selected,
which is the default, you can create bus wires only between 90 degree to 180 degree angles.
The Acute Angle check box is available only when Snap Mode is set to diagonal.
before the selection of the via. When this check box is not selected, vias float as the pointer
moves, ready to be placed at the next click.
Enable Via Assistance helps determine a legal via site location where you can add a via
during routing and not violate design clearance rules. This option works when layer grids are
defined in the technology file. This check box is available if the Place Via(s) at Last Click
check box is selected.
Auto Terminate finishes the Create Bus command as soon as a point is digitized on a
flightline target object (pin, existing wire, or via). All wires in the bus snap to the target pin.
Snap to Pin Center snaps the bus wires to the center of rectangular pins or of pins that are
created as polygons and have rectangular shapes. When this check box is selected, bus
wires snap to the starting and ending pins centers. By default, the Snap to Pin Center check
box is not selected.
Snap to Via Center snaps wires to the center of vias. If this check box is selected and you
click a via, the starting wire starts from the clicked point and two small segments are added
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to connect to the via origin. With this check box selected, tapping a via and a wire gives
preference to the via. This check box is off by default.
Environment variable: snapToViaCenter
Related topics
Creating a Bus
Creating a Wire
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The Create Bus context-sensitive menu appears on right-clicking in the design display area
when the Create Bus (L/XL/GXL) or the Create Wire (XL/GXL) command is running and
multiple wires are being routed.
The context-sensitive menu provides the following commands:
Options
Select Via
Via Up
Via Down
Rotate Via(s) Cut Pattern
Via Alignment
Via Pattern
Cycle Control Wire
Finish Bus
Finish Entire Bus
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Gather/Spread Bus
Use Width
Use Spacing
Use Width and Spacing Target Pins
Backup Point
Options
Opens the Create Bus Form. You can also use press F3 at any time to open this form.
Select Via
Opens the Select Via Form to change the bus layer. You can rotate the via by using the Select
Via form or by using the Rotate Via(s) Cut Pattern command on this context-sensitive menu.
Via Up
Changes the layer to the next layer up and places the corresponding default via.
Via Down
Changes the layer to the next layer down and places the corresponding default via.
Rotates the via cuts and swaps the rows and columns, if any, while rotating the via shape by
90 degree as you place or drag the via. You can also rotate pending vias by clicking the middle
mouse button. This command is available only while you are adding a via. You can also rotate
a via by using the Rotate Via(s) Cut Pattern button on the Select Via Form.
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Via Alignment
Provides options to align vias while adding them to the layout. You can choose to align a via
automatically or by selecting a custom alignment option. You can also align a via by using the
Via Alignment options on the Select Via Form. For more information about the Automatic
and Override alignment options, see the Select Via Form.
Note: The Override options on the Via Alignment sub-menu, as shown in the figure above,
are available while you are adding a via.
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Via Pattern
Provides predefined via patterns to choose from to add multiple vias simultaneously while you
are routing multiple wires. For more information about the available patterns, see the Select
Via Form.
Cycle Control Wire
Cycles the control wire function among the extreme and middle wires of a bus. For more
information, see Using the Control Wire.
Finish Bus
Automatically routes the active flightline following the layer, via and width specifications
defined in the application default constraint group or any overrides defined in the Create Bus
Form or in the Wire Assistant. The command is available only XL tier onwards. The command
routes only the active flightline even if the current net contains more than one open flightline.
This command is available only when the Create Bus command is running and there is an
active flightline (dynamic flightline from the current cursor position to the closest target). By
default, the Finish Bus command leaves opens if it cannot create the routes without creating
violation. For more information, see Finishing Connections.
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Finish Entire Bus
Automatically routes flightlines of the current nets being edited following the layer, via and
width specifications defined in the active constraint group. By default, it leaves opens if it
cannot connect without creating violation. The command is available only XL tier onwards.
For more information, see Finishing Connections.
Gather/Spread Bus
Gathers or spreads bus wires before the first digitized point. It toggles to Ungather/
Unspread Bus command.
Use Width
Fixed Width: Sets the same bus wire width to be used on all the layers. The width value
is derived either from the Width field in the Create Bus form, in which case all the bus
wires have the same width, or from the widths of pins from which the bus wires start, in
which case the bus wires have different widths.
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Start Pin Nearest Edge: Sets the bus wire width the same as the length of the starting
pin edge nearest to the pointer. The nearest pin is determined by the distance between
the pointer and the center of a pin edge. This is the default Use Width setting. The entire
pin edge highlights within the Aperture distance from the pointer.
If you select Start Pin Nearest Edge as the width option and also select the Fixed
check box on the Use Width sub-menu, the initial bus wire width is maintained on all the
layers the wire is changed to. After you complete creating the bus and start creating a
new one, the Use Width mode is still set to Start Pin Nearest Edge. You can tap
another pin to reset bus wire width to the width of the new pin.
Derived from Constraints: Sets the bus wire width the same as the minWidth value in
the technology file or in any applicable constraint group defined at the design or object
level. Within Aperture distance from the pointer, the length of the highlight matches the
minWidth value.
Last Specified: Sets the bus wire width the same as the value specified in the Width field
in the Create Bus form or as the Width value in the Override Constraints table in the
Wire Assistant for the applicable layer. Within Aperture distance from the pointer, the
length of the highlight matches the respective width value.
Target Pins: Sets each bus wire to match the width of the same edge of each respective
target pin. If the pins are vertically aligned to bus wires, the bus wire widths match the
width of the vertical edges of the respective target pins. Similarly, if the pins are
horizontally aligned to bus wires, the bus wire widths match the width of the horizontal
edges of the respective target pins. The horizontal and vertical edges might correspond
to narrow edges for some target pins and wide edges for other target pins.
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Use Spacing
Fan Out To Vias: Spreads bus wires for via placement.
Keep Bit Spacing: Maintains the same bit spacing on all the layers.
Target Pins: Sets the same spacing between the centerlines of bus wires as the spacing
between the centers of the target pins. This option is available only in XL and GXL.
Use Width and Spacing Target Pins

Sets both Use Width: Target Pins and Use Spacing: Target Pins.
Backup Point
Removes the last digitized point. If a via was added to the last digitized point, that via is also
removed.
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By using this form, you can create paths and geometric pathSegs and vias. For creating
pathSegs in routes, see the Create Wire Form.
Create Geometric Wire Form in L
Wire Tab
Bus tab is available only in XL and GXL tiers.
Create Geometric Wire Form in XL and GXL
Wire Tab
Bus Tab (Available only for Segments)
Create Geometric Wire Form in L

Create Wire using
Environment variable: createWireMode
Paths are single layer objects. When used to create non-orthogonal routing, paths can
lead to off-grid vertices being created, depending on the width and angle being used.
Segments (pathSegs) are single layer objects that can be used to create on grid 45
degree wires. Segments can not be used for any-angle routing and are limited to
orthogonal and diagonal routing. This option is selected by default.
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The form when Paths is selected:
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The form when Segments is selected:
Connectivity
Net Name lets you enter a net name for the current wire. The created wire is added to
the specified net. A new net is created if the one specified does not already exist. To
specify net names for creating a bus, enter a list of net names separated by commas or
spaces. You can also specify net names in bus notation, such as net<0:3>.
Snap Mode controls how the cursor snaps when you create the wire. When Segments
(pathSegs) are used to create wires, anyAngle is not an option. PathSegs are limited to
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anyAngle creates wires at any angle. Can only be specified when using paths to create
wires.
direction.
direction.
Acute Angle allows the creation of acute angle paths and segments. When off (default), you
can create paths only from 90 degree to 180 degree angles. Acute Angle is available only
when Snap Mode is set to anyAngle or diagonal.
before the selection of the via. When off, vias float as the cursor is moved, ready to be placed
at the next click.
as polygons and have rectangular shapes. The option snaps wires to the starting and ending
pins. The Create Shape Geometric Wire and Create Wiring Wire commands
snap wires to the centerline of paths and pathSegs and the origin of vias when tapping those
particular objects regardless of whether Snap to Pin Center is on or off. The Snap to Pin
Center option is off by default.
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Wire Tab
Using Paths
Width displays the width of the current wire. You can also enter a value for the width of
the current wire. You can increase or decrease the wire width interactively by pressing
Ctrl + Shift keys and scrolling the mouse wheel up or down, respectively.
Fixed Width specifies that wires on all layers are to be created using the value specified
in the Width field.
Justification controls the direction in which to offset the path from the digitized points
of the path.
Offset creates a wire at a specified distance from the digitized points with respect to the
centerline of the path, in the direction specified by Justification. The default is 0.
Path Style controls how the path ends are created.
Environment variable: pathStyle
truncate creates a wire with no ending extension.
extend creates a wire with the default ending extension value.
round creates a wire with path ends extending from the path points by one half the
path width, creating an octagonal shape.
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variable uses the value specified in the End field for the ending extension of a wire.
Begin allows a value to be specified for the beginning extension of the wire. This field
becomes active when variable is selected from the Path Style field.
Environment variable: pathBeginExt
End allows a value to be specified for the ending extension of the wire. This field
Environment variable: pathEndExt
Create as ROD, named creates the path as a ROD object with the specified name.
Environment variable: rodAutoName
Using Segments
the current wire.
in the Width field.
Justification controls the direction in which to offset the pathSeg from the digitized
points of the pathSeg.
centerline of the pathSeg, in the direction specified by Justification. The default is 0.
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truncate creates a wire with no beginning extension.
extend creates a wire with the default beginning extension value.
variable uses the value specified in the Begin field for the beginning extension of
a wire.
custom creates a wire in which the vertices are constrained to the current grid.
becomes active when variable is selected from the Begin Style field.
variable allows a value to be specified in the End field for the ending extension of
a wire.
becomes active when variable is selected from the End Style field.
Create Geometric Wire Form in XL and GXL

Create Wire using
Environment variable: createWireMode
Paths are single layer objects. When used to create non-orthogonal routing, paths can
lead to off-grid vertices being created, depending on the width and angle being used.
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Segments (pathSegs) are single layer objects that can be used to create on grid 45
degree wires. Segments can not be used for any-angle routing and are limited to
orthogonal and diagonal routing. This option is selected by default.
In XL and GXL, the Create Wire command, by default, uses pathSegs in routes.
The form when Paths is selected:
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The form when Segments is selected:
Connectivity
Probe Nets creates probes for the selected or specified net.
Snap Mode controls how the cursor snaps when you create the wire. When Segments
(pathSegs) are used to create wires, anyAngle is not an option. PathSegs are limited to
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anyAngle creates wires at any angle. Can only be specified when using paths to create
wires.
direction.
direction.
at the next click. When this option is on in XL or GXL, the Enable Via Assistance option is
enabled to allow the display of suggested via locations.
defined in the technology file. This option is enabled when the Place Via(s) at Last Click
option is selected.
Auto Terminate terminates the Create Wire command as soon as a point is digitized on a
flightline target object (pin or existing wire or via). When creating a bus and Auto Terminate
is on, all wires in the bus snap to its target pin.
as polygons and have rectangular shapes. The option snaps wires to the starting and ending
pins. The Create - Shape - Geometric Wire and Create - Wire commands snap wires to
the centerline of paths and pathSegs and the origin of vias when tapping those particular
objects regardless of whether Snap to Pin Center is on or off. The Snap to Pin Center
option is off by default.
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Wire Tab
Using Paths
in the Width field.
Justification controls the direction in which to offset the path from the digitized points
of the path or pathSeg.
centerline of the path, in the direction specified by Justification. The default is 0.
Path Style controls how the path ends are created.
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Environment variable: pathStyle
round creates a wire with path ends extending from the path points by one half the
path width, creating an octagonal shape.
variable uses the value specified in the End field for the ending extension of a wire.
Environment variable: pathBeginExt
Environment variable: pathEndExt
Create as ROD, named creates the path as a ROD object with the specified name.
Environment variable: rodAutoName
Using Segments
in the Width field.
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Justification controls the direction in which to offset the pathSeg from the digitized
points of the path or pathSeg.
variable uses the value specified in the Begin field for the beginning extension of
a wire.
variable allows a value to be specified in the End field for the ending extension of
a wire.
becomes active when variable is selected from the End Style field.
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Bus Tab
Width overrides the default width value of wires. You can increase or decrease the wire width
interactively by pressing Ctrl + Shift keys and scrolling the mouse wheel up or down,
respectively.
Fixed Width, if selected, specifies that wires on all the layers must be created using the
value specified in the Width field. If this check box is selected before the Create Wire
command is run and the value specified in the Width field does not violate the minWidth
value of the layer being edited, the Width value is saved for subsequent Create Wire
command runs. However, if the check box is not selected or the specified width value violates
the minWidth value of the layer being edited, the Width value is not saved.
If you change the value in the Width field or select the Fixed Width check box, the Use
Width option in the Create Bus Context-Sensitive Menu section automatically sets to Last
Specified. Conversely, if the Fixed Width check box is selected and you update the Use
Width option to a value other than Last Specified, the Fixed Width check box automatically
clears.
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Related topics
Creating a Wire
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Create Wire Form

Using this form, you can create pathSegs and vias in routes. This form is available only in XL
and GXL tiers. See Creating a Wire for more information. To create paths and geometric
pathSegs, see the Create Bus Form. The Create Wire form has the same fields and options
as those for Segments in the Create Bus Form, with the difference that the Create Wire
form generates symbolic wires.
The form comprises some common options and the Wire Tab and Bus Tab.
Connectivity
Snap Mode controls how the cursor snaps when you create the wire.
orthogonal creates wires parallel to the X or Y axis. This is the default.
direction.
direction.
at the next click. When this option is on in XL or GXL, the Enable Via Assistance option is
enabled to allow the display of suggested via locations.
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defined in the technology file. This option is enabled when the Place Via(s) at Last Click
option is selected.
Auto Terminate finishes the Create Wire command as soon as a point is digitized on a
flightline target object (pin or existing wire or via). When creating a bus and Auto Terminate
is on, all wires in the bus snap to its target pin. This option is selected by default.
as polygons and have rectangular shapes. If this check box is selected, wires snap to the
starting and ending pins. The Create Shape Geometric Wire and Create Wiring
Wire commands snap wires to the centerline of paths and pathSegs and the origin of vias
when tapping those objects regardless of whether Snap to Pin Center is on or off. The Snap
to Pin Center check box is off by default.
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Wire Tab
Width displays the width of the current wire. You can override this value. You can increase or
decrease the wire width interactively by pressing Ctrl + Shift keys and scrolling the mouse
wheel up or down, respectively.
Fixed Width specifies that wires on all layers are to be created using the value specified in
the Width field. If this check box is selected before starting the Create Wire command, and
the value specified in the Width field does not violate the minWidth value of the current
editing layer, the Fixed Width value is saved for subsequent Create Wire commands.
However, if either the check box is not selected or the specified value violates the minWidth
value of the current editing layer, the Fixed Width value is not saved.
If you change the value in the Width field, then the Use Width option in the Create Single
Wire Context-Sensitive Menu section automatically sets to Last Specified, if not already.
Similarly, if you select the Fixed Width check box, the Use Width option changes to Last
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Specified, if not already. Conversely, if the Fixed Width check box is selected and you
update the Use Width option to any value other than Last Specified, then the Fixed Width
check box automatically turns off.
Justification controls the direction in which to offset the pathSeg from the digitized points
of the path or pathSeg.
variable uses the value specified in the Begin field for the beginning extension of a wire.
variable allows a value to be specified in the End field for the ending extension of a wire.
End allows a value to be specified for the ending extension of the wire. This field becomes
active when variable is selected from the End Style field.
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Bus Tab
Width overrides the default width value of wires. You can increase or decrease the wire width
interactively by pressing Ctrl + Shift keys and scrolling the mouse wheel up or down,
respectively.
Fixed Width specifies that wires on all layers are to be created using the value specified in
the Width field. If this check box is selected before starting the Create Wire command, and
the value specified in the Width field does not violate the minWidth value of the current
editing layer, the Fixed Width value is saved for subsequent Create Wire commands.
However, if either the check box is not selected or the specified value violates the minWidth
value of the current editing layer, the Fixed Width value is not saved.
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If you change the value in the Width field, then the Use Width option in the Create Bus
Context-Sensitive Menu section automatically sets to Last Specified, if not already. Similarly,
if you select the Fixed Width check box, the Use Width option changes to Last Specified,
if not already. Conversely, if the Fixed Width check box is selected and you update the Use
Width option to any value other than Last Specified, then the Fixed Width check box
automatically turns off.
Related topics
Creating a Wire
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Right-clicking in the design canvas when the Create Geomteric Wire or Create Wire (XL/
GXL) command is active displays the Create Single Wire context-sensitive menu.
The context-sensitive menu offers the following options:
Options
Select Via
Via Up
Via Down
Via Alignment
Finish Wire
Finish Entire Net
Use Width
Backup Point
Smart Snapping
Auto Tap Wire
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Constraint-Aware Editing
Options
Opens the Create Bus Form (L, XL, GXL) or the Create Wire Form (XL, GXL) depending on
the command that is active. You can also press F3 to open the options form.
Select Via
Opens the Select Via Form to change to other layers. Using this form, you can also rotate the
via and also control via alignment.
Via Up
Changes the layer to the next layer up and places the corresponding default via.
Via Down
Changes the layer to the next layer down and places the corresponding default via.
Rotates the via cuts and swaps the rows and columns, if any, while rotating the via shape by
90 degree as you place or drag the via. You can also rotate pending vias by clicking the middle
mouse button. This menu command is available while you are adding a via. You can also
rotate a via by using the Rotate Via(s) Cut Pattern button on the Select Via Form.
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Via Alignment
Provides options to align vias while adding them to the layout. You can choose to align a via
either automatically or by selecting a custom alignment option. You can also align a via by
using the Via Alignment options on the Select Via Form. For more information about the
Automatic and Override alignment options, see the Select Via Form. The Override options
on the Via Alignment sub-menu are available while you are adding a via.
Finish Wire
Automatically routes the active flightline following the layer, via and width specifications
defined in the application default constraint group or any overrides defined in either the F3
Options form or the Wire Assistant. The command routes only the active flightline even if the
current net contains more than one open flightline. This command is available only when the
Create Wire command is active and there is an active flightline (dynamic flightline from the
current cursor position to the closest target). To use the command, select Finish Wire from
the context-sensitive menu. By default, it leaves opens if it cannot connect without creating
violation. For more information, see Finishing Connections.
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Finish Entire Net
Automatically routes remaining sections of incomplete nets following the layer, via and width
specifications defined in the active constraint group or any overrides defined in the Create
Wire Form or in the Wire Assistant. By default, it leaves opens if it cannot connect without
creating violation. This command is available only when the Create Wire command is active.
For more information, see Finishing Connections.
Use Width
In VLS L, only Fixed Width, Derived from Constraints, and Last Specified options are
available.
In XL and GXL, for all the Use Width options, except for Target Pin Narrow Edge and
Target Pin Wide Edge, a pin edge highlights when it is within a specific distance from the
pointer. If you click, the wire snaps to the highlighted pin edge. This is the smart snapping
feature of wire. You can configure the snap distance (Aperture) in the Layout Editor
Options form. The highlight represents the starting point of wire creation and the length of
the highlight determines wire width. The center of the highlight is represented by a yellow box.
You can cycle the highlight through the available edges within the Aperture distance by using
the Cycle Edge command on the Smart Snapping sub-menu.
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Note: Only the Aperture setting from the Gravity Controls section in the Layout Editor
Options form is used during wire creation. Other settings in the Gravity Controls section
are not considered.
Narrow Edge
Wide Edge
The Use Width options include:
Fixed
Start Pin Nearest Edge
Derived from Constraints
Last Specified
Target Pin Narrow Edge
Target Pin Wide Edge
Start Pin Nearest Edge is the default Use Width option.

Environment variable: wireWidthMode
Fixed
If this check box is selected, the same wire width is used on all the layers. The width value is
derived either from the Width field in the Create Wire form, the width of the starting pin, or
from constraints.
Start Pin Nearest Edge
This option matches wire width to the length of the starting pin edge nearest to the pointer.
The nearest pin is determined by the distance between the pointer and the center of a pin
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edge. This is the default Use Width option. The entire edge highlights within Aperture
distance from the cursor.
A. Starting Wire Creation from Narrow Edge
Use Width = Start Pin Nearest Edge
Wire Creation Along X Axis
Wire Creation Along Y Axis
Wire Width = Length of Nearest Pin Edge

= Length of Narrow Pin Edge

= Length of Narrow Pin Edge
If you select Start Pin Nearest Edge as the width option and also select the Fixed check
box on the Use Width sub-menu, the initial wire width is maintained on all the layers the wire
is changed to. After you complete creating the wire and start creating a new one, the Use
Width mode is still set to Start Pin Nearest Edge. You can tap another pin to reset wire
width to the width of the new pin.
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B. Starting Wire Creation from Wide Edge

Use Width = Start Pin Nearest Edge
Wire Creation Along X Axis
Wire Creation Along Y Axis

= Length of Wide Pin Edge

= Length of Wide Pin Edge
Derived from Constraints

This option matches wire width to the minWidth value as specified in the technology file or
in any applicable constraint group defined at the design or object level. Within Aperture
distance from the cursor, the length of the highlight matches the specified width value.
Last Specified
This option picks the value specified in the Width field in the Create Geometric Wire form,
the Create Wire form or in the spacing table in the Wire Assistant for the applicable layer.
Within Aperture distance from the cursor, the length of the highlight matches the specified
width value.
Target Pin Narrow Edge
This option matches the last segment wire width to the length of the shortest edge of the
target pin. The width of the remaining wire is unaffected.
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Target Pin Wide Edge
This option matches the last segment wire width to the length of the longest edge of the target
pin. The width of the remaining wire is unaffected.
Backup Point
Removes the last digitized point. If a via had been added to the last digitized point, the via is
also removed.
Smart Snapping
This command is available on the Create Single Wire context-sensitive menu in XL and
GXL. You can toggle between Cycle Edge and Use Current Position modes by using the
corresponding bindkeys, Ctrl + Spacebar and Ctrl + Shift + Spacebar, respectively.
Enabled
If selected, it enables the smart snapping mode. If off, the Cycle Edge and Use Current
Position options are not available. If smart snapping is off, you can start creating the wire by
clicking anywhere on a pin; the wire starts from the clicked position.
Environment Variable: weNoSmartSnap
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Cycle Edge
This command enables you to highlight and cycle through the edges available within the
Aperture distance from the cursor. You can, therefore, quickly and precisely choose the
appropriate edge of a level 1 or top-level pin both while starting wire creation and while
completing the wire creation. This command also helps to select the edge of the required pin
from a group of overlapping pins. You can configure Aperture in the Layout Editor Options
form.
Note: Only the Aperture setting from the Gravity Controls section in the Layout Editor
Options form is used during wire creation. Other settings in the Gravity Controls section
are not considered.
Wire creation begins from the edge that is highlighted at the time of click.
Wire creation completes on the edge to which the wire is snapped at the time of
click.
The length of the highlight on the starting pin edge depends on the Use Width option
selection, which also determines the wire width. You can cycle the highlight through the
prospective starting and ending pin edges in the Cycle Edge mode by pressing Ctrl +
Spacebar keys. You can switch to Use Current Position mode by using either the contextsensitive menu or by pressing the Ctrl + Shift + Spacebar bindkeys.
Use Current Position
This command resets the point of starting wire creation and completing wire creation to the
cursors current location. In this mode, you can start or end a wire in empty space as well as
from or at a pin. Therefore, select this command when you do not want to start or end a wire
by snapping to a pin edge. This is the default smart snapping mode when Smart Snapping
is Enabled.
Auto Tap Wire
This option is on by default. See the Auto Tap option in the Layout Editor Options form in
the Virtuoso Layout Suite L User Guide.
Constraint-Aware Editing
Enforces constraints for nets grouped in a bus constraint, differential pairs, shielding wires,
and for setting symmetry. This option is on by default and is available only in XL and GXL.
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The options listed in this section are specifically associated with creating or editing wires. For
remaining options of this form, see the Virtuoso Layout Suite L User Guide.
Snapping
Tap
Wire Editing
Snapping
Snap To Track
For more information about this option, see the Virtuoso Layout Suite L User Guide.
For information about snapping wires to tracks, see Creating Wires Snapped to Track
Patterns.
Tap
See the description of all the options in this section in the Virtuoso Layout Suite L User
Guide.
For controlling filtering out of tapped objects, see tapPreference.
Wire Editing
For information on the Wire and Allow Loops options, see the Virtuoso Layout Suite L
User Guide.
The following options are available in the Wire Editing section only in VLS XL and GXL:
Show Alignment Markers dynamically displays an alignment arrow and an alignment
marker. The arrow points to the closest object on the active flightline. The marker snaps the
cursor to the target object edges and center as you move the cursor.
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Environment variable: showAlignmentMarkers
Alignment Marker
(Flightline)
Alignment Arrow
Blockage: Use Minimum Width allows blockages to be treated as metal shapes with
minimum width when width-based spacing tables are defined in the application default
constraint group. When off, unassigned blockages are treated as metal shapes and their
actual width is used to calculate spacing requirements. The option is off by default.
Environment variable: blockageUseMinWidth
For Create Via options, see the Virtuoso Layout Suite L User Guide.
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Point to Point Form
Connectivity
Net Name enables you to enter a net name for the wire being created.
Width enables you to specify the width of the wire to be created using point-to-point routing.
Environment variable: enableWidthOverride
Fixed Width, if selected, causes the wire width specified in the Width field to be used to
generate wire segments for all layers. If the specified width is less than the minWidth value,
the width that you specify is ignored and the default minWidth value for each layer is used
instead. If the specified width is greater than the minimum maxWidth value, the value that
you specify is ignored and the default minWidth value for each layer is used instead.
Whenever a value specified by you is overridden, a warning message is generated. The
Fixed Width value applies to all the routing layers.
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Layers
Routing column specifies the Top and Bottom layers to define the range of the valid
routing layers. The specified layer range generally intersects the Pin Escape layer
range. If you override the valid top or bottom layer, a color bar appears next to the layer
cyclic field. Placing the cursor over the color bar displays the specified routing layer limit
and the override information, as shown below.
Pin Escape column specifies the Top and Bottom layers to define the layer range. You
can use this field to override the validLayers setting in the virtuosoDefaultTaper
constraint group. If a virtuosoDefaultTaper constraint group does not already exist,
it is created based on the specified Layers, Vias, and Halo values. If you override the
valid top or bottom layers, a color bar appears next to the layer cyclic field. Placing the
cursor over the color bar displays the specified pin escape layer limit and the override
information.
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Valid Vias enables you to select the vias to be used for creating and editing wires.
Clicking the Vias button in the Routing column opens the Setup Valid Vias form, and
clicking the Vias button in the Pin Escape column opens the Setup Taper Vias form.
The forms display the valid standard and custom vias from the application default
constraint group and show the looked up valid vias to use as "checked". You can override
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those vias. If you override the valid vias, a color bar appears next to the Vias button in
the Point To Point form. Placing the pointer over the color bar displays the original and
user-override information.
Halo specifies the taperHalo value of the virtuosoDefaultTaper constraint group.
You can override this value by specifying a positive float value.
Connection Type
Exact Location uses the exact digitized points to create routing between two given
points.
Shortest Connection uses the shortest route for connecting points and may also use
pre-existing wires for creating the route.
Environment variable: p2pSeedStyle
Related topics
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Right-clicking in the design canvas when the Point to Point command is active displays the
Point to Point context-sensitive menu.
Options
Use Width
Backup Point
Auto Tap Wire
Constraint-aware Editing
Options
Opens the Point to Point Form (XL, GXL). You can also use the F3 bind key to open the
options form.
Use Width
This command provides options for setting the wire width based on pin sizes.
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Match Pin Narrow Edge: Matches the wire width to the shortest edge of the pin
Match Pin Wide Edge: Matches the wire width to the longest edge of the pin
Last Specified: Picks the value specified in the Width field in the Point to Point Form
or in the spacing table in the Wire Assistant for the applicable layer
Backup Point
Removes the last digitized point. If a via had been added to the last digitized point, the via is
also removed.
Auto Tap Wire
This option is on by default. See the Auto Tap option in the Layout Editor Options form in
Enforces constraints for differential pairs, for shielding wires, and for setting symmetry. This
option is on by default and is available only in XL and GXL.
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Guided Routing Form
Connectivity
Net Name enables you to specify a net names for the wire or bus being created. If the
nets you specify do not exist in the design, those nets are created.
Probe Nets, if selected, highlights the net as you create the wire or bus.
Wiring
Width enables you to specify the width of the wire to be created using guided routing.
The router uses the specified value if the value is greater than the minWidth value and
less than the maxWidth value of the routing layer on which wire is being created. If the
specified value is less than the minWidth value of the routing layer, the router uses the
minWidth value to create the wire. If the specified value is greater than the maxWidth
value of the routing layer, the router uses the maxWidth value to create the wire.
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Environment variable: enableWidthOverride
Fixed Width, if selected, causes the wire width specified in the Width field to be used to
generate wire segments for all layers. If the specified width is less than the maximum
minWidth value, the width that you specify is overridden by the minWidth value. If the
specified width is greater than the minimum maxWidth value, the value that you specify
is ignored and the default minWidth value for each layer is used instead. Whenever a
value specified by you is overridden, a warning message is generated. The Fixed Width
value applies to all the routing layers.
Bit Spacing enables you to specify the distance between the centerlines of the bus
wires. If no value is specified in this field, the minSpacing value is considered. This field
is available when you create a guided route for multiple wires (bus).
Layers
Routing column specifies the Top and Bottom layers to define the range of the valid
routing layers. The specified layer range generally intersects the Pin Escape layer
range. If you override the valid top or bottom layer, a color bar appears next to the layer
cyclic field. Placing the cursor over the color bar displays the specified routing layer limit
and the override information, as shown below.
Pin Escape column specifies the Top and Bottom layers to define the layer range. You
can use this field to override the validLayers setting in the virtuosoDefaultTaper
constraint group. If a virtuosoDefaultTaper constraint group does not already exist,
it is created based on the specified Layers, Vias, and Halo values. If you override the
valid top or bottom layers, a color bar appears next to the layer cyclic field. Placing the
cursor over the color bar displays the specified pin escape layer limit and the override
information.
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Valid Vias enables you to select the vias to be used for creating and editing wires.
Clicking the Vias button in the Routing column opens the Setup Valid Vias form, and
clicking the Vias button in the Pin Escape column opens the Setup Taper Vias form.
The forms display the valid standard and custom vias from the application default
constraint group and show the looked up valid vias to use as "checked". You can override
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those vias. If you override the valid vias, a color bar appears next to the Vias button in
the Guided Routing form. Placing the cursor over the color bar displays the original and
user-override information.
Halo specifies the taperHalo value of the virtuosoDefaultTaper constraint group.
You can override this value by specifying a positive float value.
Routing Envelope
The routing envelope encloses the actual space required for routing all the nets.
Number of Additional Tracks enables you to specify the additional width of the
routing envelope in track units. The specified value is added to the minimal routing
envelope width that the router automatically calculates. The additional width provides
more routing space to the router. The default value of the additional number of tracks is 4.
The router calculates the envelope width as follows:
envelopeWidth = minimumEnvelopeWidth + (additionalTracks * trackWidth)
where,
minimumEnvelopeWidth is automatically calculated by the router as follows:

minimumEnvelopeWidth = Sum ((width + spacings) of all the nets in the
picked set for the layer used to calculate the trackWidth) +
trackSpacing
Note: The minimal routing envelope width is only an estimate. The router derives
the minimal width by using the width and spacing of all the layers, including the
layers that may not be used in the final routing.
where,
trackSpacing = (spacing) of the net used for trackWidth
additionalTracks is as specified in the Number of Additional Tracks field in

the form.
Note: There can be situations when the router cannot route with the Number of
Additional Tracks field set to 0, especially when routing higher layers.
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trackWidth is the potential track width of the representative net (one with the
smallest potential track width).
potentialTrackWidth = Second smallest (width + spacing) value of all
the legal routing layers for a given net
where,
width = Max ((bus width value, if specified | override cache
value, if present | 0), minWidth constraint through lookup) for
a given layer
spacing = Max ((bus bit spacing value, if specified | override

cache value, if present | 0), minSpacing constraint through
lookup) for a given layer
legal routing layers = Union ((net valid routing layers

constraint through lookup intersected with override routing
layers, if specified), (net taper valid routing layers
constraint through lookup intersected with override pin escape
layers))
Example of Potential Track Width Calculation

Consider the width and spacing values for the metal layers of netA.
Metal1: width=0.1, spacing=0.1
Therefore,
potentialTrackWidth of netA = 0.15+0.15 = 0.3
Example of Envelope Width Calculation

Consider the width and spacing values for three nets: netA, netB, and netC.
netA: width=0.1, spacing=0.1
netB: width=0.2, spacing=0.2
netC: width=0.3, spacing=0.3
Value specified in the Number of Additional Tracks field = 7

In this case,
potentialTrackWidth of netA = 0.1+0.1 = 0.2
potentialTrackWidth of netB = 0.2+0.2 = 0.4
potentialTrackWidth of netC = 0.3+0.3 = 0.6
Therefore,
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trackWidth = 0.2
trackSpacing = 0.1
And,
minimumEnvelopeWidth = [(0.1+0.1) + (0.2+0.2) + (0.3+0.3) + 0.1] = 1.3
envelopeWidth = [1.3 + (7*0.2)] = 2.7
You can modify the additional tracks value in the F3 form anytime while creating the wire.
You can also modify the tracks value in the Guided Routing Envelope section in the Wire
Assistant. The setting applies to the entire envelope, except to the starting and ending
portions (around the starting and ending pins/instPins), where the envelope needs to be
sufficiently wide to allow the connection between the wire and the starting or ending pins/
instPins.
Environment variable: envelopeNumTracks
Gather At Bend, if selected, enables the width of the first and last segments of the
routing envelope to match the width of the pin envelopes they connect to. If this check
box is off, the width of the first and last segments is calculated as the usual routing
envelope width, based on the specified Number of Additional Tracks.
Environment variable: weGuidedRouteGatherAtBend
Related topics
Guided Routing
Guided Bus Routing
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Right-clicking in the design canvas when the Guided Routing command is active displays the
Guided Routing context-sensitive menu.
Options
Use Width
Backup Point
Toggle L90 X/Y
Auto Tap Wire
Options
Opens the Guided Routing Form (XL, GXL). You can also use the F3 bind key to open the
options form.
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Use Width
This command provides options for setting the wire width based on pin sizes.
Match Pin Narrow Edge: Matches the wire width to the shortest edge of the pin
Match Pin Wide Edge: Matches the wire width to the longest edge of the pin
Last Specified: Picks the value specified in the Width field in the Guided Routing Form
or in the spacing table in the Wire Assistant for the applicable layer
Backup Point
Removes the last digitized point. If there is at least a point in the envelope, the last point and
associated data are removed from the envelope. If there is no more point as a result of the
last removed point, the current command is done. Next click starts a new envelope.
Otherwise, next click continues in the current envelope.
Toggle L90 X/Y
Toggles the snap mode of the routing envelope between L90 X First and L90 Y First. The
orientation of the first segment defines whether the snap mode is X or Y First.
Auto Tap Wire
This option is on by default. See the Auto Tap option in the Layout Editor Options form in the
This option is not supported by the Guided Routing command in IC 6.1.4 release.
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Related topics
Guided Routing
Guided Routing Form
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Select Via Form

For a single wire:
Layer
Column
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Via Type
Column
Via Cut Class

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For a bus:
The Select Via form consists of a matrix of layer, via, and cut class lists in three columns.
Each row in the matrix represents a routing layer and contains a button for the layer, a droplist for the vias that can reach that layer from the current layer, and the cut classes, if any are
defined for the cut layer. The first column contains the buttons for the layers. The second
column provides a list of the available via types for the given layer. The third column provides
a list of the cut class choices if a cutClasses constraint is defined for the cut layer of the
selected viaDef in the layerRules section of the technology file. The buttons in the first
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column are color coded by layer color, and the layer name appears on each layer button.
Buttons for layers that can be reached from the current active layer are enabled, while buttons
for inaccessible layers are grayed out. For more information about the cut class values, see
Cut Class in the Create Via Options Form in the Virtuoso Layout Suite L User Guide.
The via cyclic fields are initialized to the current default via for the target layer. To change the
default via for a target layer, choose from the cyclic field beside the target layer.
The displayed layers and vias are defined in the active validLayers and validVias rule.
You can choose either the layer you want to change to or a via type on the layer. The Select
Via form supports the selection of a via cutClass. The wire editor supports the use of the
selected via cutClass.
Rotate Via rotates vias 90 degrees as you place or drag them. You can also rotate pending
vias by pressing the right mouse button. This option is also available in the Create Single Wire
Context-Sensitive Menu.
Via Alignment enables you to align vias as they are digitized during wire or bus creation. You
can choose to align a via either automatically or by selecting a custom alignment option. Vias
are aligned between the edges of via enclosure shapes and the edges of the connecting
wires on the same layer. For example, for a Metal1 to Metal2 via, the via location is
adjusted in a way that the Metal1 wire edge is aligned with the Metal1 via enclosure and
the Metal2 wire edge is aligned with the Metal2 via enclosure. The alignment offsets the
via origin to maintain it at the intersection of the wire end points. If you are adding and aligning
a via stack, the same via alignment is applied to all the vias in the stack.
You can also access the via alignment options from the Create Single Wire Context-Sensitive
Menu.
Automatic, if selected, automatically aligns the digitized via with respect to both the
existing and the new pathSeg. By default, this check box is not selected. After you select
the check box, it remains selected for the remaining session while you digitize more vias.
When the check box is selected, the default alignment of the next via is calculated
automatically. When the check box is not selected, the default alignment of the next via
is Center Center (see Override option setting).
Note: Automatic via alignment is not supported while routing a bus.
Environment variable: autoViaAlignment
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The following figures illustrate the automatic via alignment in three different scenarios
based on the directions in which the next pathSeg of the wire is added.
Initial Via Alignment With Respect to the Existing PathSeg
Change in Via Alignment With Respect to the

PathSeg Being Added
Direction 1
Direction 2
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Direction 3
Override enables you to specify a custom via alignment option that overrides the
automatic alignment. The Override buttons are available only if you click a target layer
button.
Each Override button carries the image of two pathSegsblue and redand a
rectangular via. The two pathSeg colors indicate two layers. You move the wire you are
creating from one layer to the other after digitizing a via. The image on the button
represents the alignment of the via with respect to the two layers. Clicking a button
displays a check mark on the button; the check mark is cleared when you digitize a via
with the selected alignment setting. The Center Center button is available only if the
Automatic check box is selected.
Environment variable: viaAlignment
Top Right
Center Center
Bottom Right
Top Left
Bottom Left
Clear removes the check mark displayed on the selected Override button.
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Pattern helps you specify a pre-defined manner in which multiple vias can be added
simultaneously when routing multiple wires. You can choose from the predefined via patterns:
Auto No Crossing, Auto Crossing, Perpendicular, Diagonal Down, Diagonal Up,
Stagger, In Taper, and Out Taper. The display in the Pattern list next to the pattern name
indicates the pattern in which the vias would be placed for the current routing direction.
Auto No Crossing is the default via pattern. You can either set one of the two automatic via
pattern modes or temporarily override the automatic pattern by setting the pattern to one of
Perpendicular, Diagonal Down, Diagonal Up, Stagger, In Taper, or Out Taper. If a
selected pattern, such as Perpendicular with orthogonal bus wires, creates shorts, then the
dragging of the wires is prevented.
Environment variable: viaPattern
Auto No Crossing: Automatically places the vias in a diagonal pattern in such a way that
bus wires do not cross when making orthogonal transitions. This pattern retains the bus
bit order and might prevent the wire editor from creating jogs if Via Alignment is on.
Auto Crossing: Automatically places the vias in a diagonal pattern in such a way that bus
wires do cross when making orthogonal transitions. This pattern reverses the bus bit,
which might be useful if the starting and targets pins are reversed.
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Perpendicular: Vias are created along a line perpendicular to the incoming direction of
the wires.
Diagonal Down: The right-most or top bus is the longest segment to drop via. This
pattern is most appropriate for right-hand turns.
Diagonal Up: The left-most and bottom bus is the longest segment to drop via. This
pattern is most appropriate for left-hand turns.
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Stagger
In Taper
Out Taper
Via patterns and Fan Out to Vias support both orthogonal and diagonal wire directions.
Related topics
Using Vias
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Stretch Form
The options listed in this section are specifically associated with creating or editing wires. For
remaining options of this form, see the Virtuoso Layout Suite XL User Guide.
Keep Connected allows overlapping wires on the same net to remain connected during
the stretch command. To control the amount of data the wire editor considers when using
Keep Connected, use the environment variable maxNumConnWireElements. If the
limit defined by this environment variable is reached, a message box with a warning
along the following lines will appear:
The number of objects in selection set plus connected objects exceeds the limit
currently set to value through layout environment variable
maxNumConnWireElements. Continuing stretch operation without complete
selection may produce unexpected results such as unconnected nets. You may
increase maxNumConnWireElements at the cost of longer run time.
The following methods are used to keep wires connected:
Inhibit movement that would cause a disconnect.
Stretch connected objects together. In the following example, the via is moved with
the segment being stretched. The attached pathSeg is lengthened.
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Add a new segment between connected objects. In the following example, a

segment is added to the pathSeg to keep the pathSeg connected to the pin.
When stretching a path or a pathSeg that is attached to a non-wire object such as a pin
or polygon, a new "surrogate" segment is added between the path or pathSeg where it
originally connects to the other object.
During the stretch, if the end of the path or pathSeg is moved far enough so that it would
no longer connect to the other object, the surrogate segment appears, maintaining the
connection. If the path or pathSeg is stretched in a way that keeps its end within the other
object, the surrogate segment is not needed, and will, therefore, not appear.
The following conditions apply to segments added when using the Stretch command:
Segments are added when attached objects would otherwise not stay connected.
Segments are added to avoid changing the angle of an existing object.
Added segments may take on a different angle.
Added pathSegs may be diagonal when original segments were orthogonal.
Added segments in paths may be anyAngle when original segments were

orthogonal.
Angles of added segments are controlled by Snap Mode, not Lock Angles.
Attributes of added segments are derived from the attached segments.
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Lock Angles preserves the angles of existing objects during stretch. When off, Lock
Angles may snap a pathSeg to a different legal angle; a path may take on any angle. In
all cases, the non-selected end does not move.
Stretching a corner of a path:

When Lock Angles is on, stretching a corner does nothing.
When Lock Angles is off, stretching the corner of a path moves the corner to any
new location desired, possibly creating any-angle segments and acute angles.
Lock Angles on
Lock Angles off
Stretching a segment in a path:

When Lock Angles is on, the lengths of the neighboring segments are adjusted.
When Lock Angles is off, the segment is moved to any new location desired, possibly
creating any-angle segments and acute angles.
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Forms Reference
Stretching a corner of a pathSeg:

When Lock Angles is on, stretching a corner does nothing.
When Lock Angles is off, stretching the corner of a pathSeg corner to any new
location desired on a 45 degree grid.
Lock Angles on
Lock Angles off
Stretching a segment in a pathSeg:

When Lock Angles is on or off, the lengths of the neighboring segments are
adjusted on a 45 degree grid.
Before
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Lock Angles off
B
Environment Variables
This chapter describes the environment variable that affect options in the Virtuoso Spacebased Power and Automatic Routers.
Automatic Router Environment Variables
Interactive Wire Editing Environment Variables
Automatic Router Environment Variables

Automatic Routing Environment Variables
Form Field Label
Route Environment Variable
Data Type
NA
enableVsrUi
boolean
NA
enableMaximizeCuts
boolean
Common Variables
Route Setup
Special Blockage Treatment setTreatBlockageAsMetalLayers
boolean
Fix Routing Violations

Minimum Spacing
fixErrorsFixMinAreaAtPins
boolean
Minimum Area
fixErrorsErrorTypesMinArea
boolean
Minimum Enclosed Area
fixErrorsErrorTypesMinEnclArea
boolean
Minimum Edge Length
fixErrorsErrorTypesMinEdge
boolean
Minimum Width
fixErrorsErrorTypesMinWidth
boolean
Manufacturing Grid
fixErrorsErrorTypesMfgGrid
boolean
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Form Field Label
Data Type
Routing Grid
fixErrorsErrorTypesRGrid
boolean
Crossing
fixErrorsErrorTypesCrossing
boolean
Port Shorts
fixErrorsErrorTypesPort Short
boolean
Minimum Number of Cuts
fixErrorsErrorTypesNumCut
boolean
Reduce Wire Notches at

Pins
fixErrorsRobustPinConnection
boolean
Align Vias to Wire of Edges
adjustViaToWireEdge
boolean
Reduce Vias
optimizeRouteReduceVias
boolean
Minimize Unprotected Vias
routeSearchAndRepair
boolean
Repair Opens
routeSearchAndRepairCloseOpens boolean
EXTRACT NET
CONNECTIVITY FORM
Pin Style
extractedPinStyle
cyclic
Possible values are:
Labeled Shapes
Connected
Shapes
Whole Net
allowLowerLevelShapeForRoute
boolean
deleteRoutingKeepPower
boolean
Blockage
checkRoutabilityBlockage
boolean
Minimum Space
checkRoutabilityMinSpace
boolean
Minimum Width
checkRoutabilityMinWidth
boolean
Via
checkRoutabilityVia
boolean
Markers Limit Per Type
checkRoutabilityMarkersLimit
boolean
Delete Routing
Keep Routed Power Nets
CHECK ROUTABILITY
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Variable Definitions
setTreatBlockageAsMetalLayers
Directs the router to alter the treatment of blockages. By
default, all pre-existing effective width and/or minimum
spacing properties on blockages will be used. Any
blockages without properties will be treated as a metal
and their actual widths will be used to calculate spacing
requirements.
fixErrorsFixMinAreaAtPins
Directs the router to fix the minimum area violations.
fixErrorsErrorTypesMinArea
Directs the router to fix the minArea rule violations
fixErrorsErrorTypesMinEnclArea
Directs the router to fix the minEnclosedArea rule
violations.
fixErrorsErrorTypesMinEdge
Directs the router to fix the minEdgeLength rule
violations.
fixErrorsErrorTypesMinWidth
Directs the router to fix the minWidth rule violations.
fixErrorsErrorTypesMfgGrid
Directs the router to fix manufacturing grid violations.
fixErrorsErrorTypesRGrid
Directs the router to fix the routing grid violations.
fixErrorsErrorTypesCrossing
Directs the router to eliminate routes on the same net
from crossing over each other.
fixErrorsErrorTypesPortShort
Directs the router to remove multiple connections to
multiple ports on a cell.
fixErrorsErrorTypesNumCut
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Directs the router to fix the minNumCut rule violations.

fixErrorsRobustPinConnection
Directs the router to remove any small metal notches
located near pins by shifting the wires slightly.
adjustViatoWireEdge
Directs the router to move vias such that the edge of the
metal layers in the vias overlap/align with the edges of
the wires. This can reduce the number of small notches
around vias.
optimizeRouteReduceVias
Directs the router to reduce the number of vias by
increasing the number of small same layer jogs.
routeSearchAndRepair
Directs the router to search for and attempt to fix same
net and different net spacing violations.
routeSearchAndRepairCloseOpens
Directs the router to do localized changes to fix the opens
that were caused by fixing spacing violations.
extractedPinStyle
Indicates which shapes become pin shapes. By default,
the drawn pin shape is the only legal point of connection.
deleteRoutingKeepPower
Directs the router to keep the routed power nets when
deleting the routing topology.
checkRoutabilityBlockage
Checks for the pins blocked by top-level blockage or
blockage of another instance.
checkRoutabilityMinSpace
Directs the router to check for minimum pin spacing
violations.
checkRoutabilityMinWidth
Directs the router to check for minimum pin width
violations.
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checkRoutabilityVia
Directs the router to check for via escapes.
checkRoutabilityMarkersLimit
Sets a limit for the number of markers generated for each
violation type by the rteCheckRoutability function.
However, the rteCheckRoutability function still produces
the number of violations shown in the Routability Report
in the CIW.
rte checkRoutabilityMarkersLimit int
positive_integer
Note: If this environment variable is set to 0 or a negative
value, there will be no routability markers generated. In
order to generate the routability markers, the value for this
environment variable should be greater than 0.
enableMaximizeCuts
Attempts to pack more cuts in an overlap area than the
minimum normally selected. The default value is t. You
can turn off this option by specifying
(envSetVal "rte" "detailRouteMaximizeCuts"
'boolean nil).
enableVsrUi
Allows the deprecated IC613 Automatic Routing GUI
form to be used in place of the new IC614 Automatic
Routing GUI form. This is supported for compatibility only
and will be removed in the next release.
allowLowerLevelShapeForRoute
Controls the pin model used by the routers connectivity
extractor. When set to t will model the labeled shape and
connecting shapes on the same layer as a pin. However,
when it is set to nil only the labeled shape will be
modeled as the pin.
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Interactive Wire Editing Environment Variables

The system looks for the system-defined default settings in the following file:
install_dir/etc/tools/layout/.cdsenv
For description of the variables, see Variable Definitions.

Form Field Label
Data Type
NA
spaceFuncName
string
{ function_name
| "" }
NA
setTaperMode
boolean
NA
wireTaperConstraintGroup
string
{
constraintGroup
_name | "" }
NA
weKeepSelectViaOrder
boolean

NA
autoReshape
boolean
Auto Tap
autoTap
boolean
NA
tapPreference
cyclic
Possible values
include: noPrefer,
wire, pin
Include All (Wire) Via Layers layerTapPickWireVia
boolean
Wire
string
wireConstraintGroup
{
constraintGroup
_name | "" }
Auto Merge Geometric
Wires
weAutoMergeWires
boolean
Allow Loops
allowLoops
boolean
Adjust Edited Vias Params
adjustEditedViaParams
boolean
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Form Field Label
Data Type
Show Alignment Markers
showAlignmentMarkers
boolean
Blockage: Use Minimum

Width
blockageUseMinWidth
boolean
maxNumConnWireElements
int
Stretch Form
NA
Value should be a nonnegative integer

Keep Connected
keepWiresConnected
cyclic
Possible values
include: all, spine,
none
Select Via Form

Via Alignment - Automatic
autoViaAlignment
boolean
Via Alignment - Override
viaAlignment
cyclic
Possible values
include: none, topleft, top-center, topright, center-left,
center-center,
center-right, bottomleft, bottom-center,
and bottom-right
Pattern
cyclic
viaPattern
Possible values
include: perp,
diag_1, diag_2,
stagger, out_taper,
in_taper
Create Wire using
createWireMode
cyclic
Possible values
include: paths,
segments
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Form Field Label
Data Type
Create Geometric Wire Form/Create Wire Form

Width
wireWidth
float
Value should be a
positive float number
Offset
wireOffset
float
Value should be a
positive float number
Acute Angle
acuteAngleWire
boolean
Place Via(s) at Last Click
usePrevPointForVia
boolean
Auto Terminate
autoTerminate
boolean
Snap to Pin Center
snapToPin
boolean
Snap to Via Center
snapToViaCenter
boolean
Enable Via Assistance
viaAssistance
cyclic
Possible values
include: snap,
display, none
Create Geometric Wire Form (Segments)/Create Wire Form

Begin
pathSegBeginExt
float
Begin Style
pathSegBeginStyle
cyclic
Possible values
include: truncate,
extend, variable,
diagonal
End
pathSegEndExt
float
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Form Field Label
Data Type
End Style
pathSegEndStyle
cyclic
Possible values
include: truncate,
extend, variable,
diagonal
Fan Out To Vias
fanOutToVias
boolean
Gather Wires
gatherBusWires
boolean
Create Single Wire Context Menu

Use Width
wireWidthMode
cyclic
Possible values
include:
nearestEdgeWidth,
narrowEdgeWidth,
wideEdgeWidth,
constraintsDerviedWi
dth,
userSpecifiedWidth
Smart Snapping Enabled
weNoSmartSnap
boolean
Keep Bit Spacing
weKeepBusWireSpacing
boolean
Create Bus Constraint
weCreateBusConstraint
boolean
Number of Bits
weBusNumBits
int
Width
enableWidthOverride
boolean
Connection Type
p2pSeedStyle
cyclic
Create Bus Form
Point to Point Form
Possible values
include: Exact
Location, Shortest
Connection
Guided Routing Form
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Form Field Label
Number of Additional Tracks envelopeNumTracks
Data Type
int
Gather At Bend
weGuidedRouteGatherAtBend
boolean
weWADefaultSeedCGName
string
Wire Assistant
NA
{
constraintGroup
_name | "" }
NA
weWASeedCGColor
string
{ color | "" }
NA
weWAUserDefColor
string
{ color | "" }
NA
weWAConflictColor
string
{ color | "" }
Flightlines
autoUpdateFlightlines
cyclic
Possible values
include: on, off,
minimum
Wrong Way Tax
allLayersWrongWay
cyclic
Possible values
include: As Is,
Allow, None,
Custom, unknown
Wrong Way Tax Value
allLayersWrongWayCustomValue
int
Value should range
between 0 to 100.
Enforce Gap Spacing on

DiffPair Vias
enforceGapSpacingOnDiffPairVias
boolean
Use Squarish Collinear Vias useOverlapRegionForVia
boolean
Controlled Wire Only
boolean
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300

Variable Definitions
spaceFuncName
Binds the name of the specified function to the space
bar. The default value is " ". The leArrowFunc
function executes the function named by this
environment variable, and the leHiCreateWire
function automatically sets spaceFuncName to
leHiAddWireVia, which accepts Up or Down to
select the default via leading to the next layer above
or below the current layer.
setTaperMode
Controls the global taper routing mode. The setting
determines whether or not the
virtuosoDefaultTaper constraint group is used
during the commands Point to Point, Guided
Routing, and Finish Wire. You can set it as:
envSetVal("rte" "setTaperMode" 'boolean nil)
Default is t.
wireTaperConstraintGroup
The taper constraint group can be used for several
purposes. The primary purpose is to taper the width
of a wire to match the width of the pin to which it
connects. You can also adjust the widths of taper
routing. Many different constraints can be included in
the taper constraint group.
Another purpose is to restrict routing on the poly layer
to the taper and set a taperHalo to control the length
of a wire.
The default value for
wireTaperConstraintGroup is
virtuosoDefaultTaper. When the desired
routing requires tapering, you must define the
virtuosoDefaultTaper constraint group. Doing
so will ensure that the correct layers and widths are
being used for the tapered wires.
weKeepSelectViaOrder
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Displays vias in the Select Via form in the same

order as they are defined in the validVias section
of the technology file. When set to t, the order is not
maintained and the more frequently selected vias are
displayed at the top of the list in the Select Via form.
The default is nil.
autoReshape
Enables reshape which allows you to change the
shape of a selected wire. Clicking on a segment of an
existing wire, digitizing points, and then doubling
clicking highlights the option of the new wiring plus
the start of the initially selected wire. Right clicking
toggles between highlighted reshaped wire options.
Default is nil.
autoTap
Controls whether a design-tap occurs on the first
entry point (t) or not (nil), when you use the
Create Wire command. When auto tap is on, the
current entry layer will seed the form and update
attributes of the wire you create based on the first
point you enter. The tap command does not seed the
Net Name field of the Create Wire form the layout
editor. The Net Name field is seeded in Virtuoso XL
and Virtuoso Chip Editor.
Default is t.
tapPreference
Controls the tapped objects that are filtered out if
there is more than one object in the tapped list that
contains both preferred and non-preferred objects.
noPrefer: No filtering is done. This is the

default setting.
wire: Filters out any non-wire tapped objects.
pin: Filters out any non-pin tapped objects.
If the tapped list contains valid routable objects but

none of them is a preferred object, then the Wire
Editor ignores the tapPreference setting.
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layerTapPickWireVia
The default behavior when tapping on a via is, if
there is an existing segment connected to one layer
of the via (or stack of vias) the intend wire is tap from
the unoccupied layer of the via. This option can be
used to disable the default behavior causing the
Choose Object to Tap form to open.
wireConstraintGroup
Specifies the constraint group used to supply a
default set of constraints for both interactive and
automatic routing. The default constraint group is
virtuosoDefaultSetup. The
virtuosoDefaultSetup constraint group should
contain validVias and validLayers for routing
and possibly other process rules that would override
the foundry rules.
weAutoMergeWires
Automatically merges the connected geometric paths
and collinear geometric pathsegs while creating or
stretching a geometric wire.
Default is t.
allowLoops
When t, allows loops when creating or editing wires.
Default is nil.
adjustEditedViaParams
Re-calculates via alignment if you stretch the wire
connected to the via.
Default is nil.
showAlignmentMarkers
Allows display of alignment marks when the pointer
aligns with a nearby wire, pin, or via that is on the net
you are routing.
blockageUseMinWidth
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When t, blockages are treated as metal shapes with

minimum width. When nil, unassigned blockages
are treated as metal shapes and use their actual
width to calculate spacing requirements.
Default is nil.
maxNumConnWireElements
Controls the maximum number of connected
elements when stretching wires.
Default is 5000.
keepWiresConnected
Specifies whether to keep pathSegs and vias
connected when using the Stretch command. In the
layout editor, wires remain connected if the end
points meet exactly. In the XL layout editor and chip
editor, wires remain connected even if end points do
not meet exactly.
The default is all, which maintains pathSeg-topathSeg and pathSeg-to-via connections during
stretch. spine maintains only spine pathSeg
connections during stretch.
autoViaAlignment
Specifies a via to be automatically aligned with
respect to both the existing and the new pathSeg.
viaAlignment
Specifies a custom via alignment option.
viaPattern
Specifies a pre-defined manner to add multiple vias
simultaneously when routing multiple wires. The
default is diag_1.
createWireMode
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You can create Geometric Wires as paths or

pathSegs (Segments). Paths are not supported by
SOC Encounter as part of a route element. When
saving data to Encounter you must use pathSegs
rather than paths. Using paths for non-orthogonal
routing, you can create off-grid vertices, depending
on the width and angle being used. You can create
on grid 45 degree wires with pathSegs. PathSegs
cannot be used for anyAngle routing and are limited
to orthogonal and diagonal routing. The default is
segments.
wireWidth
Sets a value for the width of the current wire. The
default is 0.6 user units.
wireOffset
Allows you to create a wire a specified distance away
from the cursor. The default is 0.0 user units.
acuteAngleWire
When t, you can create acute angle paths and
segments (pathSegs). You only create pathSegs
using the Create Wire form. When nil, you can
create paths and segments only from 90 degree to
180 degree angles. Acute Angle is available for paths
when the Snap Mode is set to anyAngle or diagonal
and available for pathSegs when the Snap Mode is
set to diagonal.
Default is t.
usePrevPointForVia
When t, the placement of via locations is at the last
click. When nil, vias will float on the end of the
wires as the cursor is moved, ready to be placed at
the next click.
Default is nil.
autoTerminate
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When t, and creating a wire, the wire will

automatically terminate when you creates a vertex
on an existing object with the same net name.
Default is nil.
snapToPin
Snaps the starting point of wires to the origin of pins.
Default is nil.
snapToViaCenter
Snaps the wire to the center of via.
Default is nil.
viaAssistance
Controls via assistance to help determine a legal via
site location where you can add a via using Create
Wire Select Via. This option works when layer
grids are defined in the technology file and when the
Place Via(s) at Last Click option is enabled. Via
assistance does not apply to multiple wire editing.
display shows the possible valid via locations.
snap shows the possible valid via locations as

well as snaps the cursor to the closest valid via
location.
Default is none.
pathSegBeginExt
Sets the beginning extension value is used when you
create a path segment with a variable extension. The
default is the constraint group value for the path
width for the active layer.
pathSegBeginStyle
Sets which beginning extension style is used when
you create a path segment. The default is
truncate.
pathSegEndExt
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Sets the ending extension value is used when you

create a path segment with a variable extension. The
default is the constraint group value for the path
width for the active layer.
pathSegEndStyle
Sets which ending extension style is used when you
create a path segment. The default is truncate.
fanOutToVias
Spreads out the bus wires for via placement.
Default is nil.
gatherBusWires
Gathers the bus wires before the first digitized point.
Default is nil.
wireWidthMode
Matches wire width to pin size, except when set to
constraintsDerviedWidth or userSpecifiedWidth.
nearestEdgeWidth: Matches wire width to the

length of the edge of the pin nearest to the
cursor.
constraintsDerivedWidth: Matches wire

width to the minWidth value as specified in the
technology file or in any applicable constraint
group defined at the design or object level.
userSpecifiedWidth: Uses the value

specified in the Width field in the Create
Geometric Wire form, the Create Wire form or
in the Width/Spacing table in the Wire Assistant
for the applicable layer.
The default is nearestEdgeWidth.

weNoSmartSnap
Disables the smart snapping mode while creating a
wire.
Default is nil.
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weKeepBusWireSpacing
Maintains the same centerline-to-centerline spacing
between the bus wires on all the layers.
Default is nil.
weCreateBusConstraint
Creates a bus constraint automatically for the nets
you specify by using the netName environment
variables or for the ones you pick by selecting
multiple pins.
Default is nil.
weBusNumBits
Specifies the number of wires in the bus.
Default is 2.
enableWidthOverride
Allows the wire width specified in the Width field to
be used by the point to point router when generating
wire segments.
p2pSeedStyle
Controls the type of connection to be followed when
creating a point to point route. The default is
Shortest Connection.
Exact Location uses the exact digitized points

to create routing between two given points.
Shortest Connection uses the shortest route

for connecting points and may also use preexisting wires for creating the route.
envelopeNumTracks
Specifies number of tracks that is used to calculate
the width of the routing envelope while creating a
guided route. The routing envelope represents the
available routing area for the wire.
Default is 5.
weGuidedRouteGatherAtBend
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Matches the width of the first and last segments of

the routing envelope to the width of the pin envelopes
they connect to.
Default is t.
weWADefaultSeedCGName
Enables you to set a user-defined default constraint
group for the Wire Assistant.
The default is .
weWASeedCGColor
Enables you to set up the color of the color bar when
a constraint group from Seed Attributes From a
Constraint Group icon on the Wire Assistant
toolbar is loaded.
You can specify the color as an RGB value or as the
color name. The RGB value must be between 0 and
255. The color name should be specified as one
word. For example:
layout weWASeedCGColor string "NavyBlue"
layout weWASeedCGColor string "255 245 10"
The default is .
weWAUserDefColor
a user-defined constraint group is loaded in the Wire
Assistant.
word. For example:
layout weWAUserDefColor string "NavyBlue"
layout weWAUserDefColor string "255 245 10"
The default is .
weWAConflictColor
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there are any constraint overrides in the Wire
Assistant.
word. For example:
layout weWAConflictColor string "NavyBlue"
layout weWAConflictColor string "255 245 10"
The default is .
autoUpdateFlightlines
Controls the display of flightlines during wire
creation. It is set to on by default. You can hide the
flightline display by setting it to off or display only
three flightlines for each bus by setting it to
minimum.
allLayersWrongWay
Controls wrong way routing.
As Is allows certain wrong way routing if

required.
Allow permits wrong way routing freely.
None does not allow wrong way routing.
Custom lets you control the extent of wrong way

routing you want to permit. When set to Custom,
use the allLayersWrongWayCustomValue
environment variable to specify a value.
Default is As Is.
allLayersWrongWayCustomValue
Specifies the extent of wrong way routing you want to
permit. You can specify a value between 0 to 100, 0
being the level of maximum freedom for creating
wrong way routing and 100 being the level of
maximum restriction for creating wrong way routing.
The default value is 1.
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enforceGapSpacingOnDiffPairVias
Lets you force the application of gap spacing
between consecutive vias of the differential pair.
Default is t.
useOverlapRegionForVia
Creates square vias to connect collinear wires.
Default is nil.
weShowCtrlWireAlignMarkerOnly
Displays the alignment marker only if the control wire
is aligned with its target pin.
Default is t.
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312
C
For information about bindkeys, see Bindkeys and Access Keys.
F keys
F1
F2
F3
F4
F5
F6
F7
Cadence
Help
Save
Toggle
Display
Form
Toggle
Partial
Select
Open
Design
Toggle
Maintain
Connections
DRD
Options
Form
F10
F11
F12
F8
F9
Set Filter
Size,
Toggle
between
values with
each press
Shift-F5
Fully Select
Partially
Selected
Objects
Display/
Hide
Assistants
Alphabet keys
Key to Map: 1=Top row is Control + key
2=Second row is Shift + key
3=Third row is key
4=Last row is Control + Shift + key
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1 Select All
1 Interrupt
1 Deselect All
1 Toggle DRD
Edit Mode
2 Select Area
2 Return
2 Chop
2 Deselect Area 2 Layout Editor

Options
3 Select
3 Go to Level
3 Copy
3 Deselect
4 Via Down
3 Display
Options
4 Create Point to
Point Routing
1 View 0
2 View 32
2 Zoom To Grid
2 Toggle L90 X/Y

(Guided Routing)
3 Fit All
3 Toggle Gravity
3 Create
Instance
4 Finish Entire
Net
K
N Snap mode
options:
1 L90XFirst
1 Select Via
Stack
2 Clear Rulers
2 Merge
2 orthogonal
2 Rotate
3 Draw Rulers
3 Label
3 Move
3 diagonal
3 Create Contact
1 Create Pin
1 Redraw
1 Split
1 Zoom to Set
2 Create
Polygon
2 Design Prop
2 Reshape
2 Search
2 Tree
3 Create Path
3 Object Prop
3 Create
Rectangle
3 Stretch
3 Tap
4 Via Up
4 Create Guided
Routing
1 Type in CIW
1 Close
1 Fit Edit
1 Cycle Select
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2 Redo
2 World View
2 Next View
2 Descend
2 Paste
3 Undo
3 Attach
3 Previous View 3 Edit-In-Place
4 Finish Wire
4 Create
4 Create Bus
Geomteric Wire
(L)
Create Wire (XL,
GXL)
Esc
Tab
Delete
Back Space
1 Zoom In x2
2 Zoom out x2
3 Zoom In
3 Cancel
3 Pan
3 Delete
3 Undo Point
3 Yank
4 Cycle Control
Wire
Return
Spacebar
Enter last point

1 Cycle Edge
(Create Single
Wire contextsensitive menu)
2
3 Select Via
4 Use Current
Position (Create
Single Wire
context-sensitive
menu)
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Arrow keys
Control + key: Fit cell to portion of window
Shift + key: Move Cursor
Key: Pan to portion of cellview
Home
PgUp
top
left
center
right
End
PgDn
bottom
Symbol keys on arrow key pad

/
Sets cursor to
move 1 grid
point. Then
press Shift
and arrow
keys to move
the cursor 1
grid point.
Sets cursor to
move 2 grid
points. Then
press Shift
and arrow
keys to move
the cursor 2
grid points.
Resets cursor Set reference Enter point

.5 grid points. point
Then press
Shift and
arrow keys to
move the
cursor .5 grid
points.
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Enter
D
Routing Assistants
Wire Assistant
The Wire Assistant, available in VLS-XL and GXL, is a dockabe assistant that provides a
single point of access to the most commonly used options for creating and editing a wire.
These options are otherwise available in the corresponding options forms when the Bus,
Wire, Point to Point, or Guided Routing command on the Create Wiring menu is
running, in the Layout Editor Options form, and in the Create Single Wire, Point to Point,
and Guided Routing context-sensitive menus. Some options are available exclusively in the
Wire Assistant.
In addition, the Wire Assistant provides a quick, easy, and single-point access to the
constraint values to be used by the wire editor for creating and editing wires. Using the Wire
Assistant, you can override values for constraints such as minimum width, minimum spacing,
minimum number of cuts, valid layers and valid vias. You can override the constraint values
in the Wire Assistant if the values you specify are:
Greater than the constraint value in the looked-up constraint group for the applicable
minimum rules.
Within the layer/via range in the looked-up constraint group for Routing, Pin Escape
layers and Valid Vias. See Override Constraints section of the Wire Assistant.
For more information about constraint group look up precedence, see Constraint Group
Lookup Precedence.
While routing a net from the Navigator assistant, you can choose to use the Wire Assistant
override values. To do this:
1. In the Navigator assistant, right-click a net.
The Net context-sensitive menu displays.
2. Choose the Route With WA Override command.
Note: This command supports Specialty Routing.
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Unlike the Process Rule Editor, the constraints set up by using the Wire Assistant are not
persistent with an exception. The spacing constraint set up by using the Wire Assistant is
persistent on the resulting wiring (not net). In addition, the constraints set up by using the
Wire Assistant do not impact the Automatic Router and the Batch Checker.
This appendix covers the following topics:
Launching the Wire Assistant on page 318
Wire Assistant User Interface on page 319
Wire Assistant Options on page 324
Launching the Wire Assistant

You can adopt one of the following methods to access the Wire Assistant in VLS XL and
GXL:
Select Window Assistants Wire Assistant.
Right-click in the main menu or toolbar area and select Wire Assistant.
Once selected, Wire Assistant is added as a docked assistant pane within the current
session window. By default, Wire Assistant is positioned in the lower right area of the
session window.
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Routing Assistants
Wire Assistant User Interface
Toolbar
Sections for Configuring Wire Creation

and Editing
You can add or remove sections.
The Wire Assistant comprises of two components, the toolbar and the different sections for
configuring settings while creating and editing wire or a bus. You can add or remove these
sections to or from the Wire Assistant. You can also configure the fields and options to
appear in each section, as required.
The toolbar contains the following buttons:
Configure Wire Assistant
Clear Override Constraints

: Resets all the override values to the constraint
values in the default constraint group. It also resets the constraint group, if selected from
the Seed Attributes From a Constraint Group list, to the default constraint group
defined in the Wire setting in the Layout Editor Options form.
January 2011
: Opens the Wire Assistant Options Form.
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Routing Assistants
Save Override Constraint Values

Form.
Seed Attributes From a Constraint Group

: Enables you to select a constraint
group to use for seeding the values in the Override Constraints section the width and
spacing table, the valid routing layers and vias, and the valid taper layers, vias, and taper
halo. The constraint groups defined in your technology file appear in the drop-down list
from the button.
: Opens the Save Override Constraint Values
Wire Assistant Options Form

This form opens when you click the Configure Wire Assistant button on the Wire Assistant
toolbar.
Top-Level Node
Represents the Wiring section in the
Wire Assistant
Child Node
Represents an option in the Wiring
section on the Wire Assistant
Use this form to configure sections and the options in each section that you want to display
or hide in the Wire Assistant for a session. In this form, the top-level nodes (next to the +
sign) represent titles of sections that appear in the Wire Assistant. The child nodes of these
top-level nodes represent the fields and options that are available for the respective sections.
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Selecting the check box next to the top-level or child node displays the respective section and
the field or option in a section, respectively, in the Wire Assistant.
The Files list displays all the possible locations where you can save the settings of the Wire
Assistant Options form.
Use the Save button to save the settings in the Wire Assistant Options form. By default,
the settings are stored the waConfig.il file in the following directory:
./.cadence/dfII/wireEditor/waConfig.il
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The following figure shows the contents of a sample waConfig.il file, which indicates the
visibility of fields and options in the Wire Assistant:
(waConfig (list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
(list
"Net Name" t)
"Probe Nets" nil)
"Override Constraints" t)
"Fixed Width" t)
"Allow Loops" nil)
"Snap To Pin Center" t)
"Snap To Via Center" t)
"Snap to Track" nil)
"Adjust Edited Vias Params" nil)
"Automatic Via Alignment" t)
"DRD Mode" nil)
"Flightlines" nil)
"Wrong Way Tax" t)
"Use Grid" nil)
"Blockage: Use Minimum Width" t)
"Enforce Gap Spacing on DiffPair Vias" nil)
"Use Truncate End Style at Pins" nil)
"Attempt to Use Double Cut Vias" t)
"Purposed Routing" nil)
"Specify Via Cuts" t)
"Use Squarish Collinear Vias" nil)
"Show Alignment Markers" t)
"Auto Terminate" nil)
"Place Via(s) at Last Click" nil)
"Use Width" t)
"Snap Mode" nil)
"Pin Strapping Layer" nil)
"Taper Pin Width" t)
"Remove Preroute Dangles" t)
"Wrong Way Tax" t 'netRoute)
"Use Grid" nil 'netRoute)
"Pin Strapping Layer" nil 'netRoute)
"Blockage: Use Minimum Width" t 'netRoute)
"Enforce Gap Spacing on DiffPair Vias" nil 'netRoute)
"Attempt to Use Double Cut Vias" t 'netRoute)
"Taper Pin Width" t 'netRoute)
"Remove Preroute Dangles" t 'netRoute)
"Use Simple Pattern for Pin-to-Trunk" nil 'netRoute)
"P2P Connection Type" t)
"Guided Routing Envelope" t)
"Layer Mode" t)
"Direction Mode" t)
"Match Widths and Spacings" t)
"Pattern" t)
"Tapping" nil)
)
)
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Routing Assistants
Save Override Constraint Values Form
This form opens when you click the Save Override Constraint Values button on the Wire
Assistant toolbar.
Use this form to save the override values you specify in the Wire Assistant to another
constraint group. You can specify the name of the constraint group in which to save the
override values in the Constraint Group Name field. When you click OK in the form, the
form closes and a message informing you about the creation of the constraint group is
generated in the CIW.
Based on the values you override, the following three types constraint groups are created:
<name>_WA_Net: For overrides to width, spacing, preferred routing direction, valid

layers, and valid vias
<name>_WA_Design: For overrides to the layer directions
<name>_WA_TAPER: For overrides to the taper values
The constraint group name you specify is suffixed with _WA_Net, _WA_Design, or
_WA_TAPER, based on the values you override.
Note: If there are no override values, the corresponding <name>_WA_* constraint group is
not generated.
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Routing Assistants
The new constraint group is created at the design-level. You can view the updated constraints
in the constraint group by using the Process Rule Editor, as shown below.
In the Wire Assistant, you can access the new constraint group from the Seed Attributes
From a Constraint Group button on the toolbar. Corresponding to the three types of
constraint groups created (_WA_Net, _WA_Design, and _WA_Taper), only one entry is
created in the Seed Attributes From a Constraint Group drop-down list. Selecting that
single entry from the Seed Attributes From a Constraint Group list updates all the values
in the Wire Assistant from the three constraint groups.
Wire Assistant Options

The Wire Assistant provides access to various options under the sections described here.
For the Wire Assistant options that are available in other GUIs or context-sensitive menus,
it has been indicated so. For others, it can be assumed that they are available exclusively in
the Wire Assistant.
Note: Options enabled or disabled or parameter values changed using the Wire Assistant
are updated in the corresponding GUIs. Similarly, for GUI options that also exist in the Wire
Assistant, any updates in the GUI reflects in the settings in the Wire Assistant.
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The table below lists all the sections you can enable in the Wire Assistant and the options
available in each section.
Wire Assistant
Section
Wire
Assistant
Section
Options
Options
Connectivity
Net Name
Probe Nets
Finish Net
Pin Strapping Layer

Taper Pin Width
Remove Preroute Dangles
Override
Constraints
Width and Spacing table

Minimum Number of Cuts
Routing Layers
Pin Escape Layers
Valid Vias
Halo
Net Route
Wrong Way Tax

Use Grid
Pin Strapping Layer
Width
DiffPair Vias
Attempt to Use Double
Cut Vias
Taper Pin Width
Use Simple Pattern for
Pin-to-Trunk
Wiring
Fixed Width
Allow Loops
Snap To Pin Center
Snap To Via Center
Snap to Track
Adjust Edited Vias Params
Automatic Via Alignment
DRD Mode
Enable Pushing
Flightlines
P2P
Connection
Type
Exact Location
Shortest Connection
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Routing Assistants
Wire Assistant
Section
Wire
Assistant
Section
Options
Options
Assisted Routing
Wrong Way Tax

Guided
Use Grid
Routing
Envelope
Width
DiffPair Vias
Use Truncate End Style at
Pins
Attempt to Use Double Cut
Vias
Remove Pre-Route Dangles
in P2P
Remove Tangles Dangles in
Finish Wire
Purposed Routing
Number of Additional
Tracks
Gather At Bend
Create Wire(s)
Specify Via Cuts

Tapping
Use Squarish Collinear Vias
Show Alignment Markers
Controlled Wire Only
Auto Terminate
Place Via(s) at Last Click
Use Width
Snap Mode
Auto Tap
Tap Layer
Tap Attributes
Tap End Styles
Select from Overlaps
Include All (Wire) Via
Layers
Tap Purpose List
By default, the Wire Assistant displays the Connectivity, Override Constraints, and
Wiring sections.
Connectivity
These options are available in the Create Wire Form, Create Bus Form, Point to Point Form,
and Guided Routing Form.
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Routing Assistants
Net Name enables you to specify a net name for the current wire. The created wire is
added to the specified net. A new net is created if the one specified does not already
exist.
Probe Nets executes the probe command as soon as you digitize a new net object when
starting a wire.
Override Constraints
The text above the table indicates the constraint group used to seed the table. The Default
constraint group is derived from the Wire setting in the Layout Editor Options form (for
more information about the form, see Virtuoso Layout Suite L User Guide). You can
change the constraint group from which to seed the table by selecting a value from the Seed
Attributes From a Constraint Group list on the Wire Assistant toolbar. If you select a
different value from the Seed Attributes From a Constraint Group list, the Default label
changes to Seeded From. By using weWADefaultSeedCGName, you can seed a default
constraint group on the Wire Assistant.
Some of the features of the Override Constraints section include:
The constraint group selected from the Seed Attributes From a Constraint Group
list does not change the application default constraint group setting in the Wire section
of the Layout Editor Options form.
While overriding the constraint values in the Width and Spacing table, ensure that the
values specified for the Width, Spacing, and Minimum Number of Cuts are greater
than or equal to the values for the corresponding minimum rules in the looked up
constraint group. In addition, the valid routing layers and valid vias should be a subset of
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Routing Assistants
the looked up constraint group for Routing and Pin Escape layers and Valid Vias.
Ensure that the override values do not create artwork that will immediately violate an
existing looked-up constraint value.
Modification of the values in the Override Constraints section does not change the
content of the constraint group in the OpenAccess database.
If you override any value in the Override Constraints section, the change is indicated
by colored fields in the table and by color bars next to the other updated fields. The
figures below illustrate some examples where the constraint values are overridden in the
table and for other fields.
Color Highlighting in the Table Indicates

Constraint Override
Color Bar Indicates Constraint Override
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Routing Assistants
You can place the pointer on the colored fields in the table or on color bar to view the
override information in a tool tip, as shown in the figures below.
Width and Spacing Table allows you to override the preferred routing direction, the
width, and the spacing for the layers to be used while creating wires. You can override
the current preferred routing direction for each layer by selecting a different value from
the Dir list. The routing directions supported by the Wire Assistant include Horizontal
, Vertical
, and None
. Any update to the routing direction for a layer in the
Layers assistant is automatically updated in the Dir column for that layer in the Wire
Assistant.
You can click in the Width and Spacing fields to edit them. If a net has been specified
in the Net Name field, then the net width and spacing overrides, if any, are visible in the
table. If you change any width value, then the Use Width option in the Create Wire(s)
section automatically sets to Last Specified, if not already.
If you select a non-drawing, voltage-aware layer purpose to create a wire, the layer
purpose is represented in the Layers column in the
<layer:purpose_abbreviation> format, as in metal1:dr4.
Note: The wire editor allows the creation of bus wires even if the terminals/instance
terminals distance is less than the override spacing, regardless of the current DRD
checking mode. After creating the bus, you should run the Batch Checker on the result.
The Batch Checker will flag error on the pins/instPins that do not have enough spacing
for the override spacing value. For more information about the Batch Checker, see
Chapter 7, Space-based Router Batch Checking.
Minimum Number of Cuts enables you to override the minNumCut rule value for
creating and editing wires. This setting is applied to the next via selected from the Select
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Routing Assistants
Via form. If the override value is less than either the technology rule or the current
constraint group on the net or on the design, then the value specified in the Wire
Assistant is reset to the minimum value.
Routing column enables you to select the Top and Bottom valid routing layer limits and
overrides the validLayers setting in the selected constraint group. The specified layer
range generally intersects the Pin Escape layer range. If you place the pointer at the
Routing column, a tool tip displays information about the applicable valid routing layers
and valid routing vias and the constraint group from which they are derived. In the
following example, the applicable valid routing layers are Metal1 to Metal6.
Tool Tip Showing

Information about the
Valid Routing Layers
Pin Escape column enables you to select the Top and Bottom layer limits and overrides
the validLayers setting in the virtuosoDefaultTaper constraint group. If a
virtuosoDefaultTaper constraint group does not already exist, it is created based
on the specified Layers, Vias, and Halo values. If you place the pointer at the Pin
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Routing Assistants
Escape column, a tool tip indicates that the pin escape layers are controlled through the
taper constraints.
Note: The wire editor follows the union of both the Top and Bottom Routing and Pin
Escape layers setting in the Wire Assistant. For example, if the Routing Top and
Bottom layers are set to Metal4 and Metal1, respectively, and the Pin Escape Top
and Bottom layers are set to Metal5 and Metal2, respectively, the routing interval
assumed by the wire editor is between Metal5 and Metal1.
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Valid Vias enables you to select the vias to use for creating and editing wires. If you click
the Vias button in the Routing column, it opens the Setup Valid Vias form.
If you click the Vias button in the Pin Escape column, it opens the Setup Valid Vias
form.
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Routing Assistants
These forms display the valid standard and custom vias from the application default
constraint group and show the looked up valid vias to use as checked. You can override
those vias. The vias in the Routing column set up the validVias rule in the applicable
wire constraint group. The vias in the Pin Escape column set up the validVias rule in
the virtuosoDefaultTaper constraint group. If a tapped net does not have a
corresponding virtuosoDefaultTaper constraint group, the Setup Taper Vias form
lists the global taper vias.
If the Finish Wire, Guided Routing, or Point to Point command needs to drop a wire
to a via that is not part of the valid list, the command fails and generates an appropriate
message.
Halo enables you to override the taperHalo value of the virtuosoDefaultTaper
constraint group. You can override this value by specifying a positive float value.
The Routing Layers, Pin Escape Layers, Valid Vias, Halo options are also available
in the Point to Point Form and the Guided Routing Form.
Wiring
These options are available in the Create Bus Form, Create Wire Form, Create Bus Form,
Select Via Form, and the Layout Editor Options Form.
Fixed Width, if selected, maintains the same specified width on all the layers while
creating wires. If this option is not selected, then the wire width is derived from settings
of the Use Width option in the Create Wire(s) section. If the Fixed Width check box is
selected before the Create Wire, Point to Point, and Guided Routing commands are
run and the value specified in the text field does not violate the minWidth value of the
layer being edited, the Fixed Width value is saved for subsequent create command
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Routing Assistants
runs. However, if the check box is not selected or the specified value violates the
minWidth value of the layer being edited, the Fixed Width value is not saved.
If you change the value in the Fixed Width text field or select the Fixed Width check
box, the Use Width option in the Create Wire(s) section automatically sets to Last
Specified. Conversely, if the Fixed Width check box is selected and you update the
Use Width option to a value other than Last Specified, the Fixed Width check box
automatically clears.
Allow Loops allows the creation of loops when creating or editing wires. This option is
available in the Layout Editor Options Form. For more information about this option, see
Snap to Pin Center snaps wires to the center of rectangular pins or of pins that are
created as polygons and have rectangular shapes. The option snaps wires to the starting
and ending pins. This option applies to wires created using Create Geometric Wire,
Create Wire, Point to Point, Guided Routing, and Finish Wire commands. This
option is available in the Create Wire Form, Create Bus Form, and Create Bus Form.
Snap to Via Center snaps wires to the center of vias. This option applies to wires
created by using Create Geometric Wire, Create Wire, Point to Point, Guided
Routing, and Finish Wire commands. This option is available in the Create Wire Form,
Create Geometric Wire Form in XL and GXL, and Create Bus Form in XL and GXL.
Snap to Track, if selected, snaps all the wire elements (paths, path segments and vias)
to the routing grid while using the Create Wire or the assisted routing commands. If on,
this option controls the cursor snapping to track grid and forces routing on grid where
pins are on grid. The check box is off by default.
Tip
Select the Snap to Track check box during Point to Point and Guided Routing
to ensure that the intermediate click points are on grid.
In the case of specialty routing, symmetric routing is snapped to the routing grid if the
axis is on the grid. If the axis is not on the grid, only the master net is guaranteed to be
on the grid.
Tip
To click at an off-grid pin, you can switch off the Snap to Track check box
temporarily.
This option is also available in the Layout Editor Options Form. For more information
about this option, see the Virtuoso Layout Suite L User Guide.
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Routing Assistants
Adjust Edited Vias Params, if selected, enables the re-evaluation of via parameters.
For example, with Automatic Via Alignment on, you stretch a wire in such a way that
the via needs to be re-aligned, the re-alignment is done if the Adjust Edited Vias
Params check box is selected; if the Adjust Edited Vias Params check box is not
selected, the via is not re-aligned and stays the way it was before stretching the wire.
Automatic Via Alignment, if selected, automatically aligns the digitized via with
respect to both the existing and the new pathSeg. By default, this check box is not
selected. This option is available in the Select Via Form.
Note: Automatic via alignment is not supported while routing a bus.
DRD Mode enables you to specify the DRD editing mode. If you select this check box,
both Enforce and Notify modes are switched on. With Enforce, the currently running
command fails and a message is generated when there are DRD violations. With Notify,
a message is generated when there are DRD violations but you can continue with the
edit operation. The DRD Mode option is available in the DRD Options form.
Enable Pushing, if selected, pushes the existing wires and vias aside while routing
to maintain current clearance rules. If you select this check box, both Vias and
Stack are enabled. Vias enables the pushing of both vias and pathSegs. Stack
enables the pushing of wires that have stacked vias. The stacked vias are kept as is.
Flightlines controls the display of flightlines during Wire, Bus, and Guided Routing
commands. They are displayed by default.
on displays the flightlines. This is the default setting.
off hides the flightlines. You can gain performance improvements by using this
setting in the case of large buses.
Note: The Finish Wire and Finish Entire Net commands display flightlines even
if the Flightlines setting in the Wire Assistant is set to off.
minimum displays only three flightlines per bus - one for the central control wire and
the other two for the extreme side bus bits (left and right or top and bottom bus bits).
This setting applies only to bus mode. You can gain performance improvements by
using this setting in the case of large buses.
Environment Variable: autoUpdateFlightlines
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Routing Assistants
Assisted Routing
This section is automatically enabled in the Wire Assistant when you start the Bus, Wire,
Point to Point, or Guided Routing command from the Create Wiring menu and
Assisted Routing is selected in the Wire Assistant Options form. This section remains
available in the Wire Assistant as long as one of these commands is running.
Wrong Way Tax controls whether or not wrong way routing is permitted.
As Is uses the default setting as initialized by the router. This setting can allow
certain wrong way routing if required. This is selected by default and maps to the tax
value 1.
Allow permits wrong way routing freely. This maps to the tax value 0.
None does not allow wrong way routing. The wrong way tax is 100.
Custom lets you control the extent of wrong way routing you want to permit. You
can select this option and specify a value in the Wrong Way Tax Value combo box.
The default value is 1. You can increase the value to impose higher restriction on
wrong way routing.
Environment variable: allLayersWrongWay
Wrong Way Tax Value indicates the extent to which wrong way routing can be created.
This cyclic field is placed next to the Wrong Way Tax combo box. This field is editable
only when Wrong Way Tax is set to Custom. You can specify a value between 0 to 100,
0 being the level of maximum freedom for creating wrong way routing and 100 being the
level of maximum restriction for creating wrong way routing.
Environment variable: allLayersWrongWayCustomValue
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Routing Assistants
Use Grid forces the maximal routing on grid. You can use this option where pins are off
the grid. The segments other than the ones directly connecting to the off-grid pins are
snapped to the routing grid. You can choose between Manufacturing and Routing
grids. The default setting is Manufacturing.
Note: In the default wire editor constraint group, you can define the routing grid by using
an OpenAccess track pattern or by a routingGrids constraint.
Blockage: Use Minimum Width uses minSpacing to route blockages (blockages
are treated as metal shapes with minimum width) if width-based spacing tables are
defined in the application default constraint group. If this check box is not selected,
unassigned blockages are treated as metal shapes and their actual width is used to
calculate the spacing requirements. This option is available in the Layout Editor Options
Form.
Environment variable: blockageUseMinWidth
Enforce Gap Spacing on DiffPair Vias forces the application of gap spacing between
consecutive vias of the differential pair. This check box is selected by default.
Environment variable: enforceGapSpacingOnDiffPairVias
Use Truncate End Style at Pins enables the router to use pathSegs with truncate end
style when reaching the target pin. This option applies to Point to Point, Guided
Routing, and Finish Wire commands. This check box is selected by default.
Attempt to Use Double Cut Vias enables the assisted routing commands to place
double cut vias if the space allows. However, in congested areas where there is no space
for a double cut via, the assisted routing commands add single cut vias.
Remove Pre-Route Dangles in P2P, if selected, the Point to Point routing command
removes any pre-existing dangles connected to the from point and to point of the
current command. This check box is off by default.
Remove Target Dangles in Finish Wire, if selected, the Finish Wire command
removes any pre-existing dangles on the target segment. This prevents creation of
dangles between the last segment of the Create Wire command and first segment of
the Finish Wire command. This check box is off by default.
Purposed Routing enables you to select the non-drawing, voltage-aware and drawing
purposes if the voltage-related purposes are defined in the techPurposes section of
your technology file.
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Routing Assistants
Create Wire(s)
This section is automatically enabled in the Wire Assistant when you start the Create
Wiring Wire command and Create Wire(s) is selected in the Wire Assistant Options
form. This section remains available in the Wire Assistant as long as the Wire command is
running.
Specify Via Cuts enables you to specify the number of Rows and Columns for the
next via to be placed while creating a wire. By using this option, you can create the
required via array while creating the wire.
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Routing Assistants
Use Squarish Collinear Vias enables the wire editor to use a square via to connect
two collinear wires. This check box is off by default. The following figures show the
resultant when this check box is on and off.
Use Squarish Collinear Vias is off.
Use Squarish Collinear Vias is on.
Environment variable: useOverlapRegionForVia

Show Alignment Markers, if selected, dynamically displays an alignment arrow and
an alignment marker. The arrow points to the closest object on the active flightline. While
creating a bus, the alignment marker appears when any of the bus bits align with their
target pins.
Alignment Marker
Alignment Arrow
This option is available in the Layout Editor Options Form.

Controlled Wire Only displays an alignment arrow and an alignment marker only
if the control wire is aligned with its target pin. For more information about control
wires, see Using the Control Wire. This check box is selected by default.
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Routing Assistants
Environment Variable: weShowCtrlWireAlignMarkerOnly
Auto Terminate completes the Wire command as soon as a point is digitized on a
flightline target object (pin , existing wire, or via). When creating a bus, Auto Terminate
snaps all wires in the bus to the target pins. This check box is selected by default. It is
also available in the Create Geometric Wire Form in XL and GXL and Create Wire Form.
Place Via(s) at Last Click, if selected, creates vias at the last click location. Via
location is digitized before the selection of the via. If this check box is not selected, vias
float as the pointer moves, ready to be placed at the next click. This option is available in
the Create Bus Form and Create Wire Form.
Enable Via Assistance, if selected, helps to determine a legal via site location where
you can add a via during routing and not violate design clearance rules. This option
works when layer grids are defined in the technology file. The check box is enabled when
the Place Via(s) at Last Click check box is selected. Via assistance does not apply to
multiple wire editing. This option is available in the Create Geometric Wire Form in XL
and GXL and Create Wire Form.
Use Width provides options for setting wire width based on pin sizes.
Start Pin Nearest Edge matches wire width to the edge of the starting pin nearest
to the pointer. The edge closest to the pointer highlights automatically if the cursor
is at a specific distance from the edge. You can configure this distance (Aperture)
in the Layout Editor Options form.
Derived from Constraints matches wire width to the minWidth value as
specified in the technology file.
Last Specified picks the value specified in the Wire Width Value field in the
Wiring section. If the Fixed Width check box in the Wiring section is selected and
you update the Use Width option to a value other than Last Specified, the Fixed
Width check box automatically clears. If you change the value in the Fixed Width
field or select the Fixed Width check box, then Use Width automatically sets to
Last Specified.
Snap Mode controls how the cursor snaps when you create a wire. This option is
available in the Create Bus Form and Create Wire Form.
Acute Angle, if selected, enables you to create acute angle paths and segments. If the
check box is not selected, you can create paths only from 90 degree to 180 degree
angles. Acute Angle is available only when Snap Mode is set to diagonal. This option
is available in the Create Bus Form and Create Wire Form.
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Routing Assistants
Finish Net
This section is automatically enabled in the Wire Assistant when you start the Wire or Bus
command from the Create Wiring and Finish Net is selected in the Wire Assistant
Options form. This section remains available in the Wire Assistant as long as the Wire
command is running.
Pin Strapping Layer adds a strapping via at the pin location or as close as possible to
the pin when you run the automatic Finish Wire or Finish Entire Net command. You
can set the strapping layer as Poly or Metal. This option helps to minimize the use of
poly while performing device-level routing of multi-finger devices that have poly layer
pins.
Taper Pin Width enables the router to create pathSegs connecting to top-level pins or
instPins using width matching the target pin. This option applies to the Finish Wire and
Finish Entire Net commands.
Remove Preroute Dangles checks for and removes wire dangles, if any, when you run
the Finish Entire Net command.
Net Route
This section is automatically enabled in the Wire Assistant if you select a pathSeg or a net
in the Navigator assistant and if Net Route is selected in the Wire Assistant Options form.
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Routing Assistants
This section remains available in the Wire Assistant as long as the pathSeg or the net
remains selected.
See Assisted Routing for these options:
Wrong Way Tax
Wrong Way Tax Value
Use Grid
Blockage: Use Minimum Width
Enforce Gap Spacing on DiffPair Vias
Attempt to Use Double Cut Vias
See Finish Net for these options:
Pin Strapping Layer
Taper Pin Width
Use Simple Pattern for Pin-to-Trunk, if selected, allows only pin-to-trunk routing. If
this check box is off, pin-to-trunk and trunk-to-trunk routing is performed.
Important
Cadence recommends that you lock the nets after performing pin-to-trunk routing to
ensure that any subsequent routing by assisted routing commands does not rip
them up and re-route them as regular nets.
You can view the current Route Pattern on a net in the Property Editor assistant after
selecting the net in the Navigator assistant. The Route Pattern field is editable and can
take one of these values: steiner, balanced, trunk.
Note: Wire Assistant supports specialty routing. For more information about trunk
topologies and specialty routing, see the Virtuoso Routing IDE User Guide.
P2P Connection Type
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Routing Assistants
Wiring Point to Point command and P2P Connection Type is selected in the Wire
Assistant Options form. This section remains available in the Wire Assistant as long as
the Point to Point command is running.
These options are also available in the Point to Point Form.
Exact Location uses the exact digitized points to create routing between two given
points.
Shortest Connection uses the shortest route for connecting points and may also use
pre-existing wires for creating the route.
Guided Routing Envelope
Wiring Guided Routing command and Guided Routing Envelope is selected in the
Wire Assistant Options form. This section remains available in the Wire Assistant as long
as the Guided Routing command is running.
These options are available in the Guided Routing Form.
Number of Additional Tracks enables you to specify the additional width of the
routing envelope in track units. The specified value is added to the minimal routing
envelope width that the router automatically calculates. The additional width provides
more routing space to the router. The default value of the additional number of tracks is 4.
Gather At Bend, if selected, enables the width of the first and last segments of the
routing envelope to match the width of the pin envelopes they connect to. If this check
box is off, the width of the first and last segments is calculated as the usual routing
envelope width, based on the specified Number of Additional Tracks.
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Routing Assistants
Tapping
See the Layout Editor Options form in the Virtuoso Layout Suite L User Guide for the
options in this section.
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Virtuoso Space-based Router User Guide

Product Version 6.1.5

20062011 Cadence Design Systems, Inc. All rights reserved.

Virtuoso Space-based Router User Guide

Licensing in Virtuoso Space-based Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enabling the Space-based Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technology File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

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Automatic Router Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

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The Virtuoso design environment and application infrastructure mechanisms designed

The OpenAccess version 2.2 technology file.

Licensing in Virtuoso Space-based Router

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Installation, Environment, and Infrastructure

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For information on a collection of general layout tools designed to streamline command

For information on Component Description Format, see the Component Description

Relative Object Design and Inherited Connections

Typographic and Syntax Conventions

Indicates text you must type exactly as it is presented.

Indicates text that you must replace with an appropriate

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Denotes an optional argument. When used with vertical bars,

Separates a choice of options.

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Separates the possible values that can be returned by a

Indicates names of manuals, menu commands, form buttons,

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Enabling the Space-based Router

Using Layout XL Extraction

Hierarchical Level Control

Enabling the Space-based Router

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Highlight Locked Nets

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Straighten Wires View Area

Straighten Wires Entire Cell View

Straighten Wires Selected Nets