Lcdf3 Chap 03

Digital Design with an Introduction to the
Verilog HDL
Chapter 3 Gate-Level
Minimization
Overview
Chap 3
The Map Method

Four-Variable K-Map
Product-of-Sums Simplification
Dont-Care Conditions
NAND and NOR Implementation
Exclusive-OR Function
Pearson Education, Inc.

Modified by Y. L. Li, CS/NCTU
Digital Design with Verilog Practice
bL1
Circuit Optimization
Chap 3
Goal: To obtain the simplest

implementation for a given function
Optimization is a more formal approach to
simplification that is performed using a
specific procedure or algorithm
Optimization requires a cost criterion to
measure the simplicity of a circuit
Two distinct cost criteria we will use:
Literal cost (L)
Gate input cost (G)
Gate input cost with NOTs (GN)
2004 Pearson Education, Inc.
Modified by Y. L. Li, CIS/NCTU
Logic & Computer Design Fundamentals
3
bL1
boris Li, 2015/3/24
Literal Cost
Chap 3
Literal a variable or its complement

Literal cost the number of literal
appearances in a Boolean expression
corresponding to the logic circuit diagram
Examples:
F = BD + A BC + A C D
L=8
F = BD + A BC + A B D+ AB C
L = 11
F = (A + B)(A + D)(B + C + D)( B + C + D) L = 10
Which solution is best? (first verify the equality)

Gate Input Cost

Chap 3
Gate input costs - the number of inputs to the gates in the

implementation corresponding exactly to the given equation or
equations. (G - inverters not counted, GN - inverters counted)
For SOP and POS equations, it can be found from the equation(s)
by finding the sum of:
all literal appearances
the number of terms excluding terms consisting only of a single literal,(G)
and
optionally, the number of distinct complemented single literals (GN).
Example: which solution is best ?

F = BD + A BC + A C D
G = 11, GN = 14
F = BD + A BC + A B D+ AB C
G = 15, GN = 19
F = (A + B)(A + D)(B + C + D)( B + C+ D) G = 14, GN = 17
Cost Criteria (continued)

Chap 3
Example 1:
GN = G + 2 = 9
L= 5
F=A+ B C + BC
G= L+ 2 = 7
B
C
A
L (literal count) counts the AND inputs and the single

literal OR input.
G (gate input count) adds the remaining OR gate inputs
GN(gate input count with NOTs) adds the inverter inputs
Cost Criteria (continued)

Chap 3
Example 2:
A
B
C
F = A B C + AB C
L = 6 G = 8 GN = 11
F = (A + C)( B + C)( A + B)
L = 6 G = 9 GN = 12
Same function and same

A
literal cost
B
But first circuit has better C
gate input count and better
gate input count with NOTs
Select it!
Boolean Function Optimization

Chap 3
Minimizing the gate input (or literal) cost of a (a set

of) Boolean equation(s) reduces circuit cost.
We choose gate input cost.
Boolean Algebra and graphical techniques are tools to
minimize cost criteria values.
Some important questions:
When do we stop trying to reduce the cost?
Do we know when we have a minimum cost?
Treat optimum or near-optimum cost functions

for two-level (SOP and POS) circuits first.
Introduce a graphical technique using Karnaugh maps
(K-maps, for short)
Karnaugh Maps (K-map)

Chap 3
A K-map is a collection of squares
Each square represents a minterm

The collection of squares is a graphical representation of a
Boolean function
Adjacent squares differ in the value of one variable
Alternative algebraic expressions for the same function are
derived by recognizing patterns of squares
The K-map can be viewed as

A reorganized version of the truth table
A topologically-warped Venn diagram as used to visualize
sets in algebra of sets

Some Uses of K-Maps
Chap 3
Provide a means for:

Finding optimum or near optimum
SOP and POS standard forms, and
two-level AND/OR and OR/AND circuit
implementations
for functions with small numbers of variables

Visualizing concepts related to manipulating
Boolean expressions, and
Demonstrating concepts used by computeraided design programs to simplify large circuits
10
Two Variable Maps

Chap 3
A 2-variable Karnaugh Map:

y=0 y=1
Note that minterm m0 and
minterm m1 are adjacent x = 0 m0 = m1 =
xy
and differ in the value of the
xy
variable y
x = 1 m2 = m3 =
xy xy
Similarly, minterm m0 and
minterm m2 differ in the x variable.
Also, m1 and m3 differ in the x variable as
well.
Finally, m2 and m3 differ in the value of the
variable y
11
K-Map and Truth Tables

Chap 3
The K-Map is just a different form of the truth table.

Example Two variable function:
We choose a,b,c and d from the set {0,1} to implement
a particular function, F(x,y).
Function Table
Input
Function
Values
Value
(x,y)
F(x,y)
00
a
01
b
10
c
11
d
K-Map
y=0
x=0 a
x=1 c
y=1
b
d
12
K-Map Function Representation

Chap 3
Example: F(x,y) = x
F=x y=0 y=1

x=0
x=1
For function F(x,y), the two adjacent cells containing

1s can be combined using the Minimization Theorem:
F( x , y ) x y x y x

13
K-Map Function Representation

Chap 3
Example: G(x,y) = x + y
G = x+y y = 0 y = 1
x=0
x=1
reduce y
reduce x
For G(x,y), two pairs of adjacent cells containing 1s

can be combined using the Minimization Theorem:
G( x , y ) x y x y xy x y x y
Duplicate xy
14
Three Variable Maps

Chap 3
A three-variable K-map:
yz=00
yz=01
yz=11
yz=10
x=0
m0
m1
m3
m2
x=1
m4
m5
m7
m6
Where each minterm corresponds to the product terms:

yz=00
yz=01
yz=11
yz=10
x=0 x y z
xyz
xyz
xyz
xyz
xyz
xyz
x=1
xyz
Note that if the binary value for an index differs in one bit
position, the minterms are adjacent on the K-Map
15
Alternative Map Labeling

Chap 3
Map use largely involves:

Entering values into the map, and
Reading off product terms from the map.
Alternate labelings are useful:

y
x
x

00 01 11 10
0 0
x 1
yz
z
16
Example Functions
Chap 3
By convention, we represent the minterms of F by a "1" in

the map and leave the minterms of F blank
y
Example:
F(x, y, z) m(2,3,4,5)
x 41
Example:
G(a, b, c) m(3,4,6,7)
Learn the locations of the 8
indices based on the variable
order shown (x, most significant
and z, least significant) on the
map boundaries
x 41
1
7
1
2
6
z
17
Combining Squares
Chap 3
By combining squares, we reduce number of literals in

a product term, reducing the literal cost, thereby
reducing the other two cost criteria
On a 3-variable K-Map:
One square represents a minterm with three variables
Two adjacent squares represent a product term with two
variables (apply identities 7,14 one time)
Four adjacent terms represent a product term with
one variable (apply identities 7,14 three times)
Eight adjacent terms is the function of all ones (no
variables) = 1. (apply identities 7,14 seven times)

18
Example: Combining Squares

Chap 3
Example: Let
F m(2,3,6,7)
0
x1
00
01
1
7
1
11
1
6
1
10
Applying the Minimization Theorem three times:
F ( x, y , z ) x y z x y z x y z x y z
yz y z
y
Thus the four terms that form a 2 2 square

correspond to the term "y".
19
Three-Variable Maps
Chap 3
Reduced literal product terms for SOP standard

forms correspond to rectangles on K-maps
containing cell counts that are powers of 2.
Rectangles of 2 cells represent 2 adjacent minterms;
of 4 cells represent 4 minterms that form a
pairwise adjacent ring.
Rectangles can contain non-adjacent cells as
illustrated by the pairwise adjacent ring above.

20
Three-Variable Maps
Chap 3
Topological warps of 3-variable K-maps

that show all adjacencies:
Venn Diagram
0
Cylinder
4 X
6 7 5
Y 3 Z
1
2

21
Three-Variable Maps
Chap 3
Example Shapes of 2-cell Rectangles:

X
YZ
00
01
0
0
XY
4
11
10
2
XZ
YZ
5
7
z
Read off the product terms for the
rectangles shown
22
Three-Variable Maps
Chap 3
Example Shapes of 4-cell Rectangles:

X
YZ
00
01
11
Y
4
Z
5
10
Z
6
z
Read off the product terms for the
rectangles shown
23
Three Variable Maps

Chap 3
K-Maps can be used to simplify Boolean functions by

systematic methods. Terms are selected to cover the
1sin the map.
Example: Simplify F(x, y, z) m(1,2,3,5,7)
xy
1 1 1
x
1 1
z
F(x, y, z)
zxy
24
Three-Variable Map Simplification

Chap 3
Use a K-map to find an optimum SOP

equation for F(X, Y, Z) m(0,1,2,4,6,7)
X
YZ 00
0
01
11
1 XY 1
1
10
Z
1 XY 1
F = XY + XY + Z
25
Four Variable Maps

Chap 3
Map and location of minterms:

YZ
WX
01
00
Variable Order
11
W
10
10
12
13
15
14
11
10
00
01
11
Z
26
Four Variable Terms

Chap 3
Four variable maps can have rectangles
corresponding to:
A single 1 = 4 variables, (i.e. Minterm)
Two 1s = 3 variables,
Four 1s = 2 variables
Eight 1s = 1 variable,
Sixteen 1s = zero variables (i.e.
Constant "1")
27
Four-Variable Maps
Chap 3
Example Shapes of Rectangles:

WX
YZ
01
00
00
01
11
10
4
12
8
11
10
WY
7
XZ
5
XZ
13
15
14
10
11
Z
28
Four-Variable Maps
Chap 3
Example Shapes of Rectangles:

WX
YZ
Y
01
00
00
01
11
W
10
4
Y
12
8
11
10
W
5
X Z
13
15
14
10
11
ZX
X
Z
29
Four-Variable Map Simplification

Chap 3
F(W, X, Y, Z) m(0, 2,4,5,6,7,8,10,13,15)

WX
YZ
01
00
00
01
1 4
12
11
W
10

11
5
1 WX
17
XZ 15
13
1
1
9
11
10
2 XZ
1
1
6
14
10
Z
30
Four-Variable Map Simplification

Chap 3
F(W, X, Y, Z) m(3,4,5,7,9,13,14,15)
WX
YZ
00
01
11
W
10
01
00
11
10
2
3
1
WYZ
6
4
1WXY
15
17
XZ
13
12
15
14
1 WXY1
1
WYZ
9
8
11
10
1

Z
31
Systematic Simplification
Chap 3
Implicant a product term of which if the function has the

Minterm i
value 1 for all minterms.
Product term
Minterm j
A Prime Implicant is a product term obtained by combining
the maximum possible number of adjacent squares in the
map into a rectangle with the number of squares a power of
2 remove any literal not a implicant.
A prime implicant is called an Essential Prime Implicant if it
is the only prime implicant that covers (includes) one or
more minterms.
Prime Implicants and Essential Prime Implicants can be
determined by inspection of a K-Map.
A set of prime implicants "covers all minterms" if, for each
minterm of the function, at least one prime implicant in the
set of prime implicants includes the minterm.
32
Example of Prime Implicants

Chap 3
Find ALL Prime Implicants

CD
C
BD
1
BD
ESSENTIAL Prime Implicants

C
BD
BD
AB
1
B
B
1
D
AD
BC
Minterms covered by single prime implicant
33
Prime Implicant Practice

Chap 3
Find all prime implicants for:
F(A, B, C, D) m(0,2,3,8,9,10,11,12, 13,14,15)

C
BD
1 BC 1
B
1
D
34
Another Example
Chap 3
Find all prime implicants for:
G(A, B, C, D) m(0,2,3,4,7,12,13,14,15)
Hint: There are seven prime implicants!
C
1
1
B

D
35
Five Variable or More K-Maps

Chap 3
For five variable problems, we use two adjacent K-maps.

It becomes harder to visualize adjacent minterms for
selecting PIs. You can extend the problem to six variables
by using four K-Maps.
V=1
V=0
V = 1YY
Y
Y
V=0
XX
W
W
W
Z
Z
ZZ
36
Prime Implicants Selection Rule

Chap 3
Find all prime implicants.

Include all essential prime implicants in the
solution
Select a minimum cost set of non-essential prime
implicants to cover all minterms not yet covered:
Minimize the overlap among prime implicants as much
as possible.
Make sure that each prime implicant selected

includes at least one minterm not included in any
other prime implicant selected avoid
redundancy.
37
Selection Rule Example

Chap 3
Simplify F(A, B, C, D) given on the K-map.

C
1
1
1
A
1
1
1
B
1
Essential
Selected
1
B
A
1
1
D
Minterms covered by essential prime implicants

38
Selection Rule Example

Chap 3
Essential
C
1

39
Chap 3
Concept: mi = Mi
How to derive a POS using SOP derivation:
Derive F = mi+mj +mn F = Mi Mj Mn
C
F = AB + CD + BD
B
F = (A+B)(C+D)(B+D)
D
40
Chap 3
How to derive a simplified SOP and POS

from a POS?
F =(A+C+D)(A+C+D)(A+B+D)(A+B+D)
F = ACD + ACD + ABD + ABD
C
F = AB + CD + AD + BC
F = AC + BD
F = (A+C)(B+D)
D
41
Don't Cares in K-Maps

Chap 3
Sometimes a function table or map contains entries for which it

is known:
the input values for the minterm will never occur, or
The output value for the minterm is not used
In these cases, the output value need not be defined

Incompletely specified functions functions that have unspecified
outputs (it can be 1 or 0)for some input combinations.
Instead, the output value is defined as a don't care

By placing don't cares ( an x entry) in the function table or
map, the cost of the logic circuit may be lowered.
Example 1: A logic function having the binary codes for the
BCD digits as its inputs. Only the codes for 0 through 9 are
used. The six codes, 1010 through 1111 never occur, so the
output values for these codes are x to represent dont cares.
42
Don't Cares in K-Maps

Chap 3
Example 2: A circuit that represents a very common situation that

occurs in computer design has two distinct sets of input variables:
A, B, and C which take on all possible combinations, and
Y which takes on values 0 or 1.
and a single output Z. The circuit that receives the output Z observes it
only for (A,B,C) = (1,1,1) and otherwise ignores it. Thus, Z is
specified only for the combinations (A,B,C,Y) = 1110 and 1111. For
these two combinations, Z = Y. For all of the 14 remaining input
combinations, Z is a dont care.
Ultimately, each x entry may take on either a 0 or 1 value in
resulting solutions
For example, an x may take on value 0 in an SOP solution and
value 1 in a POS solution, or vice-versa.
Any minterm with value x need not be covered by a prime implicant.
Y
A
X
X
X
X
X
X
X
X
X X
X X
B
1 0
X X
C
43
Example: BCD 5 or More

Chap 3
The map below gives a function F1(w,x,y,z) which is

defined as "5 or more" over BCD inputs. With the
don't cares used for the 6 non-BCD combinations:
F1 (w,x,y,z) = w + x z + x y G = 7
y
00 01
04 15
w
X12 X13
18 19
This is much lower in cost than F2 where the

03 02
don't cares were treated as "0s."
1 7 1 6 F (w, x, y, z) w x z w x y w x y G = 12
x 2
X15 X14
For this particular function, cost G for the
POS solution for F1(w,x,y,z) is not changed
X11 X10
by using the don't cares.
z
44
Dont Care Another Example

Chap 3
B
A
F = CD + AD
F = CD + AB
F = D + AC
F = D ( A+C)
45
Selection Rule Example with Don't Cares

Chap 3
Simplify F(A, B, C, D) given on the K-map.

C
1
A
Essential
Selected
B
x
1
B
Minterms covered by essential prime implicants

46
Product of Sums Example

Chap 3
Find the optimum POS solution:
F(A, B, C, D) m(3,9,11,12,13,14,15)
d (1,4,6)
Hint: Use F and complement it to get the result.
C
F = AB + BD
F = (A + B) (B + D)
D
47
Universal
Chap 3
A set of gates is said to be universal if any

Boolean function can be composed of the
elements of this set.
{AND, OR, NOT} a universal set.
Universal gate - a gate type that can

implement any Boolean function.

48
Other Gate Types

Chap 3
Why?
Implementation feasibility and low cost
Power in implementing Boolean functions
Convenient conceptual representation
Gate classifications
Primitive gate - a gate that can be described using a
single primitive operation type (AND or OR) plus an
optional inversion(s).
Complex gate - a gate that requires more than one
primitive operation type for its description
Primitive gates will be covered first

49
Buffer
Chap 3
A buffer is a gate with the function F = X:

X
In terms of Boolean function, a buffer is the

same as a connection!
So why use it?
A buffer is an electronic amplifier used to
improve circuit voltage levels and increase the
speed of circuit operation.
50
NAND Gate
Chap 3
The basic NAND gate has the following symbol,

illustrated for three inputs:
AND-Invert (NAND)
X
Y
Z
F( X , Y, Z ) X Y Z
NAND represents NOT AND, i. e., the AND

function with a NOT applied. The symbol shown
is an AND-Invert. The small circle (bubble)
represents the invert function.
51
NAND Gates (continued)

Chap 3
Applying DeMorgan's Law gives Invert-OR (NAND)

X
Y
Z
F( X , Y , Z ) X Y Z
This NAND symbol is called Invert-OR, since inputs are

inverted and then ORed together.
AND-Invert and Invert-OR both represent the NAND
gate. Having both makes visualization of circuit function
easier.
A NAND gate with one input degenerates to an inverter.
52
NAND Gates (continued)

Chap 3
The NAND gate is the natural implementation for the

simplest and fastest electronic circuits
The NAND gate is a universal gate as shown in the
following.
NAND usually does not have a operation symbol defined
since
the NAND operation is not associative, and
we have difficulty dealing with non-associative mathematics!
x
y
xy
x
y
xy=x+y

53
Two-level NAND Gates

Chap 3
A function of sum-of-products form is easy

to convert to NAND gates.
F = AB + CD F = AB + CD F = AB CD
A
B
F
C
D

54
Two-level NAND Gates cont.

Chap 3
Converting procedures
Simplify the function and express it in sum-ofproducts form,
For each line connecting to the 2-level OR gate,
insert two inverters the its two ends,
Transform the invert-OR gate to NAND gate.
F = XY + XY + Z
1

F = XY + XY + Z
F = XY XY Z
55
Multilevel NAND Gates

Chap 3
The procedures to convert to multilevel

NAND gates circuits:
Convert all AND gates to NAND gates with
AND-NOT graphic symbols,
Convert all OR gates to NAND gates with
NOT-OR graphic symbols,
Complement the input literal if the signal has
single bubble, and insert a NOT gate for the
output signal with single bubble.
56
Multilevel NAND Gates Cont.

Chap 3
C
D
B
B
A
B
C
A
B
A
B
C
D
D

57
NOR Gate
Chap 3
The basic NOR gate has the following

symbol, illustrated for three inputs:
OR-Invert (NOR)
X
Y
Z
F(X, Y, Z) X +Y Z
NOR represents NOT - OR, i. e., the OR

function with a NOT applied. The symbol
shown is an OR-Invert. The small circle
(bubble) represents the invert function.
58
NOR Gate (continued)

Chap 3
Applying DeMorgan's Law gives Invert-AND

(NOR)
X
Y
Z
This NOR symbol is called Invert-AND, since

inputs are inverted and then ANDed together.
OR-Invert and Invert-AND both represent the
NOR gate. Having both makes visualization of
circuit function easier.
A NOR gate with one input degenerates to an
inverter.
59

Chap 3
The NOR gate is another natural implementation for

the simplest and fastest electronic circuits
The NOR gate is a universal gate
NOR usually does not have a defined operation
symbol since
the NOR operation is not associative, and
we have difficulty dealing with non-associative
mathematics!
x
y
x+y
x
y
x+y=xy

60

Chap 3
A
B
A
A
B
C
D

61
Exclusive OR/ Exclusive NOR

Chap 3
The eXclusive OR (XOR) function is an important

Boolean function used extensively in logic circuits.
The XOR function may be;
implemented directly as an electronic circuit (truly a gate) or
implemented by interconnecting other gate types (used as a
convenient representation)
The eXclusive NOR function is the complement of the

XOR function
By our definition, XOR and XNOR gates are complex
gates.
62
Exclusive OR/ Exclusive NOR

Chap 3
Uses for the XOR and XNORs gate include:

Adders/subtractors/multipliers
Counters/incrementers/decrementers
Parity generators/checkers
Definitions
The XOR function is: X Y X Y X Y
The eXclusive NOR (XNOR) function, otherwise
known as equivalence is: X Y X Y X Y
Strictly speaking, XOR and XNOR gates do no

exist for more than two inputs. Instead, they are
replaced by odd and even functions.
63
Truth Tables for XOR/XNOR

Chap 3
Operator Rules: XOR
XNOR
Y XY
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
Y (XY)
or X Y
0
1
1
0
0
0
1
1
The XOR function means:

X OR Y, but NOT BOTH
Why is the XNOR function also known as the
equivalence function, denoted by the operator ?
64
XOR/XNOR (Continued)
Chap 3
The XOR function can be extended to 3 or more variables.

For more than 2 variables, it is called an odd function or
modulo 2 sum (Mod 2 sum), not an XOR:
X Y Z XYZ XYZ XYZ XYZ

The complement of the odd function is the even function.
The XOR identities:
X0 X
X 1 X
XX 0
XX 1
XY YX
( X Y) Z X ( Y Z ) X Y Z

65
Symbols For XOR and XNOR

Chap 3
XOR symbol:
XNOR symbol:
Symbols exist only for two inputs

66
XOR Implementations
Chap 3
The simple SOP implementation uses the

following structure: X
xy = xy + xx
X Y
= x(x+y)
Y
= xxy
A NAND only implementation is:
X
X Y
Y
67
Odd and Even Functions

Chap 3
The odd and even functions on a K-map form

checkerboard patterns.
The 1s of an odd function correspond to minterms
having an index with an odd number of 1s.
The 1s of an even function correspond to minterms
having an index with an even number of 1s.
Implementation of odd and even functions for greater
than 4 variables as a two-level circuit is difficult, so we
use trees made up of :
E O E O
00
01
11
1O
00
2-input XOR or XNORs

3- or 4-input odd or even functions
01
11
10
O E O E
E O E O
O E O E
68
Example: Odd Function Implementation

Chap 3
Design a 3-input odd function F = X + Y + Z

with 2-input XOR gates
Factoring, F = (X + Y) + Z W
The circuit:
X
Y
Z
F
F
W
69
Example: Even Function Implementation

Chap 3
Design a 4-input even function F = W + X + Y + Z

with 2-input XOR and XNOR gates
Factoring, F = (W + X) + (Y + Z)
The circuit:
W
X
F
Y
Z
70
Parity Generators and Checkers

Chap 3
In Chapter 1, a parity bit added to n-bit code to produce an n

+ 1 bit code:
Add odd parity bit to generate code words with even parity
Add even parity bit to generate code words with odd parity
Use odd parity circuit to check code words with even parity
Use even parity circuit to check code words with odd parity
0
Example: n = 3. Generate even
X
parity code words of length 4 with Y 0
odd parity generator:
1
Z
Check even parity code words of X 0
length 4 with odd parity checker: Y 0
Operation: (X,Y,Z) = (0,0,1) gives
1
Z
(X,Y,Z,P) = (0,0,1,1) and E = 0.
1
If Y changes from 0 to 1 between P
generator and checker, then E = 1 indicates an error.
71
Terms of Use
Chap 3
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Lcdf3 Chap 03

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Digital Design with an Introduction to the

The Map Method

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Digital Design with Verilog Practice

Goal: To obtain the simplest

Logic & Computer Design Fundamentals

boris Li, 2015/3/24

Literal a variable or its complement

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Logic & Computer Design Fundamentals

Gate Input Cost

Gate input costs - the number of inputs to the gates in the

Example: which solution is best ?

Logic & Computer Design Fundamentals

Cost Criteria (continued)

L (literal count) counts the AND inputs and the single

Logic & Computer Design Fundamentals

Cost Criteria (continued)

Same function and same

Logic & Computer Design Fundamentals

Boolean Function Optimization

Minimizing the gate input (or literal) cost of a (a set

Treat optimum or near-optimum cost functions

Logic & Computer Design Fundamentals

Karnaugh Maps (K-map)

A K-map is a collection of squares

Each square represents a minterm

The K-map can be viewed as

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Logic & Computer Design Fundamentals

Some Uses of K-Maps

Provide a means for:

for functions with small numbers of variables

Logic & Computer Design Fundamentals

Two Variable Maps

A 2-variable Karnaugh Map:

Logic & Computer Design Fundamentals

K-Map and Truth Tables

The K-Map is just a different form of the truth table.

Logic & Computer Design Fundamentals

K-Map Function Representation

F=x y=0 y=1

For function F(x,y), the two adjacent cells containing

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Logic & Computer Design Fundamentals

K-Map Function Representation

For G(x,y), two pairs of adjacent cells containing 1s

Logic & Computer Design Fundamentals

Three Variable Maps

Where each minterm corresponds to the product terms:

Logic & Computer Design Fundamentals

Alternative Map Labeling

Map use largely involves:

Alternate labelings are useful:

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By convention, we represent the minterms of F by a "1" in

Logic & Computer Design Fundamentals

By combining squares, we reduce number of literals in

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Logic & Computer Design Fundamentals

Example: Combining Squares

Applying the Minimization Theorem three times:

Thus the four terms that form a 2 2 square