####################

#
SETUP
#
####################
#1.
set sh_enable_page_mode true
#2.
set search_path {. ./../designs}
set link_path {* ./../libs/tut_lib.db}
#3.
read_verilog ex1_design.v
#4.
link_design
####################
# CONSTRAIN
#
####################
#1. check the design's timing
check_timing
#2. 50% duty cycle, 150Mhz get
create_clock -period 6.666 -name CLK [get_ports clk1]
#3.
set_clock_latency 2.0 CLK
#4.
set_input_delay 2.0 -clock CLK [get_ports in*]
set_output_delay 1.0 -clock CLK [all_outputs]
#5.
report_clock -skew
report_port -input_delay
report_port -output_delay
check_timing
####################
# ENV ATTRIBUTES #
####################
#1.
set_driving_cell -lib_cell IV [all_inputs]
#2.
set_load -pin_load 1 [all_outputs]
#3.
set_wire_load_model -name 10Kgates
#4.
set_operating_conditions -library tut_lib -analysis_type single TYPICAL
####################
# REPORT ON DESIGN #
####################
#1.
report_design
#2.

report_hierarchy
#3.
report_net
#4.
report_cell
#5.
report_reference
#6.
report_clock
####################
# REPORT TIMING #
####################
#1.
report_timing
#2.
report_timing -nets -transition_time -capacitance
#3.
report_timing -nworst 10 -path_type summary
#4.
report_timing -nworst 10 -path_type summary -to [all_outputs]
#5.
report_timing -nworst 10 -path_type summary -from g*/CP -to g*/D