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Test Bench In Verilog

Template
module t_DUTB_name ();
reg;
wire.;
parameter

time_out =

// substitute the name of the UUT


// Declaration of the register variables for primary
//inputs of the UUT
// Declaration of the register variables for primary
//outputs of the UUT
// provide a value

UUT_name M1_instance_name (UUT ports go here);


initial $monitor ();
initial #time_out $stop;
initial
begin

//Specification of signals to be monitored and


//displayed as text
// Stopwatch to assure termination of simulation
// Develop one or more behaviors for patter
//generation and/or error detection
// Behavioral statements generating waveforms
// to the input ports, and comments documenting
// the test. Use the full repertoire of behavioral
// constructs for loops and conditionals.

end
endmodule

Test Bench without Clock


Majority Vote Module
module maj_vote (f, a, b, c);
input a, b, c;
output f;
assign f = ((a & b)|(a & c)|(b & c));
endmodule
TestBench of Majority Module
module t_maj_vote ();
wire f;
reg a, b, c;
maj_vote M1 (f, a, b, c); // unit under test (UUT)
initial begin
// time out
#100 $finish;
end

initial begin
#10 a = 0; b=0; c=0;
#10 a = 0; b=0; c=1;
#10 a = 0; b=1; c=0;
#10 a = 0; b=1; c=1;
#10 a = 1; b=0; c=0;
#10 a = 1; b=0; c=1;
#10 a = 1; b=1; c=0;
#10 a = 1; b=1; c=1;
#10 a = 1; b=0; c=0;
end
endmodule

Test Bench With Clock generation


Counter Module
module counter (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
always @ (posedge clk)
if (reset == 1'b1) begin
count <= 0;
end else if ( enable == 1'b1) begin
count <= count + 1;
end
endmodule

Counter Test Module


module counter_tb;
reg clk, reset, enable;
wire [3:0] count;
counter U0 ( .clk
.count (count) );

(clk), .reset (reset), .enable (enable),

initial begin
clk = 0;
reset = 1;
enable = 0;
end
always // generates the clock
#5 clk = !clk;
initial begin //optional line
$dumpfile ("counter.vcd");
$dumpvars;
end
initial begin
$display("\t\ttime,\tclk,\treset,\tenable,\tcount");
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count);
end
initial begin
#200 $finish; end
initial begin
//Rest of testbench code after this line
#10 reset = 0; enable = 1;

end
endmodule
$dumpfile is used for specifying the file that simulator will use to store the
waveform, that can be used later to view using waveform viewer. (Please refer to
tools section for freeware version of viewers.) $dumpvars basically instructs the
Verilog compiler to start dumping all the signals to "counter.vcd".
$display is used for printing text or variables to stdout (screen), \t is for inserting
tab. Syntax is same as printf. Second line $monitor is bit different, $monitor keeps
track of changes to the variables that are in the list (clk, reset, enable, count).
When ever anyone of them changes, it prints their value, in the respective radix
specified.
$finish is used for terminating simulation after #100 time units (note, all the initial,
always blocks start execution at time 0)

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