“Seeking a tech lead/managerial position to contribute

my expertise in VLSI design backed with a valuable

hand-on experience” ARVIND SHRIVASTAVA
arvindshr@gmail.com | +91-909-834-5419 | +91-751-2467952 Suri
Nagar, S. L. P. College Road, Morar, Gwalior – 474006, M.P., India

TECHNICAL SKILLS EDA tools: Design Compiler, RTL Compiler, Formality, PrimeTime, DFT Compiler,
VCS, Prime Power, Physical Compiler, Conformal, Debussy, Simvision, Specman,
Pinnacle, starRC, Spyglass
HDL and Scripting Languages: Verilog/VHDL, Perl, C-Shell, “e”
Revision control system: CVS, SVN, Synchronocity
Protocol: PCI, AMBA
Interface Implementation : DDRI, DDRII, MMC, PCI
Other: Project tracking/planning, Design review, Vendor/Customer interface,
mentoring/training junior engineers

LAST JOB PROFILE Project Lead for 65nm ASIC at STMicroelectronics, Phoenix, USA

EXPERIENCE 12+ years | With ST Microelectronics since 1996

Aug’ 08 - Feb’ 09 Principal Engineer | ASIC Business Gr., ST Microelectronics, Phoenix, AZ

Project: ASIC networking SOC in 65nm
Responsibilities: Developing synthesis methodology and margins for customer
Handoff checks on Gate level netlist from customer,
Budgeting of blocks level constraints, used by block engineers for implementation
Timing constraints for Synthesis, STA and P&R,
Chip level clock and reset structure document, CTS spec to run clock tree synthesis,
Timing closure and CTS methodology.
Guiding BE team during Floorplan, pad placement,PreCTS optimization, CTS ,postCTS
opt and SI fixing.

2005- July’ 08 Senior Staff Engineer | Data Storage Div., ST Microelectronics, Phoenix, AZ
Project/s: Disc controller for mobile application, desktop application and enterprise
applications, 90 nanometer
Responsibilities: Silicon debug for DDR interface,
RTL for clock generation, debug modes of chip and IO pads,
Synthesis at chip level using dc_shell (xg-mode) and multi Vt std. cells, using options to
reduce leakage and dynamic power,
Writing chip level constraints for Synthesis, Static Timing Analysis and Layout. Chip has
multiple clock domains and timing critical interfaces like DDRI, DDRII, SDRAM and
Analog IP , MiPhy, Read write channel,
Generating clock/reset structure document for implementation, guiding layout engineers
on clock implementation and physical Synthesis, Power analysis for chip
PreCTS Timing optimization using Physical Compiler
Clock tree for multiple modes of SOC using pinnacle, including DDRII interface.
Static Timing Analysis for chip across multiple corners/modes, On Chip Variation
Interacting with different groups e.g. library, DFT team and external customer,
ECO (Functional and timing) Implementation at gate level netlist,
Work with physical design team for IO pad placement, and
Other responsibilities as project lead include review of design specs, verification plan.
Verification of AMBA bus protocol using specman environment.

Résumé | Arvind Shrivastava | Page | 1

2004- 2005 Staff Engineer | Region America Design Centre, ST Microelectronics, Phoenix, AZ
Projects: Networking ASIC for Cisco
Chip specs:100 sq. mm in cmos 90 nanometer technology, Gate count of more than 20
million, Many instantiation of serdes, DDR interface, PCI interface, Gate level netlist
handoff from customer, and Hierarchical Implementation of chip, because of size.
Responsibilities: Writing Static Timing Analysis constraints for chip level, interface
includes DDR, PCI and Serdes,
Also doing Bist, test shift, test capture, transition delay fault constraints,
Static Timing Analysis across multiple corners using On chip variation and cross talk
noise violations,
Helping BE with clock implementation, achieving good clock skew for critical clocks like
DDR.

2002- 2004 Sr. Design Engineer | Reg. America Design Centre, ST Microelectronics, Phoenix, AZ
Projects: Network Processor Search Engine, cmos 1.3um technology
Responsibilities: Development of verification environment for Table search unit using “e”
language, using System C models as reference,
Verification of Table search engine using specman, achieving good functional coverage,
Timing constraints and STA at chip level. Extraction using starRC.

2000- 2002 Sr. Design Engineer | Central Peripheral Gr., ST Microelectronics, Carrollton, TX
Project: Voice over Internet Protocol chip
Responsibilities: DSP in VoIP chip was an IP from external source,
Integrated it for top level, did RTL for interrupt handling,
Verification of PCI interface using HDL based verification environment,
Working with silicon validation team for silicon bring up of VoIP chip.

Project: ASIC for EchoStar in 1.3um

Responsibilities: Synthesis, gate level simulation and Static Timing Analysis for Chip
level and block.

1999- 2000 Sr. Design Engineer | Central Peripheral Gr., ST Microelectronics, Grenoble, France
Projects: DVD player SOC
Responsibilities: Conversion of schematic based design to RTL and Verification of Digital
Encoder/Decoder.

1998- 1999 Sr. Design Engineer | Central Peripheral Gr., ST Microelectronics, Noida, India
Projects: ASIC library development
Responsibilities: Group Leader for Frontend library development,
Managing delivery of FE views to external/internal customers and a team of 6 engineers.

1996- 1998 Design Engineer | Central Peripheral Gr., ST Microelectronics, Noida, India
Projects: ASIC library development
Responsibilities: Development of frontend views for cmos libraries, for different EDA
platforms verilog/VHDL/VITAL /Synopsys/Mentor.

EDUCATION Institute of Technology, Banaras Hindu University (IT BHU), Varanasi

M. Tech. in Microelectronics, Mar 1996, CGPA 10
Madhav Institute of Technology and Science (MITS), Gwalior
B. E. in Electronics, June 1993, 78 %

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