Nanocrystalline silicon electron emitter with a high efficiency enhanced by a

planarization technique
K. Nishiguchi, X. Zhao, and S. Oda
Citation: Journal of Applied Physics 92, 2748 (2002); doi: 10.1063/1.1497703
View online: http://dx.doi.org/10.1063/1.1497703
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JOURNAL OF APPLIED PHYSICS

VOLUME 92, NUMBER 5

1 SEPTEMBER 2002

Nanocrystalline silicon electron emitter with a high efficiency enhanced by

a planarization technique
K. Nishiguchi
Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama,
Meguro-ku, Tokyo 152-8552, Japan

X. Zhao
Department of Physics, Science University of Tokyo,1-3 Kagurazaka, Shinjuku-ku, Tokyo 162-8601, Japan

S. Odaa)
Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama,
Meguro-ku, Tokyo 152-8552, Japan

Received 17 April 2002; accepted for publication 10 June 2002

A cold electron emitter has been fabricated based on nanocrystalline silicon nc-Si quantum dots
formed in the gas phase by very-high-frequency plasma decomposition of SiH4 . A small size of less
than 10 nm and the spherical shape of the nc-Si dots facilitated the generation of hot electrons.
Electrons with kinetic energies higher than the work function of the top electrode were extracted
into vacuum through the electrode. A planarization process of the nc-Si layer by annealing enhanced
the electron emission efficiency to 5%. Efficiency was optimized by varying the thicknesses of the
nc-Si layer, the SiO2 layer, and the top electrode film. 2002 American Institute of Physics.
DOI: 10.1063/1.1497703

I. INTRODUCTION

Quantum dots with a size of a few nanometers are attractive for various advanced devices, i.e., single electron
transport devices,1,2 optical devices,3 and cellular automata
devices.4 Although there have been several attempts to prepare monodispersed silicon dots, it is still a significant challenge to prepare dots with a size non uniformity of less than
10% and with precise position control.5 A poor control in the
position and the size of dots affects the transport of electrons
and decreases device reproducibility.6 In this article, we focus on nc-Si dots with a small spherical shape for a hot
electron emission device which behaves like thin film electron emitter devices.7,8 The device structure consists of dots
buried in oxide and sandwiched between thin electrode films.
It is expected that the enhancement of the electric field
around the dots due to the small radius of curvature of the
dots should enable a higher yield of hot electrons at a fixed
applied voltage. In this device, the problem of size and position distribution of nc-Si dots will not significantly affect
the device performance because of macroscopic averaging.
Cold electron emitting devices have been studied intensively for their use in flat panel type displays. Spindt-type
electron emitters9,10 based on field emission from Si and
metal cones have been studied. A high brightness and the
ability to operate at high speed were demonstrated. However,
these devices have a complicated structure and they require a
high vacuum and a high supply voltage. A large dispersion of
angles of emitted electrons results in a poor resolution. Recent reports of field emission devices based on carbon nanotubes addressed some of these problems.11,12 However, lifea

Electronic mail: soda@pe.titech.ac.jp

time is a serious issue for these devices. A planar type

electron emitter with narrow beam dispersion formed by porous Si PS has also been proposed to overcome the problems already mentioned.13,14 It has been suggested that the
dominant mechanism is the ballistic transport of hot electrons through the PS layer. An external quantum efficiency,
defined by the ratio of the emission current to the total current, of about 1% was achieved. This emission device does
not require the fine control of the position and the size of Si
nanostructures in the PS layer because the transport of a
large number of electrons is involved. One of the most important mechanisms in these devices is the tunneling process
of electrons through a SiO2 film. Thermal SiO2 around nc-Si
dots is expected to be more stable than SiO2 formed by an
anodization process for the PS formation. Thus, an electron
emitter using nc-Si dots is expected to deliver a higher performance.
In this article, we describe fabrication and characteristics
of electron emitters using nc-Si dots. In Sec. II, we explain
the fabrication processes. In Sec. III, electron emission properties with and without the planarization technique are presented. We investigate the dependence of electron emission
property on the size of nc-Si dots and the thickness of the
SiO2 layer. Then, the mechanism of the electron emission is
discussed. The effect of the top electrode film is investigated.
We evaluate the inherent efficiency of the nc-Si layer without
the loss in the electrode film. Finally, concluding remarks are
given in Sec. IV.
II. SAMPLE FABRICATION

An n -Si 0.01 cm wafer was used as the substrate

and the electron source. The nc-Si dots were deposited onto
the substrate at room temperature by plasma decomposition
of SiH4 . Figure 1 shows the fabrication system of nc-Si dots,

0021-8979/2002/92(5)/2748/10/$19.00
2748
2002 American Institute of Physics
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FIG. 1. Schematic diagram of the nc-Si deposition apparatus used in this

work.

which includes a plasma cell, which is connected with the

main ultrahigh vacuum UHV chamber through a 6-mmdiameter orifice in a stainless steel plate. Ar and SiH4 gases,
whose flow rates were 10 and 1 sccm, respectively, were
excited by a 144 MHz plasma with a power of 3 W. nc-Si
dots with sizes of 105 nm were formed in the gas phase by
a coalescence of SiHx (x:1 4) radicals and were extracted
out of the plasma cell through the orifice toward the Si wafer.
For the fine control of the size, pulsed SiH4 gas was supplied
in Ar gas as shown in Fig. 2a.15 This method enabled the
control of the growth time of nc-Si dots. The flow rate of
SiH4 was varied from 1 to 4 sccm, with a plasma power of 3
W, and the flow rate of Ar was 30 sccm. The duration of each
SiH4 supply pulse was 0.1 s and the purging time between
pulses was 1 s. Figure 2b shows the size distribution of
nc-Si dots for various flow rates of SiH4 . A high-resolution
transmission electron microscopy TEM image of nc-Si dot
is shown in Fig. 2c. The crystalline dot was covered by
native oxide. The total thickness of the nc-Si layer was varied from 0.1 to 1.5 m.
Subsequently, the samples were oxidized at 700 C for 1
h and at 1000 C for 5 min. The low temperature oxidation
was performed for covering the dots with SiO2 , and the high
temperature oxidation was for forming a thin oxide layer
near the top surface. Figure 3 shows cross sectional scanning
electron microscopy SEM images of the oxidized sample.
Near the interface between the Si substrate and the nc-Si
layer, many voids were observed between spherically shaped
nc-Si dots because nc-Si dots grown in the gas phase had
been deposited randomly onto the Si substrate. There was no
chargeup during the SEM observation because only very thin
SiO2 was formed around each dot. On the other hand, near
the top surface, the porosity is small because the molecular
volume of SiO2 is larger than the atomic volume of Si, and
the observed image was dark because of chargeup effect.
This image showed that a thick SiO2 layer was formed near
the top surface.

FIG. 2. a Schematic diagram of gas flow sequence. b size distribution of

nc-Si when the flow rate of pulsed-SiH4 is A 1 sccm, B 2 sccm, C 3
sccm and D 4 sccm. Plasma power is 3 W, Ar flow rate 30 sccm. c a high
resolution TEM image of a nc-Si dot.

Some samples were planarized by a reflow annealing

process. The high density of voids between nc-Si dots, as
shown in Fig. 3, is expected to disturb the electric field applied to the nc-Si layer. Thus, we intend to melt SiO2 around
dots and fill voids with migrating SiO2 . The melting points
of bulk SiO2 and Si are 1700 and 1400 C, respectively, and

FIG. 3. Cross sectional SEM images of an oxidized sample.

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FIG. 5. Cross sectional SEM images of a sample with a 150-nm-thick nc-Si

layer a before and b after a planarization process with P2 O5 at 1100 C
for 10 min sample D.

FIG. 4. Cross sectional SEM images of a thin layer of nc-Si dots a before
and b after a planarization step. Temperature and time are 1200 C and 10
min, respectively, c SEM image of a sample with a 100-nm-thick nc-Si
layer after a planarization step at 1200 C for 10 min. The layer between the
dashed lines is expected to be SiO2 .

their viscosities near the melting points are reduced. However, a very small particle with a high surface energy has a
further lower melting point because atoms near the surface
oscillate with large amplitude.16,17 Moreover, the surface area
is large thus, particles start to migrate at a lower temperature
than the melting point as the surface area becomes small, and
the layer of particles becomes flat.18,19 Kawachi et al. formed
an optical wave guide from glass particles by an annealing
process at 1250 C.20 These two mechanisms enable SiO2 to
migrate into voids between dots at a lower temperature than
the melting point. After the deposition of a few layers of Si
dots, the sample is oxidized at 800 C for 5 min, and then
annealed at 1200 C for 10 min under N2 flow. The nc-Si dot
layer became flat as SiO2 around dots migrated into voids
between dots as shown in Figs. 4a and 4b. However,
thicker nc-Si layers could not be adapted to this planarization
technique as shown in Fig. 4c. The oxidation was performed at 850 C for 40 min, followed by an anneal at
1200 C for 4 h. Near the interface between the Si substrate
and the nc-Si layer, a flat layer of SiO2 resulting from the
reflow process was formed. Although this oxidation condition should have oxidized nc-Si dots completely, the spherical shape of nc-Si dots was observed. These phenomena
could be explained as follows; the oxidation proceeded preferentially near the top surface, compared to the deep nc-Si
layer, as shown in Fig. 3. As the oxidation proceeded and the
volume of SiO2 increased near the surface, the supply of O2
gas into the depth of nc-Si layer was cut off because voids
between dots near the surface were sealed with SiO2 . Thus,
the deep nc-Si layers were not oxidized completely, and
nc-Si dots, which were not completely oxidized, remained
after the annealing process.
For the complete planarization for the thicker nc-Si
layer, we add two optional techniques. One is an impurity
doping into SiO2 . Impurities in SiO2 weaken bonds between

Si and O, thus, reducing the oxide melting point. Based on

this effect, phosphosilicate glass PSG is used routinely for
the planarization of integrated circuits.21,22 With the addition
of impurities, however, the oxidation rate is enhanced due to
a lower binding energy between Si and O. However, since
nc-Si dots are intrinsic, there is no impurity in SiO2 . For
doping impurities in the nc-Si layer, ion implantation and
thermal diffusion can be applied. While ion implantation can
realize a fine control of the impurity profile, the damage
caused by the implantation is undesirable. Hence, the thermal diffusion method was chosen. After the formation of a
layer of nc-Si dots with a thickness of 150 nm, a thermal
impurity diffusion was performed by a pellet of P2 O5 under
N2 at a temperature of 1100 C for 10 min. The oxidation is
performed with little oxygen source due to the oxidation rate
enhanced by the impurity and a larger surface-to-volume ratio than a bulk wafer. In this condition doping concentration
was 1017 1018/cm3 , which was measured using a highly resistive Si wafer. This method leads to an easy planarization
as shown in Fig. 5. The planarization process reduced the
thickness of the nc-Si layer from 150 to 60 nm due to a
collapse of the high porosity in the as-deposited nc-Si layers.
A dark part in the circle labeled A indicates a void where it
was not completely filled with melted SiO2 . A bright part in
the circle labeled B indicates a spherically shaped nc-Si dot.
The other method used for the complete planarization
was repeated oxidation and annealing processes. After a
short oxidation, the annealing process for reflowing SiO2 reduced the thickness of SiO2 near the top surface and exposed
nc-Si dots, which was not oxidized, as shown in Fig. 4c.
Then, the next oxidation was performed, followed by annealing. A repeat of these processes enabled the oxidation and the
planarization of thicker nc-Si layers. Figure 6 shows cross

FIG. 6. Cross sectional SEM images of samples with a 120-nm-thick nc-Si

layer after sequential oxidation and annealing processes. Oxidation conditions were at 850 C a Sample E for 1 min4 min5 min and b Sample
F for 1 min4 min5 min10 min. After each oxidation step, there was an
anneal at 1200 C for 1 h.
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FIG. 7. Diagram for the measurement of the electron emitter in the present
work.

sectional SEM images of samples, with an initial thickness

of 120 nm, after sequential oxidation/annealing process. Oxidation conditions of the samples of Fig. 6 were 850 C a for
1 min4 min5 min and b 1 min4 min5 min10 min.
After each oxidation step, an anneal at 1200 C for 1 h was
performed. Both of these samples were planarized.
Finally, an Al ohmic electrode on the backside of Si and
a 10-nm-thick Au film on the front surface were formed by
electron-beam evaporation. Figure 7 shows the device structure and the measurement system. Sample labels and preparation condition are listed in Table I.
III. ELECTRON EMISSION CHARACTERISTICS AND
DISCUSSION

Measurements were performed in vacuum with a base

pressure of 106 Torr and the Au electrode grounded. A
metal collector plate was positioned in front of the sample at
a distance of 5 mm and was applied a constant positive voltage of 100 V. A negative extraction voltage was applied to
the Al film. The electron emission efficiency is defined as the
ratio of the collected emission current to the total current.
A. Emission characteristics from devices without the
planarization technique

Figure 8 shows diode-current characteristics and electron

emission characteristics for nc-Si layers with the thicknesses
of 1 and 1.5 m without the planarization technique. We
refer to them as sample A and sample B, respectively. While
the negative extraction voltage was applied to the Si substrate, a simple diode current was observed. When a negative

FIG. 8. Diode and emission current characteristics and the emission efficiency as a function of the applied voltage. The thickness of the nc-Si layer
was a 1 m sample A and b 1.5 m sample B.

voltage of over 5 V, which may be related to the work function of Au, was applied electrons were extracted from the
sample and reached the collector. Around a voltage of 36
V, electron emission current densities in sample A and
sample B reached 4 and 0.6 A/cm2 , respectively. Electron
emission efficiencies reached 0.2% and 0.6%.

TABLE I. Sample preparation conditions.

Sample
A
B
C
D
E
F
G
H

Thickness

Dot size
nm

Planarization

Efficiency
%

1 m
1.5 m
0.6 m
60 nm
60 nm
60 nm
60 nm
60 nm

105 nm
105 nm
105 nm
105 nm
82 nm
82 nm
62 nm
105 nm

No
No
No
P2 O5 10 min
Sequential 10 min
Sequential 20 min
Sequential 10 min
Sequential 10 min

0.2
0.6
0.8
4.5
0.54
2.86
0.99
0.27

FIG. 9. FowlerNordheim plot extracted from the emission characteristics.

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FIG. 11. Diode and emission current characteristics as a function of the

applied voltage. Also included is the emission efficiency from the device
sample D planarized by a phosphorus doping process. The thickness of the
nc-Si layer was reduced from 150 to 60 nm by the planarization process.

FIG. 10. AFM surface images of samples a before and b after the improvement of the surface roughness. c Diode and emission current characteristics as a function of the applied voltage. Also included is the emission
efficiency from sample C with a smooth surface. The thickness of the nc-Si
layer was 0.6 m.

From the experimental results, it is possible to speculate

on the mechanism for electron emission. A possible process
for nc-Si emitter is as follows. First electrons are injected
from the silicon wafer into nc-Si dots without scattering due
to the small size of the dots. The electric field is applied
mainly within SiO2 regions covering the dots. Thus the electrons from nc-Si are accelerated into SiO2 by the high electric field, allowing ballistic transport through subsequent
nc-Si layers. These processes allow electrons to reach the Au
electrode with high energy. Electrons with energies larger
than the work function of Au can ballistically transport
through the Au electrode and reach the collector. Figure 9
shows FowlerNordheim FN plots of emission current
from the two samples shown in Fig. 8 and another thinner
sample. It is evident that the FN plots for these samples
follow the linear behavior. These measurements suggest that
a field-induced tunnel process occurs during the electron
emission.
For higher efficiency and for a more detailed investigation, emitters with thinner nc-Si layers and with smooth surfaces were prepared because the surface roughness is ex-

pected to lead to a large variation of electric field in the nc-Si

layer. The surface roughness rms of samples A and B are
larger than 100 nm as shown in Fig. 10a. Next, we improved the surface roughness rms to 30 nm by optimizing
the deposition of nc-Si dots as shown in Fig. 10b. The
thickness of nc-Si layer was 0.6 m. We refer to this sample
as sample C, whose current and emission characteristics are
shown in Fig. 10c. The emission efficiency was improved
to 0.8%. In this case, the film thickness is thinner than previous samples, but the observed current is smaller. It is expected that in the sample with a rough surface, electrons flow
selectively through thin areas. Thus, samples with a rough
surface had larger average currents. In the sample with
smoother surface, the diode current and the electron emission
increase with the bias voltage without saturation, unlike
samples A and B. The FN plot from sample C followed a
good linear behavior with a small dispersion, compared to
samples A and B. In the samples with rough surfaces, electric
field may be applied to voids between dots as shown in Fig.
3. It is expected that an improvement in the surface roughness may allow the electric field to be applied more uniformly to the sample. The characteristic without saturation
may lead to high emission efficiency.
B. Emission characteristics from devices planarized
by the phosphorus diffusion

As mentioned above, the uniform electric field in nc-Si

layers is required. Next, we describe the characteristics from
samples planarized by the phosphorus diffusion, as shown in
Fig. 11. This sample is referred to as sample D. The electron
emission current and efficiency were improved to 10 A/
cm2 and 4.5%, respectively. These improvements were likely
obtained by the uniform electric field in the nc-Si layer after
the planarization process as shown in Fig. 5. However, this
planarization process may lead to some problems. One is
with the geometry in the planarized nc-Si layer, i.e., the size
and the location of nc-Si dots and the crystallization of SiO2
leading to an anisotropic current characteristic. Figure 12
shows planar TEM images and the cross sectional SEM image of sample D. TEM images indicate that some nc-Si dots

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FIG. 12. a,b Planar TEM and c cross sectional SEM images of the
emitter sample D with a planarized nc-Si layer.

with a size of around 5 nm have remained crystalline and the

SiO2 region is amorphous. Most of the nc-Si dots are oxidized, which leads to low current density. If we can increase
the number of unoxidized nc-Si dots, the electron emission
current may be increased. However, the thickness of SiO2
serving as the tunnel barrier is expected to be more than 50
nm from a consideration of the small number of nc-Si dots in
the planarized nc-Si layer and the thickness of the layer. This
thickness is relatively large for electrons to tunnel through
the SiO2 barrier. Trap sites resulting from impurities may
allow a higher conduction. It has been reported that SiO2
including phosphorus displays a hysteresis in the
capacitance-voltage
characteristic
of
metal-oxidesemiconductor devices.21,23 In that case, current characteristics were found to be sensitive to the measurement temperature. Figure 13 shows the dependence of the current
characteristics on temperature from 100 to 300 K. Although
a small difference between characteristics was observed, it
was negligible from the viewpoint of the contact resistance
between the sample and the measurement probe or other undesirable disturbing elements. Thus, we can conclude that the
temperature dependence of current characteristics resulting
from electron trapping sites was quite small. Figure 14
shows that FN plots of observed characteristics from the planarized samples indicate a linear behavior. These investiga-

FIG. 14. FowlerNordheim plot extracted from the emission characteristics

of sample D planarized by a phosphorus doping step.

tions suggest that the mechanism of the electron transport is

not a hopping process but a tunneling process. For more
detailed investigation, the energy band profile and the electric field in the nc-Si layer were calculated from the Poisson
equation under the estimated structure as shown in Fig.
15a. The dielectric constant of Si and SiO2 were assumed
to be 12 and 3.9, respectively, and the quantum confinement
effect in nc-Si dots was ignored. Figure 15b shows the
energy band profiles of the nc-Si layer with and without a
single nc-Si dot. The thickness of the tunnel barrier without
dot, t ox , is divided into two thinner SiO2 layers, t 1 and t 2 .
Thus, electrons go through the thinner SiO2 layer labeled as
A by direct tunneling. Then, accelerated electrons travel
through the nc-Si dot with a low scattering rate, followed by
a FN tunnel transport through the SiO2 layer B with a
thinner and lower tunnel barrier than the SiO2 layer without
the nc-Si dot. This means that the electron transport through
the SiO2 layer is enhanced due to the presence of Si dots.
Moreover, as shown in Fig. 15c, the electric field around
the nc-Si dot is enhanced due to the spherical shape. These
roles played by nc-Si dots enhance the electron transport
density. Figure 16 shows tunnel rates, calculated by
WentzelKramersBrillouin WKB approximation, with
the 50-nm-thick SiO2 layer with and without one nc-Si dot as
shown in Fig. 15 and the SiO2 Si well-SiO2 Si structure as
shown in the inset of Fig. 16. All curves are normalized by
the maximum tunnel rate. A single nc-Si dot in the SiO2
increased the tunneling rate by more than 4 and 2 orders of
magnitude, respectively, compared to cases of without a dot
and the Si well. These curves illustrate the important role of
nc-Si dots with a small spherical shape. These investigations
show that the effect of phosphorus in a SiO2 layer to the
electric characteristic is small, at least in the FN tunnel transport. The impurities in a SiO2 film cause deep trap sites of
4 eV with a small capture cross section of 1014 1018
cm2 24,25 so the effect of phosphorus in a SiO2 film is expected to be small to electron transport.
The control of the oxidation and the planarization processes is quite important because these processes define the

FIG. 13. Dependence of the diode and emission current on temperature, in

the range of 100300 K, for sample D.
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FIG. 17. Diode and emission current characteristics of samples planarized

by 10 min sample E and 20 min sample F oxidation.

FIG. 15. a Structure of the measured sample, which is estimated from

TEM and SEM images, for calculations of the electric field and the potential
profile. b The band diagram around the nc-Si dot. The straight line marked
by the label SiO2 layer indicates the band diagram of the SiO2 layer
without the nc-Si dot. t 1,2 and t ox indicate the thickness of tunnel
barriers for electrons in the conduction band of the Si substrate with and
without the nc-Si dot, respectively. c The electric field distribution in the
nc-Si layer. The regions labeled as A and B are the SiO2 layers between the Si substrate and the nc-Si dot and between the Au film and the
nc-Si dot, respectively.

device structure. A high temperature planarization process

makes a fine control of the structure difficult because the
oxidation of the nc-Si dots may occur during the planarization process even in N2 ambient as shown in Fig. 12. For the
fine control, we performed lower temperature oxidation, the
phosphorus doping, and the annealing process, separately.

After the deposition of nc-Si dots onto the Si substrate, the

sample was oxidized at 850 C, followed by the phosphorus
diffusion at 1150 C with P2 O5 for a few minutes. For a
complete planarization, the annealing process was performed
at 1000 C for 10 min. Varying time of the oxidation and the
phosphorus diffusion can control the structure in the nc-Si
layer. A sample prepared by the oxidation period of 20 min
and the phosphorus diffusion time of 6 min showed an emission current of 0.25 A/cm2 and an efficiency of 10%. Although this sample had a short lifetime, the separation of
these processes increases the controllability of the structure
and may lead to a higher emission efficiency.
C. Emission characteristics from devices planarized
without the phosphorus diffusion

The planarization of the nc-Si layer can improve the device performance. However, a large amount of impurities in
a SiO2 reduces the dielectric endurance and enhances the
oxidation of nc-Si dots, as mentioned above. Thus, a planarization process without impurity atoms is estimated to be
better. As mentioned in the previous section, two types of
sample were prepared. One referred as sample E was oxidized for 10 min, the other sample F was oxidized for 20
min. Figure 17 indicates current characteristics of the two
samples. The longer oxidation reduced diode and emission
current, and increased the emission efficiency. The geometrical difference between the two samples is the SiO2 thickness
and the number of nc-Si dots. Since the current level and the
cross sectional SEM images of these samples are roughly the
same as samples including phosphorus observed by TEM,
the planarized device structure is expected as shown in Fig.
18a. While the sample oxidized for a longer time had only
a small number of nc-Si dots as shown on the left side of Fig.
18a, some dots overlapped each other randomly as shown
on the right side in the short-oxidized sample. Figure 18b
indicates the electric field distribution in this structure. The
arrows indicate the vector of the electric field, which drives

FIG. 16. Tunnel rates, calculated by WKB approximation, for an 50-nmthick SiO2 layer with and without one nc-Si dot as shown in Fig. 15 and the
SiO2 Si well-SiO2 Si structure as shown in the inset. All curves are normalized by the maximum tunnel rate.
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FIG. 18. a Estimated structure of the planarized nc-Si layer; b the electric field distribution in the nc-Si layer. Allows indicate directions of the
electric field.

the flow of electrons. When many dots exist, there are many
current paths due to the interactions between dots. Thus,
large current flows. However, electrons transporting in various directions suffer from scattering process. Thus, electrons
lose their gained energy easily, leading to lower emission
efficiency. In the case of a small number of dots, electrons
are accelerated in the direction perpendicular to the substrate.
So, the probability for electrons to lose their energy is small
resulting in higher emission efficiency.
Next, we investigate the effect of the size of nc-Si dots
to the emission characteristic. By using the pulsed gas supply
method explained in the previous section, three average sizes
were prepared; 61, 82, and 105 nm. We refer to
samples with a dot size of 61 and 105 nm as sample G
and sample H, respectively. The sample with a dot size of
82 nm is the same as sample E. The thickness of the asdeposited nc-Si layer is 120 nm. After the deposition, the
planarization process was performed. The conditions were
the same as the sample oxidized for 10 min. Only the sample
with an average diameter of 10 nm did not show any emission current at room temperature. However, at 77 K, electron
emission could be observed. The other two devices indicated
almost the same characteristic. The emission efficiency of
samples with average sizes of 6 and 8 nm are 0.99 and
0.54%, respectively. The smaller nc-Si dots give higher efficiency. Hereafter, we focus our discussion on the characteristic from the sample having the largest dots. Figure 19a
indicates the emission characteristics of the sample I with an
average size of 10 nm at various temperatures. The diode
current decreases with decreasing measurement temperature.
The strong temperature dependence of the diode current sug-

FIG. 19. a Diode and emission characteristics of sample H with an average

size of 10 nm at room temperature RT, 150 K, and 77 K. Except for 77 K,
only diode characteristics are shown due to an absence of emission current.
b Diode current as a function of 1000/T at various applied voltages. Applied voltages are 10, 20, and 30 V. Activation energy of each applied
voltage estimated from the slope of the plot is also shown.

gests that the electron transport may be based on a hopping

process. Figure 19b shows diode current as a function of
1000/T at various applied voltages, where T is the measurement temperature. The activation energy for the electron
transport is estimated to be around 60 meV from slopes of
plots. If trap sites for an electron hopping exist in SiO2 , all
samples should show the same behavior. Thus, the sites to
trap electrons or reduce energy of electrons are expected to
result from nc-Si dots because the difference of measured
samples is the size of nc-Si dots. In the electron emitter
based on the PS layer, electrons are expected to transport
ballistically because nc-Si dots in the PS layer are smaller
than the electron mean free path. The electron mean free path
is dominated by phonon scattering at room temperature, and
is expected to be a few nm.26,27 The mean free path increases
with a reduction of temperature,28 to about 10

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J. Appl. Phys., Vol. 92, No. 5, 1 September 2002

nm at 77 K, which is comparable to the largest size of the

nc-Si dots. The strong temperature dependence of the diode
current can be explained from a viewpoint of the electron
transport through quantum dots sandwiched between two
electrodes. There are some reports about the transport
through quantum dots covered with an insulator, which
showed a strong temperature dependence of the
conductance.29,30 In the investigation of germanium dots in
SiO2 , Fujii et al.31 suggested that the temperature dependence resulted from the difference in the energy of the discrete subbands in each dot due to the size dispersion. The
electrons on the conduction band of a dot hop to the next dot
due to the energy difference. From these considerations, the
mechanism of the electron transport with largest dots may be
explained as follows: electrons go through nc-Si dots loosing
their energy due to a phonon scattering. Thus, the energy
difference of quantized subbands in dots serves as the hopping states of electrons. At lower temperatures, the probability of scattering is reduced due to an extended mean free
path, and electrons can transport without the effect of energy
difference because electrons have enough energy to go over
the energy barrier. Then, electrons are emitted from the
sample. This mechanism is consistent with the experimental
fact that higher efficiency is obtained for samples with
smaller nc-Si dots. For a more detailed discussion, the energy distribution of the emitted electrons and a geometrical
analysis should be investigated.

Nishiguchi, Zhao, and Oda

FIG. 20. Electron emission efficiency as a function of the thickness of the

Au top electrode.

of the electrode films because the work function of 4 eV is

smaller and the mean free path is longer than those of metal
films. Moreover, a thinner film formed by CVD can be obtained easily, and cohesion is also improved. Yokoo et al.37
reported the electron emitter composed of a few-nm-thick
SiO2 sandwiched between a thin a-Si electrode and a Si substrate. They compared the Al top electrode with the a-Si top
electrode, and indicated that the a-Si top electrode enhanced
the electron efficiency by more than one order of magnitude
so, replacing the Au top electrode with an a-Si film may
enhance the efficiency of the electron emitter using nc-Si
dots.

D. Effect of the Au top electrode

Electrons accelerated in nc-Si dots and the SiO2 layer

are extracted into the vacuum through the top Au electrode.
In the Au film, electrons loose their energy due to scattering,
and electrons with an energy less than the work function of 5
eV are absorbed into the Au electrode without emission. The
electron mean free path in a metal film, which is determined
by electronelectron interaction and electronphonon interaction, is shorter than that of Si.32,33 Although the mean free
path depends on the electron energy, the mean free path of
hot electrons with an energy of higher than 5 eV is estimated
to be 57 nm.34 Thus, a thinner Au electrode is desirable.
However, a very thin film, less than 10 nm, formed by an
evaporation method can hardly cover the surface
completely.35,36 Especially, the poor cohesion between Au
film and SiO2 makes the formation of very thin Au film
difficult. The effect of the Au film with the thickness of more
than 10 nm was investigated. Figure 20 shows the emission
efficiency as a function of the thickness of the Au film. The
number of emitted electrons is proportional to exp(t/lm,
where t is the Au film thickness, l m the electron mean free
path. The mean free path estimated from the slope of the plot
is 5.8 nm, which is plausible. When the slope is extrapolated,
the interception at zero thickness is not 100% but 10%. This
means that 90% of all electrons reaching the Au film are
either reflected quantum mechanically at Au surface or having an energy of less than the work function of the Au film.
While electrons go through the conduction band of SiO2 ,
electrons loose their energy. Under this consideration, polycrystalline poly- or amorphous a- Si may be good choices

IV. CONCLUSION

Electron emitters using nc-Si dots have been investigated. A planarization technique based on annealing processes has improved the emission efficiency, to 5%. The
optimization of the planarization condition may lead to a
higher efficiency. The basic mechanism of this device has
been found to be the same as the emitter using PS. However,
there are significant differences in the number of nc-Si dots
and the thickness of SiO2 , where electrons are accelerated
and gain high energy. In the case of electron emitter using
nc-Si dots, electrons are accelerated in thick SiO2 layer.
Thus, an optimization of the thickness of SiO2 can improve
the efficiency and the device lifetime because the thickness
determines the electric field and the scattering probability.
The increase of nc-Si dots and the thinner Si film electrode
may lead to a higher emission current. The higher emission
current and efficiency are desirable for a flat panel display
and electron beam sources for various electron microscopes
with a lower operation voltage. Koshida et al., demonstrated
that electron emitters using PS can work under the lowvacuum condition. This capability may be used in other advanced applications. The present work introduces a new type
of device using Si quantum dots formed by various methods.
The main feature is the inclusion of very small quantum dots
in the insulator film, sandwiched between the thin electrode
film and the substrate. This device does not require a fine
control of the size and location of quantum dots.

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J. Appl. Phys., Vol. 92, No. 5, 1 September 2002

ACKNOWLEDGMENTS

This work was supported by CREST, JST. The authors

are indebted to Dr. R. T. Tung for critical reading of this
manuscript.
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