: 3:00 pm-5:00 pm
Date
Duration
: 21-Feb-2009
: 2 Hours
INSTRUCTIONS TO CANDIDATES
Marks
Marks
Obtained
Question
1
25
Question
2
25
Question
3
25
Question
4
25
Total
Marks
100
Midterm Examination
2008/2009
Semester II
(b) In the circuit shown in Fig. 1, find the diode voltage V D and the supply voltage V such
that the current is I D 0.4 mA. Assume the diode cut-in voltage is V 0.7 V. Also
determine the power dissipated in the diode.
(9 marks)
Fig. 1
Midterm Examination
2008/2009
Semester II
(c) Consider the Zener diode circuit shown in Fig. 2. The Zener breakdown voltage is
VZ 5.6 V at I Z 0.1 mA, and the incremental Zener resistance is rz 10 .
Determine VO for R L and R L 2 k .
(10 marks)
Fig. 2
Midterm Examination
2008/2009
Semester II
(b) The input voltage to the half-wave rectifier in Fig. 3 is S 75 sin[ 2 (60)t ] V. Assume
a diode cut-in voltage of V 0 V. The ripple voltage is to be no more than Vr 4 V. If
the filter capacitor is 50 F, determine the minimum load resistance that can be
connected to the output.
(4 marks)
Fig. 3
Midterm Examination
2008/2009
Semester II
(c) The input signal voltage to the full-wave bridge rectifier circuit in Fig. 4 is
I 160 sin[ 2 (60)t ] V. Assume V 0.7 V for each diode. Determine (i) the
required turns ratio of the transformer to produce a peak output voltage of 100 V, (ii) the
diode PIV rating, and (iii) the average value of the output voltage.
(8 marks)
Fig. 4
Midterm Examination
2008/2009
Semester II
Fig. 5
Midterm Examination
2008/2009
Semester II
(b) For the diode clipper circuit in Fig. 6, plot O versus time over two periods for
sinusoidal input signal. Assume V 0 for each diode and I (max) VB1 and B 2 .
(7 marks)
Fig. 6
Midterm Examination
2008/2009
Semester II
(c) A diode clamper circuit with sinusoidal input signal is shown in Fig. 7. Assume
V r f 0 . Plot (i) the capacitor voltage versus time and (ii) the output voltage versus
time.
(8 marks)
Fig. 7
(d) Consider the circuit in Fig. 8. The output of a diode OR logic gate is connected to the
input of a second diode OR logic gate. Assume V 0 for each diode. Determine the
output VO1 and VO 2 for: (i) V1 V2 0 ; (ii) V1 5 V, V2 0 V; and (iii)
V1 V2 5 V.
(6 marks)
Fig. 8