Piotr Musznicki 1
Jean-Luc SCHANEN 2
senior member IEEE,
Bruno Allard 3
member IEEE
Piotr J Chrzan 1
1 Politechnika Gdanska,
Wydzial Elelktrotechnki i Automatyki KMiE ul. SOBIESKIEGO 7; 80-216 GDASK pchrzan@ely.pg.gda.pl
2 Laboratoire d'Electrotechnique de Grenoble,
CNRS UMR 5529 INPG/UJF, ENSIEG BP.46, F-38402 SMH cedex GRENOBLE jean-luc.schanen@leg.ensieg.inpg.fr
3 Centre de Genie Electrique de Lyon
CNRS UMR 5005 CEGELY INSA, 2 av Jean Capelle, 69621 Villeurbanne cedex Bruno.allard@cegely.insa-lyon.fr
Abstract This paper illustrates how to account for all
parasitic due to the layout of a power converter (inductive and
capacitive), in order to forecast Electromagnetic Interferences
(EMI). The method is generic, and is validated here in the
simple example of a DC-DC converter, realized on different
technologies: Insulated Metal Substrate (IMS), Printed Circuit
Board (PCB). In addition, several layouts aspects will be
investigated. Conclusions are given on the influence of layout
and all other components on EMI.
I.
INTRODUCTION
Output
capacitors
Input capacitors
(one electrolytic and
two paralleled
ceramic)
Diode
MOSFET
Inductor
II.
EMC MODELS
MOSFET Diode
parameters
Optimization
MOSFET Diode
simulation
(static or dynamic)
Measurement
(static or dynamic)
1)
For MOSFET
VTO - Zero-bias threshold voltage 3.76v[V],
IS - Bulk p-n saturation current 1[pA],
KP Transconductance 83.2,
RD - Drain ohmic resistance 1[m],
RS - Source ohmic resistance 1[m],
RG - Gate ohmic resistance 10 [],
THETA - Mobility modulation 2.025[1/V],
Crss = 1.14[nF] , Coss = [0.1n] Ciss = 14.8[nF]
Cgs = 14.8[nF] and Cds = 2.09[nF] - the inter-electrode
capacitances.
2)
For diode
Is - saturation current injection 1[nA],
rs
- series resistance 7.4[m],
Vj - voltage injection 0.3[V],
Cj - junction capacitance 1.47[nF]
B. Passive components models
As far as conducted EMI are considered, a typical ESLESR representation is sufficient for capacitors [5]. The
ceramic decoupling capacitors are of high quality and
present a only 1 nH Equivalent Series Inductance (ESL).
Electrolytic capacitors have been characterized with an
impedance bridge, and values of 30 nH and 50 m have
been obtained.
The measurement of the SESI 18K 1WR [6] shows that a
simple paralleled R-L-C representation is suitable until
several tenth of MHz. Parameters are given for a 8 A DC
bias:
L = 14.7 H
R = 3.96 k
C = 13 pF
Measurements have been carried out using an HP 4194A
impedance bridge, using the suitable test fixture, which
allows a DC current polarization.
C. Cabling model
This DC-DC converter has been realized on IMS. This
technology allows to obtain low inductive interconnections
between components, but also high value of parasitic
capacitance.
Values of self and mutual inductance of copper tracks
have been calculated using InCa software based on PEEC
method [7-8]. This method provides a very powerful
approach to account for non ideal behavior of conductors. It
is based on analytical formula to compute inductance and
coupling, provided a uniform current density. However, due
to bondings on copper tracks (see Fig. 1), current direction
is unknown, and a complete inductive meshing must be
used, contrary to other modeling used in the past [9].
According to PEEC method, a capacitive meshing can
also bee used (Fig.3).
Using strictly results from PEEC method in circuit
simulator is really too heavy for computer simulation.
Therefore, a model reduction for inductive aspects has been
proposed. The idea is similar to scattering matrix from the
microwave theory: the complete geometry is seen from
input-output only. For each conductor linking several
1
5
6
Vi =
dIij
dt
j =1
III.
A.
MODEL VALIDATION.
Simulation.
Powerful simulator is needed, which allows to make
simulations with a sufficient small time step, according to
EMC frequency range required. Because of very high time
constants of basic boost converter and of LISN, long
simulations have been carried out to obtain steady state of
working application.
Simulations of complex model of the considered
converter have been carried out using the circuit simulator.
On Fig. 5. is presented equivalent Saber scheme of boost
converter, LISN and load where all interconnections of
converter (IMS, screws and bondings) are summarized into
a single macro components, using all differential equations.
In this case different calculation time step can generated
different results what could occur especially in the high
frequencies range, so adequately small step should be
chosen (for frequencies of emitted EMI above 30 MHz it
must be smaller than 0.016 s). Therefore, this operation
takes a lot of computer power, memory and of course time.
Exploitation of simulation in term of EMI, is simply
achieved with FFT of LISN voltage. Results are presented
on Fig. 6.
Another validation can be made by comparison on
MOSFET voltage (Fig. 7). The correlation is very good,
taking into account all measurement inaccuracies (voltage
cannot really be measured directly across the chip).
Driver
LISN
Common
mode filter
B. Measurement
An experimental investigation on conducted EMI of DCDC boost has been carried out. The converter has been
connected to power supply through a LISN, on which
spectrum from 50 kHz to 30 MHz has been measured in
typical conditions of work (Fig. 8). Many difficulties were
encountered to achieve accurately this measurement. Indeed,
half of the noise emitted from the converter was due to the
driver. Voltage quick variations of the driver (15 V) are
synchronous with the one of power circuit (42 V). Reducing
of noise emitted by driver has been realized using common
mode filter and by disposing it far from the ground plane
(Fig. 9), but total decreasing of it was not possible.
Another difficulty was the modeling of the load: the
100 W resistors exhibit a large capacitor with the reference
plane, which has not been taken into account in the Saber
model. Therefore, even if the global shape of the EMI
spectrum is similar, a 10dB difference is still noticeable
between simulation and measurement.
The comparison of power MOSFET voltage however is
nearly perfect (Fig. 7), what validates the semiconductor and
inductive modeling.
The EMI level on the two legs of the LISN (plus and
minus leg) are exactly the same. This remark can be made in
both simulation and measurement. This phenomenon can be
attributed to the use of nearly perfect input capacitors
(ceramic), which leads to a symmetrical path between plus
and minus tracks.
IV.
SENSITIVITY STUDY
B. Layout influence
Inductive modeling of the tracks is not negligible in
accurate EMI forecasting. Stray inductance plays a great
role in commutation and has an effect on semiconductor
behavior. In addition, voltage ringing occur which
contribute to EMI generation. The influence of stray
inductance is shown on Fig. 12, where comparison of results
of simulation with and without Saber macro component
generated in InCa is presented.
On the other side parasitic capacitances of copper track
can be removed. For IMS circuit, stray capacitance are of
great values and their role is consequently significant.
Removing parasitic capacitance gives great different on
spectra for all frequency range of emitted EMI. It can be
said that parasitic capacitance are important parameter for
EMC behavior description.
In the same idea, it is easy to replace IMS substrate with
conventional PCB. This results in an increase of stray
inductance, and a decrease of stray capacitance (between
1 pF to 50 pF for PCB and from 100 pF to 1000 pF for
IMS). This difference is due to the modified distance to the
ground plane (~1.3 mm for PCB and ~70 m for IMS).
The comparison of LISN spectrum for these two
technologies is presented Fig. 14. Disturbances generated in
PCB layout circuit are much lower than those from IMS,
due to lower stray capacitance.
V.
VII.
Fig. 15 Simplified equivalent circuit for EMI estimation.
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CONCLUSION