SEMINAR REPORT

ON
EMBEDDED SYSTEM

Submitted by:
Sachin Tyagi
EC-0600331089
B.M.A.S. ENGG COLLEGE
 CONTENTS
1. 8051 Microcontroller Architecture
2. 8051 Pin Diagram
3. Variant in Atmel 8051 Microcontroller
4. Features of AT89c51 and AT89c52
5. Features of LCD Used
6. Features of Stepper Motor and its Drivers
7. Applications
8051 Microcontroller
AT89C51:
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
Bytes of Flash programmable and erasable read only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
Compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conventional
Non-volatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides
a highly-flexible and cost-effective solution to many embedded control applications.

Block Diagram:
Memory Organization:
Logical Separation of Program Data Memory:
All Atmel Flash microcontrollers have separate address spaces for program and data
memory. The logical separation of program and data memory allows the data memory to
be accessed by 8-bit addresses, which can be more quickly stored and manipulated by 8-
bit CPU. Nevertheless, 16-bit data memory addresses can also be generated through the
DPTR register. Program memory can only be read. There can be up to 64K bytes of
directly addressable program memory. The read strobe for external program memory is
the Program Store Enable signal (PSEN). Data memory occupies a separate address space
from program memory. Up to 64K bytes of external memory can be directly addressed in
the external data memory space. The CPU generates read and write signals, RD and WR,
during external data memory accesses. External program memory and external data
memory can be combined by applying the RD and PSEN signals to the input of an AND
gate and using the output of the gate as the read strobe to the external program/data
memory.

Program Memory:
After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a
fixedlocation in program memory. The interrupt causes the CPU to jump to that location,
where it executes the service routine. External Interrupt 0, for example, is assigned to
location 0003H. If External Interrupt 0 is used, its service routine must begin at location
0003H. If the interrupt is not used, its service location is available as general purpose
program memory. The interrupt service locations are spaced at 8-byte intervals: 0003H
for External Interrupt 0, 000BH for Timer 0,0013H for External Interrupt 1, 001BH for
Timer 1, and so on. If an interrupt service routine is short enough (as is often the case in
control applications), it can reside entirely within that 8-byte interval. Longer service
routines can use a jump instruction to skip over subsequent interrupt locations, if other
interrupts are in use. The lowest addresses of program memory can be either in the on-
chip Flash or in an external memory. To make this selection, strap the External Access
(EA) pin to either VCC or GND. For example, in the AT89C51 with 4K bytes of on-chip
Flash, if the EA pin is strapped to VCC, program fetches to addresses 0000H through
0FFFH are directed to the internal Flash. Program fetches to addresses 1000H through
FFFFH are directed to external memory. In the AT89C52 (8K bytes Flash), EA = VCC
selects addresses 0000H through 1FFFH to be internal and addresses 2000H through
FFFFH to be external. If the EA pin is strapped to GND, all program fetches are directed
to external memory. The read strobe to external memory, PSEN, is used for all external
program fetches. Internal program fetches do not activate PSEN. The hardware
configuration for external program execution. Note that 16 I/O lines (Ports 0 and 2) are
dedicated to bus functions during external program memory fetches. Port 0 serves as a
multiplexed address/data bus. It emits the low byte of the Program Counter (PCL) as an
address and then goes into a float state while waiting for the arrival of the code byte from
the program memory. During the time that the low byte of the Program Counter is valid
on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch.
Meanwhile, Port 2 emits the high byte of the Program Counter (PCH). Then PSEN
strobes the external memory, and the microcontroller reads the code byte.
Program Memory:

Program memory addresses are always 16 bits wide, even though the actual amount of
program memory used may be less than 64K bytes. External program execution sacrifices
two of the 8-bit ports, P0 and P2, to the function of addressing the program memory.

Data Memory:
The right half of the internal and external data memory spaces available on Atmel’s Flash
microcontrollers. Hardware configuration for accessing up to 2K bytes of external RAM.
In this case, the CPU executes from internal Flash. Port 0 serves as a multiplexed
address/data bus to the RAM, and 3 lines of Port 2 are used to page the RAM. The CPU
generates RD and WR signals as needed during external RAM accesses. You can assign
up to 64K bytes of external data memory. External data memory addresses can be either 1
or 2 bytes wide. One-byte addresses are often used in conjunction with one or more other
I/O lines to page the RAM. Two-byte addresses can also be used, in which case the high
address byte is emitted at Port 2.
.
Internal data memory addresses are always 1 byte wide, which implies an address space
of only 256 bytes. However, the addressing modes for internal RAM can in fact
accommodate 384 bytes. Direct addresses higher than 7FH access one memory space and
indirect addresses higher than 7FH access a different memory space. Thus, the Upper 128
and SFR space occupying the same block of addresses, 80H through FFH, although they
are physically separate entities. The lowest 32 bytes are grouped into 4 banks of 8
registers. Program instructions call out these registers as R0 through R7. Two bits in the
Program Status Word (PSW) select which register bank is in use. This architecture allows
more efficient use of code space, since register instructions are shorter than instructions
that use direct addressing
Programming Status Word:
The Instruction Set:
All members of the Atmel microcontroller family execute the same instruction set. This
instruction set is optimized for 8- bit control applications and it provides a variety of fast
addressing modes for accessing the internal RAM to facilitate byte operations on small
data structures. The instruction set provides extensive support for 1-bit variables as a
separate data type, allowing direct bit manipulation in control and logic systems that
require Boolean processing. The following overview of the instruction set gives a brief
description of how certain instructions can be used.

Program Status Word:

The Program Status Word (PSW) contains status bits that reflect the current state of the
CPU. The PSW, shown in Figure 11, resides in SFR space. The PSW contains the Carry
bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the
Overflow flag, a Parity bit, and two user-definable status flags. The Carry bit, in addition
to serving as a Carry bit in arithmetic operations, also serves as the “Accumulator” for a
number of Boolean operations.
The bits RS0 and RS1 select one of the four register banks shown in Figure 8. A number
of instructions refer to these RAM locations as R0 through R7. The status of the RS0 and
RS1 bits at execution time determines which of the four banks is selected. The Parity bit
reflects the number of 1s in the Accumulator: P=1 if the Accumulator contains an odd
number of 1s, and P=0 if the Accumulator contains an even number of 1s. Thus, the
number of 1s in the Accumulator plus P is always even. Two bits in the PSW are
uncommitted and can be used as general purpose status flags.

Addressing Modes:
The addressing modes in the Flash microcontroller instruction set are as follows.

Direct Addressing:
In direct addressing, the operand is specified by an 8-bit address field in the instruction.
Only internal data RAM and SFRs can be directly addressed.

Indirect Addressing:
In indirect addressing, the instruction specifies a register that contains the address of the
operand. Both internal and external RAM can be indirectly addressed. The address
register for 8-bit addresses can be either the Stack Pointer or R0 or R1 of the selected
register bank. The address register for 16-bit addresses can be only the 16-bit data pointer
register, DPTR.

Register Instructions:
The register banks, which contain registers R0 through R7, can be accessed by
instructions whose opcodes carry a 3- bit register specification. Instructions that access
the registers this way make efficient use of code, since this mode eliminates an address
byte. When the instruction is executed, one of the eight registers in the selected bank is
accessed. One of four banks is selected at execution time by the two bank select bits in
the PSW.

Register-Specific Instructions:
Some instructions are specific to a certain register. For example, some instructions
always operate on the Accumulator, so no address byte is needed to point to it. In these
cases, the opcode itself points to the correct register. Instructions that refer to the
Accumulator as A assemble as Accumulator-specific opcodes.

Indexed Addressing:
Program memory can only be accessed via indexed addressing. This addressing mode is
intended for reading look-up tables in program memory. A 16-bit base register (either
DPTR or the Program Counter) points to the base of the table, and the Accumulator is set
up with the table entry number. The address of the table entry in program memory is
formed by adding the Accumulator data to the base pointer. Another type of indexed
addressing is used in the “case jump” instruction. In this case the destination address of a
jump instruction is computed as the sum of the base pointer and the Accumulator data.
Pin Configuration:

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of
RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition,
the AT89C51 is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port and interrupt system to continue
functioning. The Power-down Mode saves the RAM contents but freezes the oscillator
disabling all other chip functions until the next hardware reset.
Pin Description:
VCC:
Supply voltage.
GND:
Ground.
Port 0:
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 may also be configured to be the multiplexed low order
Address /data bus during accesses to external program and data memory. In this mode P0
has internal pull ups. Port 0 also receives the code bytes during Flash programming,
and outputs the code bytes during program verification. External pull ups are required
during program verification.

Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port
1 also receives the low-order address bytes during Flash programming and verification.

Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port
2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In
this application, it uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents
of the P2 Special Function Register. Port 2 also receives the high-order address bits and
some control signals during Flash programming and verification.
Port 3:
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also
serves the functions of various special features of the AT89C51 as listed below: Port 3
also receives some control signals for Flash programming and verification.

ALE/PROG:
Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE
Pulse is skipped during each access to external Data Memory. If desired, ALE operation
can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting
the ALE-disable bit has no effect if the microcontroller is in external execution mode.
RESET:
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.
PSEN:
Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
EA/VPP:
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming, for parts that
require 12-volt VPP.
XTAL1:
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2:
Output from the inverting oscillator amplifier.

Oscillator Characters:
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an external
clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in
Figure 2. There are no requirements on the duty cycle of the external clock signal, since
the input to the internal clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time specifications must be observed.

Idle Mode:
In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be terminated
by any enabled interrupt or by a hardware reset. It should be noted that when idle is
terminated by a hard ware reset, the device normally resumes program execution, from
where it left off, up to two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the
port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin
when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.

Programming the Flash:

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased
state (that is, contents = FFH) and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.
The low-voltage programming mode provides a convenient way to program the
AT89C51 inside the user’s system, while the high-voltage programming mode is
compatible with conventional third party Flash or EPROM programmers. The AT89C51
is shipped with either the high-voltage or low-voltage programming mode enabled.
The AT89C51 code memory array is programmed byte by byte in either programming
mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory
must be erased using the Chip Erase Mode.

Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should be set up
according to the Flash programming mode table. To program the AT89C51, take the
following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 1.5 ms.

Repeat steps 1 through 5, changing the address and data for the entire array or until the
end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle.
During a write cycle, an attempted read of the last byte written will result in the
complement of the written datum on PO.7. Once the write cycle has been completed, true
data are valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY
output signal. P3.4 is pulled low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed
code data can be read back via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is achieved by observing that
their features are enabled.

Chip Erase: The entire Flash array is erased electrically by using the proper combination
of control signals and by holding ALE/PROG low for 10 ms. The code array is written
with all “1”s. The chip erase operation must be executed before the code memory can be
re-programmed.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a
normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must
be pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming

Programming the AT89C51:

Special Function Registers:
A map of the on-chip memory area called the Special Function Register (SFR) space.
Note that not all of the addresses are occupied, and unoccupied addresses may not be
implemented on the chip. Read accesses to these addresses will in general return random
data, and write accesses will have an indeterminate effect. User software should not write
1s to these unlisted locations, since they may be used in future products to invoke.

Data Memory:
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. That means the upper 128 bytes
have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode
used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM
or the SFR space. Instructions that use direct addressing access SFR space. new features.
In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers:
The individual interrupt enable bits are in the IE register. Two priorities can be set for
each of the six interrupt sources in the IP register. specifies whether the CPU accesses the
upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access
SFR space. For example, the following direct addressing instruction accesses the SFR at
location 0A0H (which is P2).
Instructions that use indirect addressing access the upper 128 bytes of RAM. For
example, the following indirect addressing instruction, where R0 contains 0A0H,
accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

Timer 0 and 1:
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in
the AT89C51.

Timer 2:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.
The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three
operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2
and TL2. In the Timer function, the TL2 register is incremented every machine cycle.
Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the
oscillator frequency. In the Counter function, the register is incremented in response to a
1-to-0 transition at its corresponding external input pin, T2. In this function, the external
input is sampled during S5P2 of every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is incremented. The new count value
appears in the register during S3P1 of the cycle following the one in which the transition
was detected. Since two machine cycles (24 oscillator periods) are required to recognize a
1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure
that a given level is sampled at least once before it changes, the level should be held for
at least one full machine cycle.

Capture Mode:
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit
can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same
operation, but a 1- to-0 transition at external input T2EX also causes the current value in
TH2 and TL2 to be captured into CAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can
generate an interrupt.
Auto-reload (Up or Down Counter):
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-
reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to
count up. When DCEN is set, Timer 2 can count up or down, depending on the value of
the T2EX pin.

Interrupts:
The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of
these interrupt sources can be individually enabled or disabled by setting or clearing a bit
in Special Function Register IE. IE also contains a global disable bit, EA, which disables
all interrupts at once. Note that bit position IE.6 is unimplemented. In the AT89C51, bit
position IE.5 is also unimplemented. User software should not write 1s to these bit
positions, since they may be used in future AT89 products. Timer 2 interrupt is generated
by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags
cleared by hardware when the service routine is vectored . In fact, the service routine may
have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit
will have to be cleared in software. . The Timer 0 and Timer 1 flags, TF0 and TF1, are set
at S5P2 of the cycle in which the timers overflow.
SERIAL COMMUNICATION:
Computers transfer data in two ways:
Parallel: Often 8 or more lines (wire conductors) are used to transfer data to a device that
is only a few feet away.
Serial: To transfer to a device located many meters away, the serial method is used. The
data is sent one bit at a time.

At the transmitting end, the byte of data must be converted to serial bits using parallel-in-
serial-out shift register. At the receiving end, there is a serial in-parallel-out shift register
to receive the serial data and pack them into byte. When the distance is short, the digital
signal can be transferred as it is on a simple wire and requires no modulation. If data is to
be transferred on the telephone line, it must be converted from 0s and 1s to audio tones.
This conversion is performed by a device called a modem, “Modulator/demodulator”.
Serial data communication uses two methods; Synchronous method transfers a block
of data at a time Asynchronous method transfers a single byte at a time It is possible to
write software to use either of these methods, but the programs can be tedious and long.
There are special IC chips made by many manufacturers for serial communications
UART (universal asynchronous Receiver transmitter) USART (universal
synchronous asynchronous Receiver-transmitter). If data can be transmitted and
received, it is a duplex transmission. If data transmitted one way a time, it is referred to as
half duplex. If data can go both ways at a time, it is full duplex.

A protocol is a set of rules agreed by both the sender and receiver on;
How the data is packed
How many bits constitute a character
When the data begins and ends. Asynchronous serial data communication is widely used
for character-oriented transmissions;
Each character is placed in between start and stop bits, this is called framing.
Block-oriented data transfers use the synchronous method.
The start bit is always one bit, but the stop bit can be one or two bits The start bit is
always a 0 (low) and the stop bit(s) is 1 (high)

SBUF is an 8-bit register used solely for serial communication. For a byte data to be
transferred via the TxD line, it must be placed in the SBUF Register. The moment a byte
is written into SBUF, it is framed with the start and stop bits and transferred serially via
the TxD line SBUF holds the byte of data when it is received by 8051 RxD line. When
the bits are received serially via RxD, the 8051 de-frames it by eliminating the stop and
start bits, making a byte out of the data received, and then placing it in SBUF
MOV SBUF,#’D’ ;load SBUF=44h, ASCII for ‘D’
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
SCON is an 8-bit register used to program the start bit, stop bit, and data bits of
data framing, among other things.

SM0, SM1: They determine the framing of data by specifying the number of bits per
character, and the start and stop bits
SM2: This enables the multiprocessing capability of the 8051
REN (receive enable): It is a bit-addressable register. When it is high, it allows 8051 to
receive data on
RxD pin: If low, the receiver is disable.
TI (transmit interrupt): When 8051 finishes the transfer of 8-bit character. It raises TI
flag to indicate that it is ready to transfer another byte.TI bit is raised at the beginning of
the stop bit
RI (receive interrupt): When 8051 receives data serially via RxD, it gets rid of the start
and stop bits and places the byte in SBUF register. It raises the RI flag bit to indicate that
a byte has been received and should be picked up before it is lost. RI is raised halfway
through the stop bit

AT89S51:
The AT89LS51 is a low-voltage, high-performance CMOS 8-bit microcontroller with 4K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard 80C51 instruction set and pin out. The on-chip Flash allows the
program memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with in-system programmable
Flash on a monolithic chip, the Atmel AT89LS51 is a powerful microcontroller which
provides a highly-flexible and cost-effective solution to many embedded control
applications. The AT89LS51 provides the following standard features: 4K bytes of Flash,
128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit
timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-
chip oscillator, and clock circuitry. In addition, the AT89LS51 is designed with static
logic for operation down to zero frequency and supports two software selectable power
saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power-down mode saves
the RAM contents but freezes the oscillator, disabling all other chip functions until the
next external interrupt or hardware reset. Rest all function of this Atmel Series
Microcontroller is same as its other members.

Architecture Features:
• 8-Bit CPU Optimized for Control Applications
• Extensive Boolean Processing Capabilities (Single-Bit Logic)
• On-Chip Flash Program Memory
• On-Chip Data RAM
• Bidirectional and Individually Addressable I/O Lines
• Multiple 16-Bit Timer/Counters
• Full Duplex UART
• Multiple Source/Vector/Priority Interrupt Structure
• On-Chip Clock Oscillator
• On-chip EEPROM (AT89S series)
• SPI Serial Bus Interface (AT89S Series)
• Watchdog Timer (AT89S Series)
AT89C52:
Features
• Compatible with MCS-51™ Products
• 8K Bytes of In-System Reprogrammable Flash Memory
• Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes

Description:
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of Flash programmable and erasable read only memory (PEROM). The device is
manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The
on-chip Flash allows the program memory to be reprogrammed in-system or by a
conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with
Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which
provides a highly-flexible and cost-effective solution to many embedded control
applications.

The AT89C52 provides the following standard features:

8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-
vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89C52 is designed with static logic for operation down
to zero frequency and supports two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt
system to continue functioning. The Power-down mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next hardware reset.
LCD (LIQUID CRYSTAL DISPLAY):

Liquid Crystal Display Fundamentals:

Liquid Crystal Displays (LCDs) are categorized as none missive display devices, in that
respect, they do not produce any form of light like a Cathode Ray Tube (CRT). LCDs
either pass or block light that is reflected from an external light source or provided by a
back/side lighting system. There are two modes of operation for LCDs during the absence
of an electric field (applied Power); a mode describes the transmittance state of the liquid
crystal elements. Normal White mode: the display is white or clear and allows light to
pass through and Normal Black Mode: the display is dark and all light is diffused.
Virtually all displays in production for PC/Workstation use are normal white mode to
optimize contrast and speed.

A simplified description of how a dot matrix LCD display works is as follows: A twisted
nematic (TN) LC display consists of two polarizer, two pieces of glass, some form of
switching element or electrode to define pixels, and driver Integrated Circuits (ICs) to
address the rows and columns of pixels. To define a pixel (or sub pixel element for a
color display), a rectangle is constructed out of Indium Tin Oxide -- a semi-transparent
metal oxide (ITO) and charge is applied to this area in order to change the orientation of
the LC material ( change from a white pixel to a dark pixel). The method utilized to form
a pixel in passive and active matrix displays differs and will be described in later
sections. Figure 1 illustrates a cross sectional view of a simple TN LC display. Figure 2
depicts a dot matrix display as viewed without its metal module/case exposing the IC
drivers.

Looking directly at the display the gate or row drivers are located either on the left or the
right side of the display while the data or column drivers are located on the top (and or
bottom) of the display. New thin display module technology mounts the ICs on
conductive tape that allows them to be folded behind the display further reducing the size
of the finished module. An IC will address a number of rows or columns.
Figure 1: Cross Section of a Simple LC Display
 viewer
///////////////////////////////////// Polarizer
_____________________________________ glass
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Liquid Crystal
_____________________________________ glass
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Polarizer
Backlight

Figure 2: LCD panel and IC driver locations

________________________________________
| |
| IC IC | Source/Column ICs
| | |
| | |
|IC---------------------Pixel |
| |
|IC <---- Gate Line/Row IC |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

* An IC driver will address a number of row/column lines and not just the single pixel in
the diagram above

Polarizers are an integral part of a LCD display, possessing the unique property of only
passing light if it is oriented in a specific (oriented) direction. To utilize this phenomenon
in TN LC displays, the bottom polarizer orients incoming light in one direction. The
oriented light passes through the LC material and is either unaltered or "bent" 90 degrees.
Depending on the orientation of the top polarizer, this light will either pass through or be
diffused. If the light is diffused, it will appear as a dark area. Figure 3 is a simple
illustration of the sequence of events that occur when light passes through a simple
twisted nematic LC display.
Stepper Motor Fundamentals and Details:

Introduction
Stepper motors are commonly used in accurate motion control. They allow to control
any motion with high precision by counting the number of steps applied to the motor.
Most of systems controlling stepper motors are embedded systems such as printer,
scanner or floppy disk drive. This application note describes how to drive a uni-polar
stepper motor with the Programmable Counter Array of an Atmel C51/C251
microcontroller. There are two major types of stepper motors: Permanent magnet stepper
motors (un-polar stepper motors and bipolar stepper motors) and variable reluctance
stepper motors (hybrid stepper motors).

Identification of Stepper Motor

There are several types of stepper motors, these cannot be driven in the same way. In
this application note, we have chosen to drive a uni-polar stepper motor For more
information you will find schemes to identify the other types of stepper motors. Uni-polar
Stepper Motor Uni-polar stepper motors are characterized by their center-tapped
windings.
 Uni-polar Stepper Motor

Bipolar Stepper Motor Bipolar stepper motors are designed with separate coils.
Bipolar Stepper Motor

Variable Reluctance Variable reluctance stepper motor (also called hybrid motors) are
characterized by one common lead.

Variable Reluctance Stepper Motor

Driving Unipolar Stepper Motors
There are three ways to drive unipolar stepper motors (one phase on, two phase on or half
step), each one has some advantages and disadvantages.

There are two stages to sorting out which wire is which in a 5- or 6-wire unipolar stepper motor:

1. Isolate the Common Power wire(s) by using an ohmmeter to check the resistances
between pairs of wires. The Common Power wire will be the one with only half as much
resistance between it and all the others. This is because the Common Power wire only has
one coil between it and each other wire, whereas each of the other wires have two coils
between them. Hence half the resistance.
2. Identify the wires to the coils by supplying a voltage on the Common Power wire(s) and
keeping one of the other wires grounded while grounding each of the remaining three
wires in turn and observing the results. Select one wire and ground it Assume it's
connected to coil 4. Keeping it grounded, ground each of the other three wires one by one
Grounding one wire should make the rotor turn a little clockwise. That'll be the wire
connected to Coil 3. Grounding one wire should make the rotor turn a little anticlockwise.
That'll be the wire connected to Coil 1. Grounding one wire should do nothing That'll be
the wire connected to Coil 2.

Stepper Motor Driver IC ULN2003

Pin Connection:
 CIRCUIT DIAGRAM OF METRO RAIL PROTOTYPE:

LCD is connected with the port 1 of the MC. Control lines are connected with port 3 of the MC. The
contrast of the LCD is controlled by 10k variable resistor.
Unipolar stepper motor is used for running of the train. This motor has five wires, which are connected
as 1a, 1b, 2a, 2b and COM. common line is given at +5v.the other lines can be connected with port of
MC. The stepper motor is derived by the ULN 2003 chip. This chip includes Darlington pair; so that
motor can get enough current for its running .this chip includes pull ups at inputs. Push button is placed
at pin no. 12, whose default state is logic 1 & when switch is pressed then logic 0 is applied on the pin
.this logic 0 causes 8051 to be interrupted.
PCB LAYOUT:
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