Experiment 6.

Delay & Power Characterization of CMOS Combinational

Logic Gates
I. INTRODUCTION
1. Objectives
Characterization of a CMOS inverter in a particular technology and/or design library is a very
important task, because the rest of the complex CMOS circuit designs use an optimized CMOS
inverter as the reference. Once the CMOS inverter is designed, optimized, and fully
characterized using a particular technology node (e.g. 0.35 m), and for a particular
application (e.g. with T=25 C, VDD=5 V, load C=100 pF), an upper bound is determined for
the DC and AC performance for all the other gates that can be designed using that technology
and under the same conditions. The DC voltage characteristics (VTC) of the CMOS inverter
was investigated and compared to a BJT based inverter in the last experiment. In this
experiment, you will first characterize the delay and power dissipation parameters of static
(standard) CMOS inverters in an oscillator. You will then design a complex CMOS gate using
off-the-shelf PMOS/NMOS components.
2. Prerequisites
Before going through preliminary and experimental work sections, it is strongly recommended
that you read and understand CMOS logic gate design, Chapter 7 from Microelectronic
Circuit Design by R. Jaeger and T. Blalock. Other references may also be helpful, such as
Thomas A. Demassa and Zack Ciccone and Adel S. Sedra, Kenneth C. Smith.
II. PRELIMINARY WORK
1. Figure 6.1 depicts an oscillator circuit with an EN (Enable) input. Such circuits are heavily
utilized in modern VLSI chips for many applications such as simple clock generation, time
keeping, process/voltage/temperature tracking. Note there has to be odd number of
inversions in the loop for the circuit to oscillate.

EN

OUT

Figure 6.1. An enabled CMOS oscillator with 5 inversion stages.

a) Given MOSFET parameters VTp= -2 V, VTn= 2 V, Kn=Kp=1 mA/V2, and also assuming a
PMOS+NMOS pair have a total input capacitance of CIN=5 pF, and supply voltage,
VDD=5 V, estimate the frequency of oscillation in this circuit with EN=VDD.

Hint: Use the RC delay estimation model an inverter with non-ideal input i.e. the input
switching is not instantaneous: tpHL=tpLH 2.4RONCL. You may first determine the
effective RON for the NAND gate, with active EN input, and then treat it similar to an
inverter in your calculations.
b) Redo your calculation for VDD=10 V. Comment on the comparison of your results
between (a) and (b).
c) If the leakage through the transistors is negligible in this particular technology, how do
you expect the current dissipation (Iavg) of the oscillator to change with VDD? Estimate

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the current dissipation at VDD=5 V and 10 V.

2. In this section, you will utilize an oscillator built using CD4007 MOSFET simulation model in
order to check your predictions from your calculations in Part 1.
a) Construct the oscillator of Figure 6.1 in LTSPICE using CD4007 MOSFET models in the
APPENDIX. Use a DC voltage source as the power supply, and modify the source model
to have a series resistance of 1 m to make it more realistic.
b) Simulate the oscillator from VDD=5 V to 10 V with 1 V steps (total of 6 corners) with
EN=VDD. At each step, measure the oscillation period (at 50% point between
consecutive rising edges of the output), and obtain the frequency of operation. In
addition, measure the average current dissipation during oscillation.

Power Delivery Note: Observe how the supply current has high frequency
fluctuations due to MOSFET switching in the circuit. You can add a decoupling capacitor
(e.g. 100 F) between VDD and GND in order to reduce such fluctuations. Decoupling
capacitors are essential components of the power delivery in digital circuits to reduce
such current fluctuations, which may result in performance and reliability impacting
voltage overshoots and undershoots respectively due to Ldi/dt events.
c) Fill in the below table based on your formulas derived in Part 1, and simulation results.
Enter the difference between hand calculations and simulations to the last two columns
of the table for oscillator frequency and Iavg.
Hand-Calculations
Simulations
Calc- CalcVDD MOSFET Inverter NAND NAND Oscillator
Sim
Sim
Oscillator
Oscillator
Oscillator
(V)
RON
Freq. Iavg.
tPHL=tPLH tPHL
tPLH
Freq.
Freq.
Iavg. (mA)
Iavg. (mA)
()
Diff. Diff.
(ns)
(ns) (ns)
(MHz)
(MHz)
5
6
7
8
9
10

d) It often provides additional insight to plot parameters against each other. Use MS Excel
or similar tools to plot simulated Iavg. against VDD for example. Do you expect this curve
to be linear? If it is not linear, can you provide any explanations for this? Does the nonlinearity explain the difference between the calculated and simulated current dissipation
values (examine your difference column is it a constant or a growing difference)?

Hint: While CMOS gates switch, both pull-down NMOS and pull-up PMOS network enter
saturation briefly during signal transition when input/output voltage is around VM point.
Although the resulting current (known as short-circuit current) is much less than the
load capacitor charge/discharge current, it still plays a role in dynamic power
dissipation.
Experiment 6

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e) It is often challenging to get a direct measurement of the intrinsic capacitance

associated with MOSFETs, since the transistors are buried into an integrated circuit (IC),
and often do not even have input/output connections to a user visible pin. It helps to
use the device theory in such circumstances to obtain an indirect measurement of the
capacitance. Use the simulated Frequency and Iavg. values in the data table you
derived in Part 2(c) in order to back-calculate the total gate capacitance, Ctotal that is
being charged/discharged in the oscillator design for each VDD setting. Divide Ctotal by
the number of MOSFETs used by your design to obtain a number for average gate
capacitance. Is your extracted value from the simulation consistent with or close to the
datasheet CIN value provided for an NMOS-PMOS pair in Part 1(a)?
f) Use the layout depicted in Figure 6.2 to identify how many of the CD4007 MOS array
chips you will need to design the oscillator in Figure 6.1 in the lab. Sketch as many of
these chips as you need side by side numbering the pins of each as below, and show
how you will wire chip-to-chip interconnects, external EN input, OUT output, and
power supplies in order to build the oscillator on the breadboard. Remember to connect
pin 14 to VDD and pin 7 to GND for each chip you plan to use.

Figure 6.2. Interconnect Layout and Pinout of the CD4007 MOS array chip
3. Design a CMOS complex logic gate that
implements the following logic function based on
the reference CMOS inverter design given on the
right in Figure 6.3, using the graphical method.
The specifications are as following:
i. Logic function: Y (( AB ) ( ACD) ( ACE ))
ii. Graphical Method Approach is a must in
minimizing cost.
iii. Same delay as for reference design inverter
CMOS with loaded capacitance of C.
Hint: Assume symmetrical design based
approach. Also, double check your W/L
calculations for each gate.
Experiment 6

VDD=5 V

Figure 6.3. Reference CMOS Inverter

III. EXPERIMENT
Part 1 Design Validation of a CMOS Oscillator
i.

Build the previously simulated oscillator using your chip layout and interconnect
planning in Part 2(f) of the preliminary work. Add 2 more columns to your data table in
Part 2(c) of the preliminary work, and for each VDD in the table note down the oscillator
frequency measured through the oscilloscope, and the average current dissipation
measured through the ammeter (multimeter). Comment on any differences between
the simulations and the measurements. If you have too much noise on the supply
current or voltage, remember to add decoupling capacitor(s) as described in Part 2(b).

ii.

How do you think the oscillation frequency and power dissipation will change if a 100 pF
additional load is added to the output of each inverter (and the NAND gate) in the
oscillator? Verify your expectation by adding 100 pF to each of the inverter and NAND
output nodes (total of 5 capacitors), and checking the performance and power impact.

Demonstrate your results to your laboratory assistant to get credit for this part.
Part 2 Design Validation of a Complex CMOS Gate
Construct the circuit you have designed in Part 3 of your preliminary work using CD4007
components, referring to Figure 6.2. Investigate the following:
i.

Obtain the truth table of the circuit by applying all input combinations to your circuit
using VDD and input VH (logic 1) level of 5 V. Use input VL (logic 0) level of 0 V. You may
connect LEDs to the inputs and the output of your circuit if it will be easier to execute
and note all combinations.

ii.

Write down the Complex Logic function which you have obtained based on the truth
table from (i). Is it equivalent to the function provided in Preliminary work?

iii.

Determine and note the average propagation delay of the circuit by connecting a 100
pF capacitor at the load.

iv.

In parallel build one reference inverter using CD4007, validate, and note its average
propagation delay under the same VDD and load conditions.

v.

Comment on the difference in results between the complex CMOS gate, and the
reference inverter.

Demonstrate your work to your Laboratory Assistant.

IC LIST FOR EXPERIMENT 5

5 x CD4007

MOSFET Array

6 x LEDs

(Optional)

5 x 100 pF

Capacitors

100 F

Decoupling capacitor

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APPENDIX: LTSPICE device models

.model CD4007nMOS NMOS (LEVEL=1 VTo=1.2 Kp=.9m LAMBDA=0.004)
.model CD4007pMOS PMOS (LEVEL=2 VTo=-1 KP=.62m LAMBDA=0.035)

Experiment 6