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20I4 Power and Energy Systems: Towards Sustainable Energy (PESTSE 2014)

A Cascaded Asymmetric Multilevel Inverter with

Minimum Number of Switches for Solar Applications


Kaustubh P. Draxe, Mahajan Sagar Bhaskar Ranjana, Kiran M. Pandav
M. Tech Students,
Power Electronics and Drives Department,
School of Electrical Engineering,
VIT University, Chennai-600127
draxe.kaustubh@gmail.com, sagar25.mahajan@gmail.com, kiranpandav88@yahoo.co.in

Abstract- Solar energy is one of the renewable energy which

fetched tremendous interests in renewable and power industry.

is used to generate electricity with the help of PV arrays. DC-DC

[n [2]-[3], cascaded multilevel inverter topologies for PV

converter is used to step up the DC voltage from PV arrays and

application are discussed. In [4], Seven-level Grid Connected

then

inverter for photovoltaic system is discussed.

it

is

connected

to

an

inverter

for

AC

applications.

Conventional inverters have many issues like non sinusoidal


output, high total harmonic distortion (THD), high switching
stress and more number of switches. So multilevel inverter (MLI)

Multilevel inverters include diode clamped converter,


flying capacitors, cascaded and H-bridge MLI [5]-[8]. This

have gained much importance over conventional inverters for

MLI help to achieve near sinusoidal output waveforms wih

high voltage and high power applications, due to the increased

reduced THO. As the number of output levels increase,

number of voltage levels producing less number of harmonics. In

harmonics decrease. The disadvantage of conventional MLI is

this paper, a cascaded asymmetric multilevel inverter is proposed

that if more number of output levels are required, then more

which

number of components are needed and due to this complexity

contains

minimum

number

of

switches

and

can

be

employed in AC applications using solar energy. The proposed


topology consists of 25 output levels using 10 switches with near
sinusoidal output, thereby reducing gate driver circuitry and
optimizing circuit layout. Asymmetric multilevel inverter is more
advantageous than symmetric multilevel inverter in obtaining
more number of output levels using same number of voltage
sources. The other advantages of proposed topology are low

increases in gate driver circuits. At present the most famous


hardware implementable topologies are cascaded H-bridge
and the diode clamped [9], [10]. The drawback of symmetric
MLI can be overcome by asymmetric MLI [11]. In this paper
a novel cascaded asymmetric MLI topology is proposed which
requires minimum number of switches with reduced THD.

voltage stress and reduced THD. The THD for proposed inverter

[I.

circuit is only 4.98%. Modeling and simulation is carried out


using MA TLAB/SIMULINK.

Keywords- Renewable Energy; Multilevel Inverter;

The
Total

Harmonic Distortion; Cascaded Asymmetric.

I.

[NTRODUCTION

All nations over the world are engaged in solving the


problem of energy crisis due to the depletion of fossil fuels.
Fossil fuels are non renewable energy sources and their
combustion leads to pollution of environment. This has ignited
the spark of green energy concept with the use of renewable
energy sources. Plenty of researches are being carried out to
harvest the renewable energy. Solar energy is one of the
renewable energy which has wide importance as it is available

BASIC CELL OF PROPOSED MLI

proposed topology contains minimum number of

switches for generating same output levels as compared to


conventional MLI. The proposed MLI's basic cell generates 5
output levels using 2 voltage sources (here the voltage sources
represent stepped up DC-output voltage from PV arrays) and 5
switches

with

anti-parallel

diodes.

Fig.1

shows

arranged same as conventional H-bridge while S15 is added to


increase output level by selecting appropriate voltage source.

vn1

freely and is pollution free. PV arrays trap solar energy and


convert it into electrical energy. The output voltage of PV

SIS

arrays is DC in nature. This output voltage is further stepped


connected to inverters for DC to AC conversion [1]. Earlier 2level inverters were developed but these were not useful for
of harmonics and non sinusoidal output. As the technology got
advanced multilevel inverters were developed which have

978-1-4799-3421-8114/$31.00 2014 IEEE

t-

__

up with the help of high gain DC-DC converters and then

high voltage and high power AC applications due to presence

the

arrangement of these switches, where SII, SI2, SI3, SI4 are

Vll

..._______.&..._...

Fig.1 Basic Cell of proposed MLI

Vout

The TABLE-I is shown below, regarding switching states of

Similarly if voltage sources of P cascaded cells are equal

proposed MLI's basic cell where logic'l' is considered as

to the voltage sources of other basic cells that is in l:1 ratio

'ON' state and logic'0' is considered as'OFF' state of switch.


The basic cell consists of 2 voltage sources.

Vl l= Vl2 = V21= V22= VPI= VP2= Vdc

TABLE-I SWITCHING STATES OF BASIC CELL

S11

S12

S14

S13

SIS

then the arrangement is defined as symmetric MLI.

This arrangement would generate 4P+1 output levels and

Vol (o/p volt.)

value of maximum output voltage level is

Vll+Vl2

Vll

-V12

- (Vll+Vl2)

(4)

2P X Vdc .

When the number of voltage sources in basic cell increase,


then the number of output levels also increase. TABLE-II

L,

illustrates relation between number of voltage sources in the


basic cell and their respective number of output levels with

corresponding number of switches.


T ABLE-II OUTPUT LEVELS FOR RESPECTIVE VOLTAGE SOURCES IN BASIC
CELL
No. of voltage

No. of switches

No. of output

sources

levels

N+3

2N+l

III.

\ l:l l

! I
S15

'II

PROPOSED MULTILEVEL INVERTER

1 __-1_...

The proposed topology of multilevel inverter is employed


by cascaded arrangement of two basic cells. Here the Fig.2

___--a.._-I

Fig.2 Proposed MLI with 10 switches

shows MLI where 25 output levels are obtained by using only


10 switches. This arrangement can be further augmented by
cascading'P' number of basic cells in series. As the number
of output levels is increased the output approaches close to

The diodes are arranged as shown in the Fig.2. Total


number of diodes for one basic cell is 4. So if'P' cascaded
basic cells are used then the total number of diodes required is

sinusoidal waveform. This topology contains two cascaded

given by 4P

basic cells. Each cell consists of two equal voltage sources.

considered). Here in proposed topology total 8 diodes are

The voltage sources of second basic cell are in ratio of l:5

used.

(anti-parallel diodes across switch are not

with respect to voltage sources of first basic cell. This


topology helps to generate 25 output levels. This arrangement
is defined as asymmetric MLI because of unequal voltage
sources in two respective basic cells.

VI I

V l 2 = Vdc

V21

V22

Vp l

OPERATION OF PROPOSED MLI

The operation of the proposed MLI is illustrated from the


switching states in TABLE-III below. The path of current flow

(1)

Vdc

5
=
(P-l)
Vp2
5

IV.

(2)

is shown in Fig.3 and Fig. 4, for positive level and negative


level respectively. Zero output voltage is represented with two
switching states. Switches SIS and S25 are select switches of
two respective basic cells. These switches help to add number
of output levels.

x Vdc

(3)

If 'P' numbers of basic cells are cascaded for this


P
particular topology then the output levels will be 5 and value

( Vdc ) ( 5-5of maximum voltage level is equal to -----(P-l)

When all basic cells are cascaded in series, output voltages


of each basic cell are added together to achieve [mal output
voltage across MLI.

Vout

Val

V02

(5)

TABLE-III SWITCHING STATES OF PROPOSED MLI


LE VE LS
1
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25

SII
0
0
0
0
0
0
0
0
0
I
1
I
1
I
I
1
I
1
0
0
0
0
0
0
0
0

SI2
1
0
1
1
I
1
I
1
1
I
1
I
1
I
I
1
I
1
I
1
1
I
1
I
1
I

SI3
0
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

SI4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

SIS
0
0
0
0
I
1
I
1
1
0
0
0
0
0
0
0
0
0
I
1
1
I
1
0
0
0

S21
0
0
0
1
0
0
0
0
1
0
0
0
0
I
0
0
0
0
I
0
0
0
0
I
0
0

S22
1
0
1
1
0
0
I
1
1
0
0
I
1
I
I
1
0
0
I
1
1
0
0
I
1
I

S23
0
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

S24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

S25
0
0
1
0
0
1
0
1
0
0
1
0
1
0
I
0
I
0
0
1
0
I
0
0
1
0

Output voltage
0
V21
V21+ V22
VII- V21- V22
Vll- V22
VII
Vll+ V21
Vll+ V21 + V22
VII+ V12- V21- V22
Vll+ V12- V22
VII+ VI2
Vll+ V12+ V21
VII+ V12+ V21 + V22
-V22
-V21- V22
V21+ V22- VI2
V21- V1 2
-V12
-V22- V1 2
- V21- V22- V12
V21+ V22- VII- VI2
V21- Vll- V12
- VII- VI2
- V22- Vll- V12
- V21- V22- VII- VI2

",,1
+

0
A

"11.1

Level 6

Level 7

Level 11
Fig.3 Current flow path during positive output levels

Level 8

Level 9

Level 10

Fig.4 Current flow path during negative output levels

V.

SIMULATION RESULTS

The simulation for proposed topology is done using 10


Sll

switches and the voltage sources in second basic cell are equal
to each other but in 1:5 ratios with voltage sources in first
basic cell. FFT window is used for harmonic spectrum
analysis

in

MA TLAB/ SIMULINK.

The

parameters

are:

Vll=V12=120V, V21=V22=24V, frequency=50Hz, R=280,


L=35mH.

; ,-t

II

o L__L-__
m

.
. L-I :-1....I.I _

--'- 0
-- _
---'---

......

-"
----__

----'__
-----'-__"""'----'SH

__

__

;01 III II II HI III

IID:nOD

nUmUB

;BDWDOI liD DID 0 U 0 ill DO I 1:0 DID 01


o

110

0.001

0.004

lime

Fig.6 Switching states of each switch


Fig.5 SIMULINK model of proposed topology

lLOJ
U j'J U,", :
p=f
!

20

200

pq
?U f U Llj UL? j L?U

511

PLf
Sll

0.001

0.1104

0.006

0.008

0.01

0.018

time

Fig.7 Output voltage of second and first basic cells respectively.

rp:EDID

In

5it 0 I 0

P1
U LOJIULOJ 'j

DIDj

01 0 lOP

P g

S25

5ifSP1t5!'
50
0,002

I'r
0,01
0,014

0,004

0,008

0.006

O.ot

iUSJPSR0,02

0,016

0,018

time

Fig.IO Switching stress across each switch

,c1=c1-,-----,--,---,

15

S IgnaI toan."

@ Oisp!irfseleaedsig nal

t) D si play FFT w i!doW


Selecte\lsaI:3cycles.FFT windowrllred):3cycles

15"----O
O.00
O.8--'------'----O.O-'- I'--"----O-'
c 4"c- ----cO.""c----c
.l----c
.
O I80

r\I\!\

100
200

O.Q2'

timt

Fig.8 25- level output waveform MLI using 10 switches for R load

0.01

0.02

0.03

FFTanalysis
Fundamental

15

005

006

(50Hz) 292 , 4.98%

TH

l2.5
2
1.5
i 1
0.5
0 0 J100 1200

Tlme (s)

1,

.1.

Joo

400 500 600 .1, 700 .I. 800 9Il0 ,I,1000

..L

.1

.1.

Frequency {11 z)

Fig.11 FFT analysis of 25 level inverter using 10 switches

Fig.S shows the SIMULINK model of proposed MLI with


10 switches. Switching states of switches, output voltage of
each cell, output waveforms using R-Ioad and RL load,
switching stress across each switch and THD are shown in
time

Fig.6, Fig.7, Fig.8, Fig.9, Fig.! 0 and Fig.11 respectively. The

Fig.9 25-level output waveform MLI using 10 switches for RL load

main advantage is that THD is 4.98% which is less than S %


and output is almost near-sinusoidal waveform.

VI.

CONCLUSION

In this paper, a cascaded multilevel inverter is proposed

[4]

N.A. Rahim, K. Chaniago, and 1. Selvaraj "Single-Phase Seven-Level


Grid Connected Inverter for Photovoltaic System", IEEE Transactions
on Industrial Electronics, Vol. 58, No. 6, June 2011, pp. 2435-2443.

[5]

A Nordvall, "Multilevel Inverter Topology Survey", M.S Thesis in


Electric Power Engineering, Department of Energy and Environment,
Chalmers University Techonology, Goteberg, Sweden, 2011.

[6]

F.Z. Peng, , W. Qian, and D. Cao, "Recent advances in multilevel


converterlinverter topologies and applications," 2010 International
Power Electronics Conference (lPEC), pp.492-501, 21-24, June 2010

[7]

1. Rodriguez, 1.S.Lai, and F.Z. Peng, "Multilevel inverters: A survey of


topologies, controls, and applications," IEEE Trans. on Industrial
electronics, vol. 49, no. 4, pp. 724-738, Aug. 2002.

[8]

Z. Du, I.. M. Tolbert, B. Ozpineci, and K. N. Chiasson, "Fundamental


frequency switching strategies of a seven-level hybrid cascaded H bridge
multilevel inverter," IEEE Trans. Power Electron., vol. 24, Kan. 2009.

[9]

S. Kouro, M.Malinowski, K. Gopakumar, J. Pou,L. Franquelo, B. Wu, J.


Rodriguez, M. Pe' andrez, and 1. Leon, "Recent advances and industrial
applications of multilevel converters," IEEE Transactions on Industrial
Electronics, vol. 57, pp. 2553 -2580, Aug. 2010.

which requires minimum number of switches with increased


output levels where, output waveform is near-sinusoidal.
Compared with conventional multilevel inverters, it requires
less number of components to achieve same number of output
levels. Overall THO is very low and thus the quality of output
waveform is

improved.

Also

this

asymmetric

multilevel

inverter is more advantageous over symmetric multilevel


inverter using same number of switches, for producing more
number of output levels. Due to the use of fewer switches,
optimized circuit layout and packaging is possible. Thus less
cost is required to implement the proposed inverter. When
sinusoidal pulse width modulation

( SPWM) technique is

installed THO value will reduce even further. This topology


can be successfully installed for solar based ac applications.
REFERENCES
[I]

J .Rodriguez, S. Bernet, B. Wu, J.O. Pontt, and S .Kouro, "Multilevel


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pp.2930-2945, Dec. 2007.

[2]

Wei Zhao, Hyuntae Choi, G. Konstantinou, M. Ciobotaru and V. G.


Agelidis "Cascaded H-bridge Multilevel Converter for Large-scale PV
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[3]

S. Rivera, S. Kouro, B. Wu, 1. 1. Leon, 1. Rodriguez and L. G.


Franquelo "Cascaded H-bridge multilevel converter multistring topology
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[10] A Nabae, T. Isao, and A Hirofumi, "A New Neutral-Point-Clamped


PWM Inverter," IEEE Trans. Industry Application, vol. IA-17, NO.5. pp.
518- 523, 1981.
[II] T. Tang, J. Han, I.. Zhou, P. Yao, and X. Tan, "Novel hybrid cascade
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