2012 Asia Pacific Conference on Postgraduate Research

in Microelectronics & Electronics (PRIMEASIA)

126

Design of an Ultra-Low Powered DC-DC Buck

Converter for Wireless Sensor Networks
Soumik Sarkar

Ashis Maity

Amit Patra

Electrical Engineering Department

IIT Kharagpur
Email: ssarkar.ie.iitkgp@gmail.com

Advanced Technology Development Center

IIT Kharagpur
Email: ashis.iit@gmail.com

Electrical Engineering Department

IIT Kharagpur
Email: amit.patra@ieee.org

AbstractWireless sensor networks (WSNs) are normally

installed in remote, inaccessible locations. Energy harvesting
technique is used in such systems which periodically charges
the battery automatically. The life-cycle of such a rechargeable
battery depends on the number of charge/discharge cycles. To
prolong the battery life, an ultra-low powered DC-DC converter,
which interfaces between the battery and the load, is required.
This paper describes an ultra-low powered, switched capacitor
based DC-DC buck converter, in 180 nm standard CMOS
technology, targeted for WSN applications. The input voltage
can vary from 2.1-4.5 V and the output voltage to be regulated
is 1.8 V. The load requires a maximum of 4 mA of load current
for 15 ms of on-time, and thereafter a mere 2 A for 3 minutes
of sleep time. The duty cycle of the clock is typically of the order
of 1:12000 or even more, and the typical average output power is
around 4.2 W. In this design, an ultra low quiescent current of
500 nA for the whole converter is achieved over a desired load
range of 0.002-4 mA. Consequently, the peak power efficiency
has been improved by 20% compared to existing designs.
Also, a unique low power consuming two-phase nonoverlapping clock generation circuit with an adjustable skew
margin is designed. A basic block diagram of this circuit is
described.

I. I NTRODUCTION
Conventionally inductor-based DC-DC buck converters
were used in electronic design. However, the weight, size and
volume of inductors are disadvantages that we must evaluate
before adding them as part of a design. On the other hand,
capacitors do not suffer from the inductors disadvantages.
Switched-Capacitor based buck converters can efficiently convert higher voltage to lower voltages using only switches and
capacitors. Hence these are easily realisable in an integrated
circuit, works well over a wide power range, and have no
inductor losses. This work describes realisation of DC-DC
buck converters using a switched capacitor based approach
for wireless sensor networks which are characterised by ultralow average power requirements and extremely low duty cycle
[6].
A wireless sensor network (WSN) is a wireless network
which consists of spatially distributed autonomous devices that
use sensors to monitor physical or environmental conditions.
The availability of cheap, low power, and miniature embedded
processors, radios, sensors, and actuators, often integrated on
a single chip, is leading to the use of wireless communications
and computing for interacting with the physical world in applications such as security and surveillance applications, smart

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classroom, monitoring of natural habitats and eco-systems,

medical monitoring etc. [7] While energy harvesters and their
power conversion circuits have recently been integrated on
the same die [1], the power harvested is not yet sufficient to
power a 1-10 W sensor node. The power management circuit
must have very low quiescent power and a high efficiency at
low output power levels. In most sensor networks the node
spends most of its time sleeping, thus the sleep power is a
very large portion of the total power budget, and therefore
must be minimized.
DC-DC buck converters for very low power requirement of
power harvesting circuits have been recently developed and
is a major research area. Only recently some buck converters
have come to market that have very low quiescent currents and
can provide high efficiencies at such low load requirements.
For example, the LTC3388 chip from Linear Technology
Corporation is an integrated synchronous step-down regulator
and provides a regulated output while consuming a mere 720
nA of quiescent current for energy harvesting applications [2].
The very low quiescent current allows for high efficiency at
loads as low as 10 A. Another article proposes the design
of a buck regulator using Dynamic Voltage Scaling for a
maximum output current of 50 mA [3]. The no-load current of
the converter is less than 1 A. It gives an expected efficiency
of 60% at output power of 4 W.
Some assumptions about the application are done for the
design. First, it is assumed that frequent changes to supply
voltage is not necessary [3]. Therefore, a large output capacitor
of 100 F is chosen. The output capacitor can be decreased
in size with a slight penalty in efficiency, peak current, ripple
voltage, and faster switching speed.
II. S WITCHED C APACITOR -BASED B UCK C ONVERTER
The overall block diagram of the converter is shown in Fig.
1. Each block is being elaborated in the following subsections.
A. Analysis
Switched capacitor circuits are made of certain established
topologies that exhibit fixed ratios. For a given input voltage,
the open loop output voltage is determined by the ratio of the
topology. Almost all major types and their general ratios are
listed in [5].

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2012 Asia Pacific Conference on Postgraduate Research

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modelled as charge transfers. The SSL impedance is inversely

proportional to switching frequency. The fast switching limit
(FSL) occurs when the resistances associated with switches,
capacitors and interconnect dominate, and the capacitors act
effectively as fixed voltage sources. In the FSL, current flow
occurs in a frequency-independent piecewise constant pattern.
The total output impedance of the converter is a combination
of the two impedance components.

Fig. 1.

Block Diagram of the Switched-Capacitor based Buck Converter

Fig. 2.

The number of ratios for whole input range is determined.

The open loop output voltage that can be obtained by a
topology must be greater than the desired regulation voltage.
Each topology achieves a peak efficiency, when the open
loop output matches with the regulation voltage, and then its
efficiency drops down at higher voltages. So, to keep the range
of efficiency throughout the input range high, the number of
topologies used will have to be increased, and thus the number
of switches and capacitors will rise. So it is a trade-off between
the range of efficiency desired and the amount of hardware
involved. For an input range of 2.1-4.5 V and an output of 1.8
V, the following topologies are decided:
For an input voltage range of 2.1-2.7 V, a 1:1 conversion ratio is decided. The output capacitor is connected
directly to the input via a switch.
For the input voltage range of 2.7-3.6 V, a 3:2 conversion ratio is decided. Only ladder and series-parallel
topologies are considered, as only these two topologies
can be created for a general m:n conversion. For a 3:2
ratio, the series-parallel topology uses 7 switches and 2
capacitors, whereas the ladder topology uses 8 switches
and 5 capacitors. Hence the series-parallel topology is
adopted.
For the input voltage range of 3.6-4.5 V, a 2:1 conversion
ratio is decided. A ladder topology which uses 1 capacitor
and 4 switches is used.
Switched capacitor circuits are characterised by impulsive
charge transfer. This is modelled by considering two extreme
limits and the circuit is assumed to operate in a state which
is a combination of these two extreme limits. According to
the analysis for switched capacitor circuits given in [5], these
asymptotic limits to output impedance are the slow and fast
switching limits. The slow-switching limit (SSL) impedance
is calculated assuming that the switches and all other conductive interconnects are ideal, and that the currents flowing
between input and output sources and capacitors are impulsive,

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Series-Parallel topology with 3:2 conversion ratio

For the 3:2 series-parallel network of Fig. 2 , the charge

multiplier vectors ajc,i , which is the charge flow through
capacitor i during phase j, can be obtained through network
analysis using Kirchoffs Current Law (KCL) and inspection.
In phase 1, charge from input source flows into C1 and C2 ,
and during phase 2, the charge stored in phase 1 is drawn to
the output. The charge flow in each capacitor is found:

T
aj = ajCout ajC1 ajC2 ajCin

T
a1 = 2/3 1/3 1/3 2/3

T
a2 = 1/3 1/3 1/3 0
Thus, the average output impedance for the slow-switching
asymptotic limit is:
P
Pn (aj )2
RSSL = icaps j=1 2Cc,i
= 9f1sw ( C11 + C12 )
i fsw
Similarly, the ajr,i charge multipliers are defined as the
charge flow through switch i during phase j. For each phase
these multipliers can be determined by a linear combination of
the ajc,i charge multipliers. The ajr,i value for switches which
are off is zero. The charge flows in the switches during both
phases are:

T
ajr = ajS1 ajS2 ajS3 ajS4 ajS5 ajS6 ajS7

T
a1r = 1/3 0 1/3 0 1/3 1/3 0

T
a2r = 0 1/3 0 1/3 0 0 1/3
The average output impedance for the fast-switching asymptotic limit is:
P
Pn Ri j 2
RF SL = iswitches j=1 D
(ar,i )
j
where Dj is the ratio of the total switching period occupied
by phase j. Since switched-capacitor circuits use 50 % duty

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cycle clock, Dj = 0.5. Thus, FSL output impedance is:

P
RF SL = 29 iswitches Ri
The simplified circuit model for an SC converter is shown
in Fig. 3. The model uses a single capacitor of value Ceq to
shuttle charge between the input and output ports with a series
resistance Req . The output is modelled as a current source
with bypass capacitance Co . These equivalent component
values can be found in terms of the SSL and FSL output
impedances:

Fig. 3.

Idealized dynamics model for SC system modelling (source:[5])

Ceq =

1
fsw RSSL

Req = RF SL =

=
P
2
9

1
C1

9
+ C1

iswitches

Ri

The discrete time system model using the above parameters

is as follows:
Vout [k + 1] = Vout [k] +

1
Co (iout [k]T [k]

Vout [k])Ceq (1 exp

T
2Req Ceq

+ (nVIN

))

where T is the switching period and n is the conversion

ratio.
The capacitor values and sizes of transistors are needed
to design the converter matrix. To optimize Ci , SSL output
impedance is minimized while constraint on total energy is
kept constant. The analysis gives the following two equations:
P
Etot = i 12 (Vc,i(rated) )2 Ci
qP

Ci =

j
n
2
j=1 (ac,i )

Vc,i(rated)

2Etotq

kcaps Vc,k(rated)

j
2
j=1 (ac,k )

Pn

Using these two equations, the calculated value of C1 =

C2 = 222 nF. Using MATLAB, the discrete time system
model equation and the capacitance values calculated above,
the transistor sizes are decided with the constraints being
Vout [k ] > 1.81 V (not 1.8 V, to create enough margin for
hysteresis controller to operate) and Vin > 2.7 V.
1) A Multi-Stage Model: After seeing the idealized dynamic model, one can deduce that if the number of stages are
increased in parallel, the equivalent resistance (Req ) decreases
and equivalent capacitance (Ceq ) increases, thus reducing
copper loss and also increasing the range of input voltages for
which desired output voltage can be achieved. Hence in this
design, the number of stages has been increased to improve
efficiency. Also the number of stages cannot be increased to
a large number as it would increase the amount of hardware
which would, in turn, draw more current than is needed. Thus,

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an optimum number of stages are used to reduce losses and

increase the overall efficiency.
Switched-capacitor circuits require 50% duty cycle clock.
It is desirable that the clock period be kept high. This is to
reduce the number of switches that the circuit undergoes, and
thus to reduce loss. But it is also necessary that the converter
maintains regulation during swift load switching. The switched
capacitor circuits undergo impulsive charging, hence it should
be ensured that the charge accumulated at the start of the
period is not exhausted before next cycle. But it cant be
ensured that during phase 2 of the period, when the load draws
the stored charge from the capacitors and the power supply
is disconnected, that a high current requirement by the load
is met by the converter. Thus, in case of transients requiring
large currents, there is a chance that the converter may lose
regulation. Hence, to allay this problem in this design, alternate
stages are clocked with out-of-phase clocks, so that at every
time half of the converter is connected to the source.
After a similar analysis for 2:1 converter, the capacitor
and transistor sizes were decided. In order to minimize the
hardware requirements, the same capacitors and transistors are
utilised for realisation of both topologies in a switched capacitor matrix, as shown in subsection E of this section. Hence,
the following values are decided for converter parameters of
the converter:
TABLE I
S WITCHED -C APACITOR BASED B UCK C ONVERTER PARAMETERS

Output Capacitance
Switching Frequency
Duty Cycle
Voltage ripple
Flying Capacitance
Switch Size
No. of Stages

100 F
10 kHz
50%
0.83%
222 nF
900 m/500 nm
4

B. Controller Design
To accomplish the objective of low quiescent current solution to build the DC-DC buck converter, hysteresis controller is
chosen. The conventional hysteresis controller is very simple,
has robust performance with good stability; and is easy to
implement. The greatest benefits of a hysteretic control is that
it offers fast load transient response and eliminates the need
for feedback-loop compensation. Hence power consumption is
minimized.
The basic hysteresis comparator is a three stage comparator
as shown in Fig. 4. The first stage is a differential amplifier
stage. The current mirrors formed by M30 and M26 supplies
the differential pair M27 and M26 with bias current. The
input differential pair is actively loaded by the current mirror
formed by M38 and M39. Since the design demands low
quiescent current, a very low bias current is used to design
the comparator. The bias current is set at 200 nA, so that
sufficient buffer from leakage current is available.

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2012 Asia Pacific Conference on Postgraduate Research

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Fig. 4.

Schematic of the hysteresis comparator

The second stage is actively loaded with the current source

transistor M14 and it acts as a common source amplifier. This
amplifier is commonly used to increase the gain. The third
stage is an inverter stage, which is used to increase the gain
and improve the slew rate at output node.
The transistors M34 and M35 which form a differential
pair are used with positive feedback to add some amount
of hysteresis. The transistors M32 and M33 form a current
mirror which provides the hysteresis current for the differential
pair. The amount of hysteresis can be varied by adjusting the
hysteresis current. The hysteresis current is chosen to be 20
nA. When the variable input voltage is increased, the voltage at
node V 01 increases, the output voltage V out increases and
V 2 begin to decrease. As V out becomes high, transistor
M35 is more on than transistor M34, more current flows
through node V 01 which results in an increase in voltage
at node V 01. This decreases the voltage at node V 2 and
V out increases. This regenerative process goes on till the
output V out saturates in the positive direction i.e. at Vdd.
The same analysis holds true when the variable input starts
to decrease. The output voltage V out saturates in the other
direction i.e. gnd.
Transient analysis is performed on the comparator. The
transient plot is presented in Fig. 5. From the transient plots,
the low-high and high-low propagation delays are measured
as 0.2462 s and 0.09 s respectively.

Fig. 5.

Transient simulation of the comparator

Due to finite delay of the comparator, the amount of

hysteresis obtained depends on the rise time of the chargingdischarging of the output capacitor and hence the output
voltage. If the output voltage rises swiftly within the hysteresis
band, the amount of hysteresis will increase due to delays.
The maximum amount of hysteresis is found to be 25 mV

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for switched capacitor based buck converter which is around

1.4% of the output voltage.
Due to the use of hysteresis controller, the converter operates in burst mode. During the burst-off time, the whole
converter including the clock generation circuit is switched off;
except the controller which continuously monitors the output.
Thus, to improve the performance of the converter in terms of
efficiency, it is very essential that the power consumption of
the controller is reduced. For this design, a 500 nA quiescent
current hysteresis controller is achieved, and is the major factor
in boosting the overall efficiency of the converter.
C. Clock Generation
A large time period also has other advantages in a lowpower design. Less power is consumed in generating a large
time period clock. A major portion of the power consumed in
these systems is due to the short circuit current in a two-phase
clock system. A design margin for eradicating problems due to
clock-skew must be included as shown in Fig. 6. This section
describes a clock generation scheme which not only consumes
low power, but also has a provision for adjusting skew margin
between two-phase non-overlapping clock pulses.

Fig. 6.

Non-overlapping two-phase clocking scheme

The operating frequency for operation is chosen to be 10

kHz. The time period is 100 s. Since the duty cycle is 0.5,
the on-time is 50 s. The duty cycle control unit and a NOR
latch generates a clock with on-time 50 s and off-time 1 s,
as shown in node Clock A of Fig. 7. The significance of this
off-time is that it defines the skew margin between two-phase
non-overlapping clock pulses and is controllable.
Using the four impulse handles in Clock A 1 and Clock
A 2, two non-overlapping clocks are generated as shown in
the scheme shown in Fig. 7. The negative edge-triggered
toggle flip flop generates the select line value of the two
demultiplexers, which effectively puts alternate pulses in its
two outputs. Then one of the outputs of both demultiplexers
are exchanged and are latched to form two non-overlapping
clocks with duty cycle 0.5, skew margin of 1 s and a time
period of 100 s.
A provision is made so that the clock generation circuit
operates only during the burst-on time. Also some of the
components are switched off, when not required. This ensures
optimal utilization of the circuit.
Thus, a larger skew margin is achieved for lesser current
consumed as mostly digital circuits are involved. The current
consumed is lesser than 21 A in burst on time of 15 ms,
which becomes negligible compared to the load current when
averaged over both burst-on and burst-off time of the converter.
Also minor components are added to cater to the short-circuit
loss at the start of burst-on and burst-off times.

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Fig. 7.

130

Clock generation scheme for SC-based buck converter

D. Switching between Topologies

The switched capacitor-based converters have to switch
between various topologies to ensure high efficiency, and also
regulation throughout the input range. As we have decided
above, the topologies with their desired input ranges are given
in Table II.
TABLE II
T OPOLOGY VS I NPUT VOLTAGE RANGE
Fig. 8. Single Stage Switching Capacitor Matrix for SC-based buck converter

Input Voltage Range

2.1-2.7 V
2.7-3.6 V
3.6-4.5 V

Topology
1:1 Switch
3:2 Series-Parallel Topology
2:1 Ladder Topology

TABLE III
S WITCH C ONFIGURATIONS F OR SC M ATRIX OF F IG . 8

Switches
S1
S2
S3
S4
S5
S6
S7
S8
S9

Two control signals are required to control the working

of the matrix containing all the topologies. This is generated using a resistive voltage divider. Also to minimize the
quiescent current, this divider operates only during burston mode, as during burst-off mode, only output capacitor is
discharged. For a perfect division of Vin into 23 Vin and 12 Vin ,
the resistors should be in the ratio 2:1:3. However, the ranges
are overlapped so that there is no anomaly when the converter
operates at the boundary of two topologies, because in such
regions the converter may lose regulation. Hence the ratio is
modified to 2.3:1:3.

3:2
1
2
1
2
1
1
2
-

2:1
1
2
1
1
1
2
2
2

III. S IMULATION

E. Switching Capacitor Network for Converter

The 3:2 and 2:1 topologies are blended in a matrix so that
minimum number of capacitors and switches can be used, as
shown in Fig. 8. The switch configurations are given in Table
III.
The matrix consists of one stage of 3:2 converter and two
stages of 2:1 converter. According to the parameters in Table I,
the number of stages of each topology is 4. Hence two stages
of the matrix in Fig. 8 are used in parallel with two stages
of 3:2 topology in Fig. 2. And the clock signal given to one
stage of each type is out-of-phase to the clock signal given
to the other stage. This ensures that at least half the circuit is
connected to the power supply at any time.

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A. Maximum Load
The maximum load current requirement of the load is 4
mA. At an output current of 4 mA, the results at maximum
and minimum input voltages are presented in Table IV.
B. Idle State
The idle state operation is most important for this application. Since the WSN spends around 3 minutes in idle mode,
the efficiency in this state determines the overall efficiency of
the buck converter. Keeping the output current at 2 A, the
results obtained are tabulated in Table V.

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2012 Asia Pacific Conference on Postgraduate Research

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TABLE IV
M AXIMUM L OAD C ONDITIONS : SC- BASED B UCK C ONVERTER

Parameters
Vout Ripple
Avg. Voltage (Steady State)
Power Efficiency
Average Current
consumed by Clock

Vin : 2.1 V
9.5 mV
1.800 V
85.8%
3.877 A

Vin : 4.5 V
19.56 mV
1.802 V
77.74%
3.264 A

TABLE V
I DLE S TATE O PERATION : SC- BASED B UCK C ONVERTER

Parameters
Vout Ripple
Avg. Voltage (Steady State)
Power Efficiency
Average Current
consumed by Clock
Quiescent current

Vin : 2.1 V
11 mV
1.801 V
66%
2.25 nA

Vin : 4.5 V
23 mV
1.804 V
51.8%
1.8 nA

465 nA

494 nA

nA. The skew margin of about 1 s in the two-phase nonoverlapping clock reduces the short circuit loss significantly
resulting in a high efficiency of the converter. Hence the
digital non-overlapping clock generating circuit used in SCbased converter is indeed instrumental in increasing the skew
margin significantly using very low current. Thus a low-power
non-overlapping clock generation scheme with adjustable skew
margin is developed.
This design exhibits a better performance than many of the
commercial products when used for this application. Table VI
shows a comparison between simulated results of this design
and measured results of LTC3388-1 [2] when used with an
output voltage of 1.8 V and a load current as low as 2 A.
Owing to a very low duty cycle, this efficiency can be taken
as the overall efficiency of the converter for the given load
profile.
TABLE VI
A C OMPARISON OF TWO DESIGNS AT 2 A LOAD

Since the output capacitor used is fairly high enough,

the output voltage can be maintained if the load switches
smoothly. However, when swift variations of load current
occur between minimum load current to maximum load current, the converter has to ensure that the output voltage is
maintained. The output current is switched between 2 A and
4 mA within short intervals of 1 s and simulation results
show that the output is still bounded between the hysteresis
band.
D. Power Efficiency
The efficiency of the SC-based converter varies from 72% to
52%. The efficiency of the SC-based buck converter is plotted
for a load current of 2 A over the whole input voltage range
in Fig. 9. Since the idle time of the load is very high, the
efficiency plot can be taken to be the efficiency of the converter
for the complete load cycle.

Power Efficiency vs Input Voltage for SC-based buck converter

AT

1.8 V

OUTPUT

VOLTAGE

Parameters

C. Load Switching

Fig. 9.

131

Vout Ripple
Power Efficiency
(at Vin = 3 V)
Best Efficiency
Quiescent current
Needs Inductor

This Design
(Simulated)
25 mV (max.)
66%

LTC3388-1 [2]
(Measured)
126 mV (max.)
< 60%

72%
494 nA
No

60%
720 nA
Yes

A lower quiescent current controller can further improve

the efficiency, as the quiescent current consumed by the
switched capacitor topology and the clock generation circuit
is negligible compared to that by the controller.
R EFERENCES
[1] M. Y.Ammar and S.Basrour, Integrated power harvesting system including a mems generator and a power management circuit, Transducers and
Eurosensors, pp. 887890, June 2007.
[2] M. Whitaker, Nanopower buck converter runs on 720 nA, easily fits
into energy harvesting and other low power applications, LT Journal of
Analog Innovation, January 2011.
[3] N. S. S. Balkr and M. W. Hoffman, The design of an ultra-low power
buck regulator supporting dynamic voltage scaling for wireless sensor
networks, ISCAS, 2009.
[4] M. S. Rahman, Buck converter design issues, Masters thesis, Linkping
Institute of Technology, 2007.
[5] M. D. Seeman, A design methodology for switched-capacitor dc-dc
converters, Ph.D. dissertation, University of California, Berkeley, Spring
2009.
[6] Y. Gu and T. He, Data Forwarding in Extremely Low Duty-Cycle Sensor
Networks with Unreliable Communication Links, In SenSys07, 2007.
[7] D. Estrin, A. Sayeed and M. Srivastava, Wireless Sensor Networks,
Tutorial at Mobicom 2002, 2002.
[8] M. Carlson, M. Vesterbacka and W. Kulesza, A non-overlapping twophase clock generator with adjustable duty cycle, Linkping Electronic
Conference Proceedings ISSN 1650-3740, poster Nr. 2, 2003

IV. C ONCLUSIONS
The SC-based buck converter has an ultra low quiescent
current which is less than 500 nA. Also the average current
consumed by the clock generating circuit is less than 3

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