The number of electronic applications using fuzzy logicbased solutions has increased considerably in the last few
years. Concurrently, new CAD tools that explore different implementation technologies for this type of systems have been
developed. Among them, the use of specific processing architectures implemented on FPGAs presents as main advantages a
good "cost-performance" ratio and an acceptably short development time. The different synthesis facilities provided by the
Xfuzzy design environment for the implementation of programmable fuzzy systems, which take advantage of the available
resources in the current FPGAs families, are analyzed in this paper.
RESUMEN
El nmero de aplicaciones electrnicas que utilizan soluciones basadas en lgica difusa se ha incrementado
considerablemente en los ltimos aos y, de forma paralela, se han desarrollado nuevas herramientas de CAD que
contemplan diferentes tcnicas de implementacin para este tipo de sistemas. De entre ellas, el uso de arquitecturas
especficas de procesado implementadas sobre FPGAs presenta como principales ventajas una buena relacin costerendimiento y un ciclo de desarrollo aceptablemente corto. En esta comunicacin se analizan las distintas facilidades de
sntesis que proporciona el entorno de diseo Xfuzzy para la implementacin de sistemas difusos programables que
aprovechen los recursos disponibles en las actuales familias de FPGAs.
(1)
Rule-Select
Input1
MFC
MUX
ci
Input2
Input3
RULE
MFC
MUX
MEMORY
i
MFC
Output
MUX
Counter
Fuzzifier
MIN/Prod
Inference
Defuzzifier
Figura 1: Esquema de evaluacin de reglas activas en sistemas de inferencia basados en lgica difusa.
L1
Label
L2
L1
L4
L2
L3
L5
L1
L2
L3
L5
L6
L7
x1
x2
x3 x4 x 5
x6
x7
L4
Li
Clock
MEM-0
Input
MEM-1
(a)
Count
Not
Reg
i-1
i
(b)
Especificacin XFL
Xfvhdl (Xfuzzy)
Sntesis VHDL
XST (Xilinx)
FC2 /FPGA Exp. (Synopsys)
Sntesis Lgica
ISE (Xilinx)
Implementacin FPGA
entity AntecedentMem is
port( clk : in std_logic;
we : in std_logic;
addr: in std_logic_vector(N-1 downto 0);
di : in std_logic_vector(M-1 downto 0);
do : out std_logic_vector(M-1 downto 0));
end AntecedentMem;
architecture RAM of AntecedentMem is
type ram_type is array (fil-1 downto 0)
of std_logic_vector(M-1 downto 0);
signal RAM: ram_type;
signal read_a: std_logic_vector (N-1 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(addr)) <= di;
end if;
read_a <= addr;
end if;
end process;
do <= RAM(conv_integer(read_a));
end RAM;
Figura 5: Descripcin de MFC implementado mediante
Memoria RAM.
2500
2000
FLCM_RAMB
1500
FLCM_ROM
1000
FLCM_LOGIC
FLCM_RAMD
500
0
600
500
400
FLCA_RAMB
300
FLCA_LOGIC
FLCA_RAMD
200
100
0
5
10
11
12
100%
1400
90%
1200
80%
1000
70%
60%
800
600
FLCM_RAMD
50%
FLCM_RAMB
FLCA_RAMD
40%
FLCA_RAMB
30%
400
20%
200
10%
0%
5
10
500
2000
400
1500
XST (ROM)
1000
XST (LOGIC)
FC2
500
0
7. REFERENCIAS
10
300
XST (LOGIC)
200
FC2
100
0
9 10 11 12
Figura 8: Comparacin del nmero de Slices obtenido por distintas herramientas de sntesis para
MFCs basados en memorias (a) y MFCs aritmticos (b).