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#10: Do not lay the transistors out as they are placed in the schematics
Quite o en you stare a li le bit too much on the schematics when you do your layout. A classical
example is a cascade of dierential ampliers. In the schematics you typically have your dierential
pair, active load, etc., in each sub-amplier. You lay out according to the schematics and you put your
input terminals to the le and your output terminals to the right. Then you start hooking the cascaded
stages up and there it starts to get messed up. You start to cross wires back-and-forth to t the input
to output terminals. It is much be er to rotate the amplier 90 degrees and then put the input
terminals to the le and outputs to the right. Then you can more or less put the stages adjacent and
automatically hook up.
There are more things like this spend some more time on what you actually have in the schematics
and do not follow it too much in detail (from a placement point of view).
#9: Matching
Matching is very important we all know that. Any small variations in transistor sizes might give you
large variations in terms of voltage or current dependent on gain and architecture. So, essentially, this
bullet is stating the obvious do not forget to match your circuit. The question though is how should
you match? We have those well-known interdigitized and common-centroid approaches, where one
interleaves in one or two dimensions in order to spread out the statistical variation to more than one
transistor.
However, what about these things:
avoid metal on top of the gate
orient all transistors (that should be matched) such that the current ows in the same physical
direction
proximity eects, i.e., the edges should also match
shallow trench isolation, i.e., do not put the combined active area edges to far from the gates (that
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regions are mostly windows that are moved around the chip and the physical verication (pv) tool
checks for density in that window. This could have the nasty property that once you are happy with
your density checks in your local sub block, it might turn out that you have too high (or too low)
density once you instantiate your block in the top level design. Annoying, but mostly solveable by
changing the pv deck to have ner stepping between the windows being swept over your design. It
could take slightly more time to run, but denitely quicker than running on the top level.
The tip here is to not be afraid to add ll structures in your subcircuits (as long as you know that you
will not need that space for routing or so). This will further improve matching. Assume, for example,
that you have a time-interleaved ADC where all parallel channels should be matched properly. Here,
you want to add ll structures for each channel rather than adding them on the top level ADC.
#4: Floorplanning do not miss the whole picture
This is of course also well-known, but yet the problem with oorplanning is that mostly not all
people are involved in the oorplanning process. This makes sense too of course, but eventhough you
are only doing one small block in the overall design, maintain a good view of the overall system. How
can your block be done such that the overall design benets from that? For example, by rotating some
components in your block you will help the top-level routing, avoid bends, etc. Remember that the
top-level responsible, in case (s)he is stressed, (s)he will mainly focus on your ports and hook them up
according to instructions. Too o en, Ive seen, for example, bias current wires being routed
back-and-forth since the overall picture has not been considered. This causes extra resistance and
noise.
#3: Think digital
The canyon between analog and digital design seems to become even wider the layout tools are
fundamentally dierent, the design style is fundamentally dierent, the simulators dierent, etc., etc.
So no wonder it is so dicult to interface between them
My message here though is to think digital, at least from a oorplanning and perimeter point-of-view:
Route your wires on digital routing grid
Use same widths for supply wires, and signals on the boundary that needs to interact with digital
core
Make your design as regular as possible, let your (wild) target be to place-and-route your analog
design using a digital back-end tool (!)
Jump back-and-forth between the two dierent worlds to mutually understand the complexities at
both ends. How can an analog macro be inserted (and properly veried) in the digital PNR? How
can a digital macro be inserted (and properly veried) in the analog ow?
#2: Strengthen metal, etc.
You have a couple of dierent bullets (#5 and #7) that motivates this one and maybe one that
contradicts (#6). Anyway, the idea here is that if you have a layout in which you have plenty of routing
that needs to be strengthened, say reducing resistance or so. Spend some hours to develop a script
that enables you to draw the interconnections in say metal 1. Then in cadence virtuoso, at least, you
have a functionality that enables you to do layer manipulations. You could for example create a metal 3
layer which is an xor between metal 1 and metal 2. Using this approach, you can automatically
generate support layers to your existing metal layers. Further on, you can also program the tool to nd
where two metals overlap and automatically insert vias in that region.
#1: Re-use and re-congurability
We slightly touched upon this bullet earlier (rubberband #8). The idea here though is for the wider
scope: how can your circuit be re-used in dierent environments/designs/chips. Still, as outlined in
bullet #4, we must not loose the whole picture, but yet we can probably layout one circuit to be reused
by adding some redundancy. Normally, the area penalty is not that high and the design time you save
could be quite signicant. Chip area can be expensive, but so is lost hours to the market.
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So, same message as I have been mentioning before: think porting. How can you move your design
from one process to another in the shortest possible time? There are some so ware tools out there to
simplify life for you and why not spend some time investigating them?
Any other ideas?
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this is the case. In the analog world, you could think several rails and possibly violate the regularity
a bit. For higher-level integration though, it makes sense to follow some guidelines, such that your
block can easily be hooked up on next level.
For me the tricky things with analog layout is the
mismatch orientation, dummies, etc.
current density considerations in wires for high currents
ESD
isolation, several PSUBs, Taps, etc. require guard rings that occupy space
modularity: analog design typically requires redesign and you want to minimize your layout
eorts. How do you cope with this?
The best book is Practice, practice, practice, by your self
Reply
AfridiTech
2012/03/11 at 10:30
Thanks for the reply jjwikner.
Actually i am implementing a CT 2nd order Delta-Sigma modulator , now the issue is that I have
a lot of mixed signal components, so I cant simply follow the digital design guidelines that is
bu ing a cell to another cell. So the major confusion I am having right now is that should I
design layout cells based on a single function or based on digital or analog functionality. for
example I have a latched comparator (single bit quantizer), which contains a comparator circuit
with a regenerative circuit, and then NAND gates for latched output. So should I design all of
this together in a single cell, or should I treat NAND gate and the comparator completely
separate and then connect them at a higher level.
I hope my question is giving some sense.
jjwikner
2012/03/11 at 11:40
Hi again,
I guess it also depends on the supplies you have at hand. You probably have a low-voltage
analog supply and a low-voltage digital supply at hand. Connecting the analog low-voltage to
the spiky NAND/regen latch could be a bit hazardous. I would suggest thinking three segments:
analog comparator in one island, than the regenerative latch in another connecting to a noisy
analog supply in one island and then the digital part/island coming in. In any case, while
integrating your converter on the top level, you want a solid digital interface, typically inserting
a levelshi er+latch at the boundary between analog and digital.
In general, as mentioned in some of the bullets above, you should think a couple of extra times
on how the signal ow is through your circuit. For example the dierential ampliers, quite
o en, by rotating them 90 degrees solves a lot of problems (this sounds a bit strange, but a bit
o en one startes too much at the schematics when doing the layout.
And dont forget the guard rings as well as isolation between the dierent supplies!
Vikas
2012/08/10 at 07:28
Hi jjwikner,
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