CSE 260 Digital Computers: Organization and Logical Design

Design Problem 2 Solutions

Jon Turner

In this problem, you will use a version of the calculator circuit that uses the S3 boards knob for
input and the LCD display for output. You will find the VHDL for this version of the calculator
on the web site (in the VHDL source area). To get started, create a new project called dp2, copy
all of the provided source files to the project directory and add them all to your project. Note
that the testbench files should be added as simulation only.
The inputMod included in the provided source code uses the knob to control the input value to
the calculator. In this problem, you will be making changes to the inputMod and the
calculator module. First, you are to change the interface to the calculator as specified by the
entity declaration below.
entity calculator is port (
clk: in std_logic;
doit: in std_logic;
op: in std_logic_vector(1 downto 0);
dIn: in word;
result: out word);
end calculator;
The clear, load and add inputs have been replaced with an operation code called op and a
signal called doit. Op specifies which of four operations is to be performed and the operation is
carried out during any clock tick in which doit is high. Specifically, if op=00, the calculator is
cleared, if op=01, a new input value is loaded, if op=10, the input value is added to the stored
value, and if op=11, the input value is subtracted from the stored value. Modify the calculators
architecture to implement this new interface. Be sure to update the comments in the source code
to accurately reflect the new design.
The inputMod interface should also to be changed as indicated by the entity declaration below.
entity inputMod is port (
clk: in std_logic;
-- input signals from buttons and knob on board
btn: in buttons;
knob: in knobSigs;
-- reset signal from btn(0)
reset: out std_logic;
-- inputs to calculator
doit: out std_logic;
op: out std_logic_vector(1 downto 0);
dIn: out word);
end inputMod;
As with the calculator, the clear, load and add signals have been replaced by doit and op.
The inputMod should generate these signals using the knob and buttons. Specifically, when
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btn(3) is held down, turning the knob should cause op to rotate through the four possible
values (the values should increase as the knob turns to the right and decrease as the knob turns
to the left). When btn(3) is not being held down, the knob should control the input value as in
the original version of the circuit. The doit signal should be asserted for one clock tick
whenever btn(2) is pressed down. The reset signal should be generated by btn(0) as in the
original circuit and btn(1) will not be used in the new version.
In addition to modifying inputMod and calculator, you will need to make a few some
changes to top. In particular, you should use the LEDs to display the current operation.
Specifically, when the operation is clear, led(7) should be turned on (and the others off), when
the operation is load, led(6) should be turned on, when the operation is add, led(5) should be
turned on and when the operation is subtract, led(4) should be turned on. You will also need to
modify the wiring of the various components within top.
You should modify the standalone testbench for the calculator circuit (called
testCalculator.vhd) to use the new interface and to exercise all the operations, including
the new subtraction operation. You will also simulate the entire circuit using the provided
testbench called testAll.vhd. Once you are satisfied that your circuit works correctly in
simulation, you should also implement the design on an S3 board in the Urbauer lab and verify
that it works correctly.
Here is what you should turn in. Please include every part, and in the order listed below.
A printed copy of the VHDL for all the circuit components that you modified
(calculator, inputMod, top). Your changes should be highlighted so that they are easy
to identify and the comments in the source code should be updated to accurately reflect the
new design. Your work will be evaluated on the correctness of your VHDL, the readability
of the source code and your comments. This part is worth 25 points.
A printed copy of your modified version of testCalculator.vhd (with appropriate
comments). Your work will be evaluated on the thoroughness of your testbench and your
comments. This part is worth 10 points.
A printed copy of the simulation output from your version of testCalculator.vhd,
with written comments pointing out how the simulation output demonstrates the correct
operation of the circuit at each step. If, for any reason, your circuit does not work correctly,
note that in your comments and explain what you did to try to correct the problem. Your
work will be evaluated on the correctness of the simulation output, the formatting and
organization of the simulation output and your written comments. This part is worth 10
points.
A printed copy of the output from your simulation run using the testbench testAll, with
comments pointing out how the simulation output demonstrates the correct operation of
the circuit at each step. Note that for this part, you must NOT modify the testbench. If, for
any reason, your circuit does not work correctly, note that in your comments and explain
what you did to try to correct the problem. Your work will be evaluated on the correctness
of the simulation output, the formatting and organization of the simulation output and
your written comments. This part is worth 15 points.

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There are two more requirements for this assignment.

You must demonstrate to one of the TAs that the circuit works correctly on the S3 board.
When you have done so, the TA will initial your paper and check your name off on a check
list. Your work will be evaluated on your ability to transfer the circuit to the S3 board and
the correct operation of the circuit. This part is worth 15 points.
Send an email to jon.turner@wustl.edu with a separate attachment for each of the four
source code files (calculator, inputMod, top, testCalculator). Your work will be
evaluated on your ability to follow directions. If this part is not done, 20 points will be
deducted from your total.

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Here is the modified source code for calculator.

------------------------------------------------------------------------- Simple Binary Calculator
-- Jon Turner, 12/2007
-- modified 5/2010 for newer prototype boards

-- modified 9/2010 to add subtract operation and new interface

--- This circuit implements a simple binary calculator with four
-- operations: clear, load, add and subtract.
--- The inputs to the calculator include a signal doit, which
-- causes an operation to be performed. The specific operation
-- that is performed is specified by the op input.
--if op=00, the calculator's stored value is cleared
-if op=01, the input value is stored in the calculator
-if op=10, the input value is added to the stored value
-if op=11, the input value is subtracted from stored value
--- The circuit operates on words, where the size of a word is
-- defined in commonDefs. The circuit does not require any
-- specific word size.
-----------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.commonDefs.all;
entity calculator is port (
clk: in std_logic;

doit: in std_logic;
-- perform operation now
op: in std_logic_vector(1 downto 0); -- selected operation
dIn: in word;
result: out word);
end calculator;

-- input data
-- output result

architecture a1 of calculator is
signal dReg: word;
begin
process (clk) begin
if rising_edge(clk) then

if doit = '1' then

case op is
when "00" => dReg
when "01" => dReg
when "10" => dReg
when "11" => dReg
when others =>
end case;

<=
<=
<=
<=

(others => '0');

dIn;
dReg + dIn;
dReg - dIn;

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end if;
end if;
end process;
result <= dReg;
end a1;

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Here is the modified source code for inputMod.

----------------------------------------------------------------------- Input module for calculator
-- Jon turner 8/2010
-- Modified 9/2010 to implement new interface
--- Converts button and knob signals into input signals needed
-- to drive simple calculator circuit.
--

-- The output doit is asserted for one clock tick by each press
-- of btn(2). The output op specifies one of four operations.
-- It is controlled by the knob when btn(3) is held down.
---------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.commonDefs.all;
entity inputMod is port (
clk: in std_logic;
-- input signals from buttons and knob on board
btn: in buttons;
knob: in knobSigs;
-- reset signal from btn(0)
reset: out std_logic;
-- inputs to calculator
doit: out std_logic;
op: out std_logic_vector(1 downto 0);
dIn: out word);
end inputMod;
architecture a1 of inputMod is
component debouncer ... end component;
component knobIntf ... end component;
-- current and previous debounced button signals
signal dBtn, prevDB: buttons;
-- debounced knob signals
signal dKnob: knobSigs;
-- outputs from knob interface
signal tick, clockwise : std_logic;
signal delta, knobVal: word;

-- signals controlling op output

signal operation: std_logic_vector(1 downto 0);
signal opSelect: std_logic;
begin
db1: debouncer generic map(width => 4) port map(clk, btn, dBtn);
db2: debouncer generic map(width => 3) port map(clk, knob, dKnob);
-- generate signals from debounced buttons
process (clk) begin

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if rising_edge(clk) then prevDB <= dBtn; end if;

end process;
reset <= dBtn(0);

opSelect <= dBtn(3);

doit <= reset or (dBtn(2) and (not prevDB(2)));
ki: knobIntf port map(clk, dBtn(0), dKnob, tick, clockwise, delta);
process(clk) begin
if rising_edge(clk) then
if dBtn(0) = '1' then -- on reset
knobVal <= (others => '0');

operation <= "00";

else
if tick = '1' then

if opSelect = '0' then -- update knobVal

if clockwise = '1' then
knobVal <= knobVal + delta;
else
knobVal <= knobVal - delta;
end if;
else -- update operation to be performed
if clockwise = '1' then
operation <= operation +1;
else
operation <= operation -1;
end if;
end if;
end if;
end if;
end if;
end process;
dIn <= knobVal;

op <= 00 when reset = 1 else operation;

end a1;

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Here is the modified source code for top.

---------------------------------------------------------------- Top module for calculator
-- Jon Turner - 5/2010

-- modified 9/2010 by Jon Turner

--- External connections include buttons, knob, switches and
-- LCD control signals.
--- The switches are not used here but are included in
-- the interface to support extensions to the calculator.
--- This version uses the knob on the S3 board to control
-- both the input value to the calculator and the operation
-- to be performed. The calculator supports four operations,
-- clear, load, add and subtract.
--- Internal components include the calculator core,
-- an inputModule that uses the knob to control the input
-- data to the calculator and a display module that uses
-- the LCD display to show the input to the calculator and
-- the result output from the calculator.
---------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.commonDefs.all;
entity top is port(
clk: in std_logic;
-- buttons and knob, switches and LEDs
btn: in buttons;
knob: in knobSigs;
swt : in switches;
led : out leds;
-- external signals to display
lcd: out lcdSigs);
end top;
architecture a1 of top is
component calculator ... end component;
component inputMod
... end component;
component displayMod ... end component;
signal reset: std_logic;

-- doit causes calculator to do the operation specified by op

signal doit: std_logic;
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signal op: std_logic_vector(1 downto 0);

signal dIn, result: word;
begin
-- connect all the sub-components

imod: inputMod port map(clk, btn, knob, reset, doit, op, dIn);
calc: calculator port map(clk, doit, op, dIn, result);
disp: displayMod port map(clk, reset, dIn, result, lcd);

-- display selected
with op select
led <= "10000000"
"01000000"
"00100000"
"00010000"

operation on LEDs
when
when
when
when

"00",
"01",
"10",
others;

end a1;

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Here is the source code for testCalculator.

-------------------------------------------------------- Testbench for calculator module
-- Jon Turner, 12/2007
-- modified 5/2010 for 16 bits

-- modified 9/2010 to use coded operation input

-------------------------------------------------------use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.commonDefs.all;
entity testCalculator is
end testCalculator;
architecture a1 of testCalculator is
component calculator port(
clk: in std_logic;

doit: in std_logic;
op: in std_logic_vector(1 downto 0);

dIn: in word;
result: out word);
end component;
signal clk:

std_logic := '0';

signal doit: std_logic := '0';

signal op: std_logic_vector(1 downto 0) := "00";
signal dIn: word := (others=>'0');
signal result: word;

begin
-- create instance of calculator circuit
uut: calculator port map(clk, doit,

op, dIn, result);

process begin -- clock process

clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
process begin

doit
doit
doit
doit
doit
doit
doit
doit
doit
doit
doit
doit
doit
doit

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

'1';
'0';
'1';
'0';
'1';
'0';
'1';
'0';
'1';
'0';
'1';
'0';
'1';
'0';

op <= "00";
wait for 20
op <= "01";
wait for 20
op <= "10";
wait for 20
op <= "10";
wait for 20
op <= "10";
wait for 20
op <= "10";
wait for 20
op <= "11";
wait for 20

dIn
ns;
dIn
ns;
dIn
ns;
dIn
ns;
dIn
ns;
dIn
ns;
dIn
ns;

- 10 -

<= x"ffff"; wait for 20 ns;

<= x"0001"; wait for 20 ns;
<= x"0001"; wait for 20 ns;
<= x"0002"; wait for 20 ns;
<= x"0003"; wait for 20 ns;
<= x"0004"; wait for 20 ns;
<= x"0003"; wait for 20 ns;

doit
doit
doit
doit
doit
doit
doit
doit

<=
<=
<=
<=
<=
<=
<=
<=

'1';
'0';
'1';
'0';
'1';
'0';
'1';
'0';

op <= "11";
wait for 20
op <= "11";
wait for 20
op <= "11";
wait for 20
op <= "00";
wait for 20

dIn
ns;
dIn
ns;
dIn
ns;
dIn
ns;

<= x"0004"; wait for 20 ns;

<= x"0005"; wait for 20 ns;
<= x"0006"; wait for 20 ns;
<= x"ffff"; wait for 20 ns;

assert (false) report "Simulation ended normally." severity failure;

end process;
end a1

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The simulation results for the run using testCalculator appear below. Note that the op signal near the
center determines the operation to be performed. We start with a clear and a load, which both work
correctly. This is followed by and several add operations, which all produce the correct sums, then a
sequence of subtract operations, which also produce the correct results. Another clear operation is
performed at the end of the sequence.

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The first part of the simulation results for the complete circuit appears below. The doit signal is activated
whenever btn(2) is pressed. The first time this happens, op=00 and a clear operation is performed. This is
also reflected in the LED value at the bottom of the window. The knob rotation then causes op to become
1, and then causes din to be incremented, so that when the next operation (a load) is performed, the value
1 is loaded into the calculator.

The middle section of the simulation appears below. This part shows several addition operations, all of
which produce the correct result. Also note that the LEDs display 20, which is what we expect for the
addition operation.

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The final section of the simulation appears below. This part has several subtract operations, all of which
produce the correct result. The LEDs also show 10, which is what we expect for the subtraction operation.
The simulation ends with a clear operation which does properly clear the result.

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