ABSTRACT

JPEG2000 has recently been approved as a new international standard of still image
compression. The standard provides a rich feature set including support for both lossy and
lossless image coding. One of core technologies employed by JPEG2000 codec is the Wavelet
Transform. In order to build a high-quality JPEG2000 encoder or decoder, one must be able to
construct an effective wavelet transform engine. VLSI Architecture is used to implement the
Discrete Wavelet Transform for multimedia image storage and retrieval. Lossy is usually
required in the multimedia field. The DWT represents the signal in dynamic sub-band
decomposition. The specific decomposition will be selected according to an optimization
criterion. The Discrete Wavelet Transform (DWT), based on time-scale representation, provides
efficient multi-resolution sub-band decomposition of signals. It has become a powerful tool for
signal processing and finds numerous applications in various fields such as audio compression,
pattern recognition, texture discrimination, computer graphics etc. Specifically the 2-D DWT and
its counterpart 2-D Inverse DWT (IDWT) play a significant role in many image/video coding
applications. Image compression has become important as storage or transmission of images
requires large amount of bandwidth. In order to minimize the complexity of DWT, fuzzy
technique has been proposed and implemented on FPGA. In recent years, many researchers have
applied the fuzzy logic to develop new techniques for contrast improvement. Fuzzy logic is a
well-known rather simple approach with good visual results, but proposed fuzzy operation
algorithm is default nonlinear. This approach is useful to improve the system performance by
taking advantage of available look up tables, routing resources and shift registers available on
target device. The proposed fuzzy algorithm is synthesized with Xilinx ISE 10.1 and
implemented on Virtex II Pro based xc2vp30-7-FF896 FPGA device. Results show better
performance of proposed design in terms of area utilization, memory requirements, and speed,
power consumptions.

TABLE OF CONTENTS
ABSTRACT

TABLE OF CONTENTS

ii

LIST OF FIGURES

iii

LIST OF TABLES

1. INTRODUCTION

1.1 Digital image compression

1.2 Image compression

1.2.1 Lossy compression techniques

1.2.2 Lossless compression techniques

1.3 Fuzzy domain

1.4 Objective

13

1.5 Methodology

13

1.6 Organization of the project

14

2. LITERATURE SURVEY

15

2.1 Motivation

21

3. DESIGN AND IMPLEMENTATION

22

3.1 Image

23

3.2 Xilinx core generator

25

3.3 Fuzzy Intensification operator

27

3.4 Discrete Wavelet Transform

29

3.5 Inverse Discrete Wavelet Transform

32

3.6 Virtex 2 pro

36

4. RESULT AND DISCUSSIONS

40

4.1 RTL Schematic

46

4.2 Display output

48

CONCLUSION AND FUTURE SCOPE

49

REFERENCES

50
ii

LIST OF FIGURES

Figure 1.1: Digital Image

Figure 1.2: The Block Diagram of the General Image Storage System.

Figure 1.3: Image Compression System.

Figure 1.4: Lossy Image Compression.

Figure 1.5: Examples of Membership Function.

Figure 1.6: Membership Function of the Term Set Age.

Figure 1.7: Rules of Fuzzy Reasoning.

10

Figure 1.8: Fuzzy Inference System.

11

Figure 1.9: Membership Function Modification.

11

Figure 1.10: Fuzzy Image Processing.

12

Figure 3.1: Proposed Block Diagram.

22

Figure 3.2: Flow of Design.

23

Figure 3.3: Resize the Image (100x100).

24

Figure 3.4: Snapshot of Type of Memory Select.

27

Figure 3.5: Intensification Set Operator.

28

Figure 3.6: Fuzzy Intensification Operator.

28

Figure 3.7: Image Coding.

30

Figure 3.8: DWT Architecture.

30

Figure 3.9: Dividing Even and Odd Pixels.

31

Figure 3.10: Filtering and Downsampling.

31

Figure 3.11: Example of Decimator by 2.

32

Figure 3.12: 2-Level of Decomposition.

32

Figure 3.13: Fuzzy D-Flip Flop.

33
iii

Figure 3.14: Block Diagram of 2-D IDWT.

34

Figure 3.15: Illustration of 2-D DWT for Image Lena.jpg

36

Figure 3.16: XC2VP3O Virtex 2 Pro Module.

37

Figure 3.17: Flow of Compression and Decompression Process.

39

Figure 4.1: Simulate in ISIM.

40

Figure 4.2: Synthesizing Blocks.

41

Figure 4.3: ISE Synthesis for Prototype Implementation.

42

Figure 4.4: RTL Schematic of Fuzzification and De-Fuzzification.

46

Figure 4.5: RTL Schematic of DWT.

46

Figure 4.6: RTL Schematic of IDWT.

47

Figure 4.7: RTL Schematic of DWT and IDWT.

47

Figure 4.8: Original Image and Reconstructed Image.

48

iv

LIST OF TABLES

Table 4.1: FPGA Resource Specifications for Various Families.

41

Table 4.3.1: Design summary.

43

Table 4.3.2: Timing Constraint.

44

Table 4.3.3: Clock Report.

45

Table 4.3.4: X-power Analyzer.

45