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Computer Architecture

Topics:
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Processor Design

Where are we now?

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C-Programming
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Data Representation
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Very limited programming model

Digital Logic
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Everything goes down to bits and bytes

Machine representation Language

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A real computer language

Transistors g Gates g Circuits

Circuits g { Memory, Registers, and
Components}

What are we going to do now.

Processor Design
Figure out how a small subset of the
instruction set works in hardware
l Use Hardware blocks to describe data path
l Use control logic to ensure steps of the
instruction flows smoothly
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Add instruction
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Type of add depends on where operands are

located
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add reg1, reg2

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add $constant, reg2

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Add contents of reg1 to reg2 and store result in reg2

Add contents of memory immediately following the
instruction to reg 2 and store result in reg2

add (effective-address), reg2

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Add contents of effective address to reg2 and store

result in reg2
Effective address could be relative; relative + offset;
relative + offset, index; relative + offset, index*scaled

Instruction Example
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Generic Form!
Addition Instruction
Encoded Representation!
addl %edx, %eax!

Add value in register %edx to that in register %eax

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0 3 rA! rB!

Store result in register %eax

Two-byte encoding
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First indicates instruction type

Second gives source and destination registers

ADD-Add : note src, dst are

reversed in the intel manual

In assembly language add src, dst means src + dst dst

Instruction Example in x86

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Generic Form!
Addition Instruction
Encoded Representation!
addl %edx, %eax!

Opcode is 03 and src, dst are %edx, %eax

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0 3 C! 2!

from previous table (Table 2.2) code is C2

8(%ebp),
%eax!
So, 03 C2 means add addl
%edx,
%eax
03 45
means add 8(%ebp), %eax
addl $4, %eax!
05
add $cons, %eax

0 3 4 5

0 5 000

Arithmetic and Logical

Operations
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Function Code!

Instruction Code!
Subtract (rA from rB)!
subl rA, rB!

2 B rA! rB!

And!
andl rA, rB!

2 3 rA! rB!

Exclusive-Or!
xorl rA, rB!

The second byte will

vary based on type of
operands
Set condition codes
as side effect

3 3 rA! rB!

Lower 4 bits can vary depending upon the type

Of operand

20 means 8 byte register transfer,

Lower 4 bits can vary

30 means 8 byte register transfer,

Subtract operationInstruction Set Reference

Single cycle stages

Fetch Instruction (IF)
l Decode Instruction (ID)
l Execute Instruction (EX)
l Memory access (MEM)
l Write back (WB)
l Update Program Counter (PC)
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Building Blocks
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fun"
A"

Combinational Logic
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Compute Boolean
functions of inputs
Continuously respond to
input changes
Operate on data and
implement control

A"
L"
U"

B"

A"
MUX"
B"

="

S

B

valA"
srcA"

Storage Elements
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valW"

Register"
file"

valB"
srcB"

A"

Store bits
Addressable memories
Non-addressable registers

B"

W"

dstW"

Clock"

Clock!

Fetch Instruction
+"

+4"

PC

IR

Fetch Instruction and increment Program counter

A"
L"
U"

Add instruction (add %edx,

%eax)
+"

IR

%edx

Register file

%eax

Op code determines type of operation

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A"
L"
U"

03 C2

Operands are in registers

They are fed to the adder (ALU)
Result stored back in register
Based On Instruction the signal to ALU can be +, -, * or /

Add instruction (add $4,

%eax)
+!

IR

%eax

Register file

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A"
L"
U"

Op code is determines type of operation

03 05
One Operand is a register, the other is part of the instruction
%eax, immediate value
They are fed to the adder (ALU)
Result stored back in register

mov instruction (mov 8(%ebp),

%eax)
Data

mem

+"

IR

%ebp

Register file

A"
L"
U"

address

%eax

data

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Op code is determines type of operation

8b 45
Load word from memory onto register %eax
Address is 8 + (%ebp)

R/W

mov instruction (mov %eax,

8(%ebp))
Data

mem

+"

IR

%ebp

Register file

A"
L"
U"

address

%eax

data

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Op code determines type of operation

89 45
Store word from register %eax onto memory
Address is 8 + (%ebp)

R/W

SEQ Hardware
Structure
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State
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Program counter register (PC)

Condition code register (CC)
Register File
Memories
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Access same memory space

Data: for reading/writing program
data
Instruction: for reading instructions

Instruction Flow
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Read instruction at address

specified by PC
Process through stages
Update program counter

newPC

PC!

!! !

valE , valM

Write back!

valM

!
!

Data
Data
memory
memory

Memory!

! !

Addr, Data

valE

CC!
! CC
aluA!, a!luB!

Execute!

ALU
ALU

Bch

!! !

valA , valB

!! !
!! !

! ! !!
! !

srcA , srcB
dstA , dstB

Decode!

Register
RegisterM
file
file
E

, !! !!

icode! ifun
rA! , rB
valC

Fetch!

valP

!
!
!

Instruction
Instruction
memory
memory

PC

!
!

PC
PC
increment
increment

newPC

SEQ Stages
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Fetch
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valM

!
!

Data
Data
memory
memory

Memory!

! !

Addr, Data

valE

CC!
! CC
aluA!, a!luB!

Execute!

Read or write data

!! !

valA , valB

! ! !!
! !

Register
RegisterM
file
file
E

Write program registers

Update program counter

!! !
!! !

srcA , srcB
dstA , dstB

Decode!
, !! !!

icode!ifun
rA! , rB
valC

PC
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ALU
ALU

Bch

Compute value or address

Write Back
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Write back!

Memory
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Read program registers

Execute
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!! !

valE , valM

Decode
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Read instruction from instruction

memory

PC!

Fetch!

valP

!
!
!

Instruction
Instruction
memory
memory

PC

!
!

PC
PC
increment
increment

Instruction Decoding
Optional!
5

0 rA" rB"

Optional!
D"

icode!
ifun!
rA!
rB!
valC!

Instruction Format
l Instruction

byte
icode:ifun
l Optional register byte
rA:rB
l Optional constant word
valC

Executing Arith./Logical
OperationOPl rA, rB! 6 rA! rB!
fn"

Fetch
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Read 2 bytes

Decode
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Perform operation
Set condition codes

Memory
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Read operand registers

Execute
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Write back
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Do nothing
Update register

PC Update
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Increment PC by 2

Stage Computation: Arith/

Log. Ops
OPl rA, rB!

Fetch!

Decode!
Execute!
Memory!
Write!

icode:ifun M1[PC]!

Read instruction byte!

rA:rB M1[PC+1]!

Read register byte!

valP PC+2!

Compute next PC!

valA R[rA]!

Read operand A!

valB R[rB]!

Read operand B!

valE valB OP valA!

Perform ALU operation!

Set CC!

Set condition code register!

R[rB] valE!
!
back!
PC update! PC valP!

!
Write back result!
!
Update PC!

Formulate instruction execution as sequence of

simple steps
Use same general form for all instructions

Executing popl
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Fetch
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8 F rA! 8
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Read 2 bytes

Decode
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popl rA!

Read stack pointer

Increment stack pointer by 4

Read from old stack pointer

Write back
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Execute
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Memory

Update stack pointer

Write result to register

PC Update
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Increment PC by 2

POP Instruction

Stage Computation: popl

popl rA!

Fetch!

Decode!
Execute!
Memory!

icode:ifun M1[PC]!

Read instruction byte!

rA:rB M1[PC+1]!

Read register byte!

valP PC+2!

Compute next PC!

valA %esp!

Read stack pointer!

valB %esp!

Read stack pointer!

valE valB + 4!

Increment stack pointer!

valM M4[valA]!

Read from stack !

Write!

R[%esp] valE!
R[rA] valM!
back!
PC update! PC valP!
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Use ALU to increment stack pointer

Must update two registers
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Popped value
New stack pointer

Update stack pointer!

Write back result!
Update PC!

Executing Jumps

fall thru:!

XX XX

Not taken!

target:!

XX XX

Taken!

Read 5 bytes
Increment PC by 5

Decode
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7 fn"

Fetch
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jXX Dest!

Do nothing

Execute
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Determine whether to take

branch based on jump
condition and condition codes

Dest"

Memory
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Write back
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Do nothing
Do nothing

PC Update
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Set PC to Dest if branch

taken or to incremented PC if
not branch

Stage Computation: Jumps

jXX Dest!

Fetch!

icode:ifun M1[PC]!

Read instruction byte!

valC M4[PC+1]!

Read destination address!

valP PC+5!

Fall through address!

Bch Cond(CC,ifun)!

Take branch?!

Decode!
Execute!
Memory!
Write!

!
back!
PC update! PC Bch ? valC : valP!

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!
!
Update PC!

Compute both addresses

Choose based on setting of condition codes and
branch condition

Executing call
call Dest!

XX XX

target:!

XX XX

Decrement stack pointer by 4

Dest"

Memory
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Read stack pointer

Execute
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Read 5 bytes
Increment PC by 5

Decode
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return:!

Fetch
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E 8

Write back
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Write incremented PC to new

value of stack pointer
Update stack pointer

PC Update
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Set PC to Dest

Stage Computation: call

call Dest!

Fetch!

Decode!
Execute!
Memory!
Write!

icode:ifun M1[PC]!

Read instruction byte!

valC M4[PC+1]!

Read destination address !

valP PC+5!

Compute return point!

valB R[%esp]!

Read stack pointer!

valE valB + 4!

Decrement stack pointer!

M4[valE] valP !

Write return value on stack !

R[%esp] valE!
!
back!
PC update! PC valC!

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Update stack pointer!

!
Set PC to destination!

Use ALU to decrement stack pointer

Store incremented PC

Call Opcodes in X86

Executing ret
C 3

ret!
return:!
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Fetch
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Read 1 byte
Read stack pointer

Execute
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Increment stack pointer by 4

Memory
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Decode
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XX XX

Write back
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Read return address from old

stack pointer
Update stack pointer

PC Update
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Set PC to return address

Stage Computation: ret

ret

Fetch!

Decode!
Execute!
Memory!
Write!

icode:ifun M1[PC]!

Read instruction byte!

valA R[%esp]!

Read operand stack pointer!

valB R[%esp]!

Read operand stack pointer!

valE valB + 4!

Increment stack pointer!

valM M4[valA] !

Read return address!

R[%esp] valE!
!
back!
PC update! PC valM!

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Update stack pointer!

!
Set PC to return address!

Use ALU to increment stack pointer

Read return address from memory