Winter 2005
Placement
Website: http:/ / vlsicad.ucsd.edu/ courses/ ece260bw05
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IO Pad Placement
Power/ Ground
Stripes, Rings Routing
Global
Placement
Detail Placement
Global Routing
Extraction and
Delay Calc.
Timing
Verification
Detail Routing
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Placement Problem
Input:
A set of cells and their complete information (a cell library).
Connectivity information between cells (netlist information).
Output:
A set of locations on the chip: one location for each cell.
Goal:
The cells are placed to produce a routable chip that meets timing
and other constraints (e.g., low-power, noise, etc.)
Challenge:
The number of cells in a design is very large (> 1 million).
The timing constraints are very tight.
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B C
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To spread ...
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.. or not to spread
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or to the right
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B C
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Placement Problem
A bad placement
A good placement
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In global placement, we
decide the approximate
locations for cells by placing
cells in global bins.
Global Placement
Detailed Placement
In detailed placement, we
make some local adjustment
to obtain the final nonoverlapping placement.
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Placement Footprints:
Standard Cell:
Data Path:
IP - Floorplanning
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Placement Footprints:
Core
Reserved areas
IO
Control
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Placement Footprints:
Perimeter IO
Area IO
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Standard Cells
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Standard Cells
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Unconstrained
Placement
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Floor planned
Placement
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Placement Cube
2x2, 4x4, .
Algorithm
tG
s
i
tl
e
N
ity
r
a
ul
n
ra
ars
ene
ss
Co
Lay
out
(4D)
Cost Function
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Advantages of Hierarchy
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Disadvantages of Hierarchy
Results depend on the quality of the hierarchy. The logic hierarchy must be
designed with Physical Design taken into account.
Additional methodology requirements must be met to enable hierarchy. Ex.
Pin assignment, Macro abstract management, area budgeting, floor
planning, timing budgets, etc
Late design changes may affect multiple components.
Hierarchy allows divergent methodologies
Hierarchy hinders Design Automation algorithms. They can no longer
perform global optimizations.
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Algorithm
ist
l
t
Ne
ity
r
a
ul
n
a
Gr
Co
Quadratic Placement
Simulated Annealing
Bi-Partitioning / Quadrisection
Force Directed Placement
Hybrid
Lay
out
ars
ene
ss
Cost Function
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Quadratic Placement
Analytical Technique
x3
A =
2 -1
-1 2
Ax = B
x4 F/ x2 = 0;
B =
x3
x4
x=
x1
x2
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Analytical Placement
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Cons:
Can Generate Overlapped Solutions: Postprocessing Needed
Not Suitable for Timing Driven Placement
Not Suitable for Simultaneous Optimization of Other Aspects of
Physical Design (clocks, crosstalk)
Gives Trivial Solutions without Pads (and close to trivial with
pads)
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Cost
Time
ECE260B CSE241A Placement.27
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Cons:
Extremely Slow Process of Reaching a Good Solution
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Bi-Partitioning/ Quadrisection
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Cons:
Not Well Understood
Lots of indifferent moves
May not work well with some cost functions.
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Variants
directed/undirected hypergraphs
weighted/unweighted vertices, edges
constraints, objectives,
Human-designed instances
Benchmarks
up to 4,000,000 vertices
sparse (vertex degree 4, hyperedge size 4)
small number of very large hyperedges
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etc
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Speed
Structure
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Pass:
FM:
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Cut
Moves
ECE260B CSE241A Placement.36
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Multilevel Partitioning
Clustering
ECE260B CSE241A Placement.37
Refinement
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Fij
j
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Cons:
Not sensitive to the non-overlapping constraints
Gives Trivial Solutions without Pads
Not Suitable for Timing Driven Placement
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Hybrid Placement
Mix-matching different placement algorithms
Effective algorithms are always hybrid
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min { x i x j 2 }
min { y i y j 2 }
Partition
and Replace
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Congestion Minimization
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Definition of Congestion
Routing demand = 3
Assume routing supply is 1,
overflow = 3 - 1 = 2 on this edge.
Overflow =
overflow
all edges
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Wirelength Congestion
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Congestion
MAP
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Prediction
What is prediction ?
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Paradigms of Prediction
statistical prediction
constructive prediction
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Co
Lay
out
ist
l
t
ity
r
Ne
a
ul
n
a
Gr
Algorithm
Net-cut
Linear wirelength
Quadratic wirelength
Congestion
Timing
Coupling
Other performance related
cost functions
Undiscovered: crossing
ars
ene
ss
Cost
Function
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1
2
(x2,y2)
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1
2
(x2,y2)
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Congestion Cost
Routing demand = 3
Assume routing supply is 1,
overflow = 3 - 1 = 2 on this edge.
Congestion Overflow =
overflow
all edges
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Wirelength Congestion
A congestion minimized
placement
A wirelength minimized
placement
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Bin Nodes
Cell Nodes
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Net-centric Heuristic
1
2
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Congestion
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Solution Space
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Timing Cost
Critical
Path
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Timing Analysis
22
3
L
A
T
C
H
19
4
2
1
L
A
T
C
H
4
1
4
3
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Approaches
Budgeting
Path Analysis
In accurate information
Fast
Most accurate information
Very slow
Somewhere in between
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Timing Metrics
How do we assess the change in a delay due to a
potential move during physical design?
Whether it is channel routing or area routing, the
problem is the same
translate geometrical change into delay change
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Coupling Solutions
Noisy region
Extra space
Grounded Shields
Quiet region
Segregation
Spacing
Shielding
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Netlist Granularity:
Problem Size and Solution Space Size
Algorithm
Co
Lay
out
ist ity
l
t
r
Ne ula
an
r
G
ars
ene
ss
Cost Function
ECE260B CSE241A Placement.84
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Layout Coarsening
GP, DP (Twolf)
2x1, 2x2, .
ity
r
a
ul
n
parts
ra
G
ist
l
t
Ne
Algorithm
Lay
out
Co
ars
ene
ss
Cost Function
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Incremental Placement
Given an optimal placement for a given netlist, how to
construct optimal placements for netlists modified from
the given netlist.
Very little research in this area.
Different type of incremental changes (in one region, or all
over)
Methods to use
How global should the method be
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Incremental Placement
A placement move changes the interconnect
capacitance and resistance of the associated net
A net topology approximation is required to estimate
these changes
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Placynthesis Algorithms
resizing
cloning
buffering
restructuring
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6
5
1.5
Vdd
Vt
4
power
3
2
0.5
1
0
0
1997 1999 2002 2005 2008 2011
1997
1999
2002
2005
2011
Source: The Incredible Shrinking Transistor, Yuan Taur, T. J. Watson Research Center, IBM, IEEE Spectrum, July 1999
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feedthrough
VL
VH
GND
VL
IN
OUT
GND
Layout Structure
ECE260B CSE241A Placement.90
Placement References
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