ARTICLE IN PRESS

Microelectronics Journal 40 (2009) 197201

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

New implementation of high linear LNA using derivative

superposition method$
Shuguang Han a, Baoyong Chi b,, Zhihua Wang b
a
b

Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

Institute of Microelectronics, Tsinghua University, Beijing 100084, China

a r t i c l e in fo

abstract

Article history:
Received 4 October 2007
Received in revised form
16 September 2008
Accepted 16 September 2008
Available online 20 November 2008

New implementation of a high linear low-noise amplier (LNA) using the improved derivative
superposition (DS) method is proposed. The input stage is formed by two transistors connected in
parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the
moderate inversion region instead of the weak inversion region, thus allowing a feasible source
degeneration inductance at the sources of the two transistors to achieve a good input impedance
matching and low noise gure (NF) while keeping high third-order input intercept point (IIP3)
improvement with the DS method. The new implementation has been used in a 0.18-mm CMOS high
linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB
NF and 7.5 mA at 1.8 V power consumption.
& 2008 Elsevier Ltd. All rights reserved.

Keywords:
Low-noise amplier (LNA)
RF
CMOS
Inter-modulation distortion
Derivative superposition (DS)
Third-order input intercept point (IIP3)

1. Introduction
Linearity is a key performance parameter for RF circuits since
nonlinearity may cause harmonic generation, gain compression,
desensitization, blocking, cross modulation and inter-modulation
distortion, and many other problems. For the low-noise amplier
(LNA), high linearity should be achieved without lowering other
performances, such as low noise gure (NF), high gain, good
impedance matching and low power consumption. The linearity
of the LNA is usually specied as an input-referred third-order
intercept point (IIP3). Many RF systems demand higher than
+8 dBm IIP3 LNAs while keeping the other performance
satised [1]. Considering that the power supply has been
lowered along with the scaling down of the feature size in the
CMOS process, the high IIP3 requirement is a big design challenge
and many linearization techniques are proposed to solve
the problem.
The derivative superposition (DS) method [24], which falls
under the category of feed forward, is one of the various
linearization techniques. It uses two transistors connected in
parallel and biased in the weak inversion region and in the strong

$
This work was supported in part by the National Natural Science Foundation of
China (No. 90407006) and the Fok Ying Tung Education Foundation (No. 104028).
 Corresponding author. Tel.: +86 10 62795096; fax: +86 10 62795104.
E-mail address: chibylxc@tsinghua.edu.cn (B. Chi).

0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2008.09.007

inversion region, respectively. The sizes and bias voltages of the

two transistors are chosen such that the positive peak of the thirdorder nonlinear coefcient of the weak inversion transistor is
aligned with the negative peak of that of the strong inversion
transistor. This results in an extended linear range over which the
third-order nonlinear coefcient is close to zero. However, the IIP3
improvement using this method is only modest at RF (3 dB, as
reported in [3]). Ref. [4] boosts IIP3 in the DS method by 10 dB by
reducing the source degeneration inductance and using the
cascode technique to reduce the drain load impedance. However,
as reported in [1], for feasible values of the source degeneration
inductance, which is limited by the downbond inductance
(40.5 nH), the conventional DS method provides no IIP3 improvement at all. But, with a very small source degeneration
inductance, it is difcult to simultaneously achieve a good input
impedance matching and low NF. Although the modied DS
method [1] or new circuit topology [5] is proposed to boost IIP3,
they need two source degeneration inductors and complicate the
circuit design.
In this paper, new implementation of a high linear LNA
using the improved DS method is proposed. The input
stage is formed by two transistors connected in parallel.
One transistor is biased in the strong inversion region and
another one is biased in the moderate inversion region,
thus allowing a feasible source degeneration inductance at the
sources of the two transistors while keeping high IIP3 improvement with the DS method. The new implementation has been

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S. Han et al. / Microelectronics Journal 40 (2009) 197201

used in a 0.18-mm CMOS high linear LNA. The measured results

verify the feasibility of the proposed implementation in improving
IIP3 of the LNA.

2. Circuit description
Fig. 1 shows the principle of the DS method [24]. Two
transistors are connected in parallel and their sources are
degenerated by the same inductance L. One transistor, MA, works
in the strong inversion region as usual and another one, MB, works
in the moderate inversion region instead of the weak inversion
region. Fig. 2 shows the DC IV curve of the transistors, the
vertical axis is ln(ID) and sqrt(ID), respectively. The DC IV curve
could be divided into three regions: weak inversion, moderate
inversion and strong inversion. The transistor shows different
IV characteristics in different regions. The IV curve in the weak
inversion region shows exponential characteristics, while the
IV curve in the strong inversion region shows square-law
characteristics. The transition region between these two regions
is the so-called moderate inversion region. From Fig. 2, it could be
seen that the transistor works in the moderate inversion region
when VGS is between 0.3 and 0.5 V.
Fig. 3 shows the third-order nonlinear coefcient G3A and G3B
of MA and MB versus the voltage source VGS. By setting the
voltage source VBD to 0.3 V, MA is designed to work in the strong
inversion region and MB is designed to work in the moderate

Fig. 1. Principle of the DS method.

inversion region. G3 is dened as

3

G3

1 q ID
6 qV 3GS

and controls the third-order inter-modulation distortion (IMD3)

at low signal levels, thus determines IIP3. It could be seen that the
third-order nonlinear coefcient G3A of the transistor in the strong
inversion region is negative and the third-order nonlinear
coefcient G3B of the transistor in the moderate inversion region
is positive. The negative G3A is aligned with the positive G3B, but
they have a similar mirror-image curvature, the resulting
composite G3 will be close to zero and the theoretical IIP3
will be signicantly improved in a relatively wide range of the
gate biases.
Fig. 4 shows the schematic of the whole LNA. The input stage is
the same with Fig. 1, only the ESD protection circuit and the gate
series inductance are added. The gate series inductance is to
resonate with the gate-source capacitance of the input transistors
to provide a real resistance for the input impedance matching
purpose. MA and MB are biased by the off-chip bias voltages, VA
and VB, to work in the strong inversion region and the moderate
inversion region, respectively, so that their third-order nonlinear
coefcients G3A and G3B reach the negative peak and positive
peak. MA and MB could also be biased on-chip with a welldesigned bias circuit. Since Fig. 3 shows that the theoretical IIP3
will be signicantly improved in a relatively wide range of gate
biases (about 70 mV), the accuracy requirements on VA and VB are
not high, so it should not be very challenging to design the onchip bias circuit. In our work, the off-chip biases are applied for
the prototyping purpose.

Fig. 3. The third-order nonlinear coefcient G3A and G3B of MA and MB versus the
voltage source VGS.

Fig. 2. The DC IV curve of the transistors, the vertical axis is ln(ID) and sqrt(ID).

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S. Han et al. / Microelectronics Journal 40 (2009) 197201

After the biases VA and VB are xed, the size of MA is chosen

based on the normal noise/power optimization procedure of the
inductance source-degenerated common-source LNA. Then the
size of MB is adjusted to make the composite G3 close to zero in a
relatively wide range of gate biases.
The cascode transistor is added to reduce the drain load
impedance of the composite input transistors at the second
harmonic frequency, so that the effect of the second-order
harmonic response on IIP3 is reduced to a great extent [4].
Another goal is to improve the isolation between the input and
output of the LNA.
On-chip inductance Ld is resonated with the output node
parasitic capacitance and on-chip capacitance Cd to provide the
load for the LNA and also provide the output impedance matching.
The source degeneration inductance, provided by the bondwire, is about 1.6 nH to generate a real resistance at the input of
the LNA, thus allowing simultaneously the input impedance
matching and the noise matching. This inductance requirement is
feasible for the normal package. So the low source degeneration
inductance requirement in Ref. [4] has been cancelled by making
one of the parallel transistors work in the moderate inversion
region instead of the weak inversion region.

199

3. Simulated results
The LNA has been implemented in the 0.18-mm CMOS process.
Fig. 5 gives out the simulated S-parameters with Agilent ADS
when VA 0.77 V and VB 0.47 V. The gure shows that the
LNA has achieved good input impedance matching and output

Fig. 6. The simulated stability factor k of the LNA as well as D factor.

Fig. 4. Schematic of the whole LNA using the DS method.

Fig. 5. The simulated S parameters with Agilent ADS when VA 0.77 V and VB 0.47 V.

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S. Han et al. / Microelectronics Journal 40 (2009) 197201

impedance matching with a 1.3 GHz operating frequency, and it

could provide 12.3 dB power gain and 21.7 dB reverse isolation.
Since MB works in the moderate inversion region, the gate voltage

variation of MB has little effects on the S-parameter performance

of the LNA.
Fig. 6 gives out the simulated stability factor k of the LNA as
well as D factor (D |S11S22S12S21|). It could be seen that k is
greater than 1 and D factor is smaller than 1, so the LNA is
unconditionally stable.
Fig. 7 gives out the simulated effective small-signal transconductance Gm of the LNA and the contribution of MA and MB. Gm is
mainly dependent on MA, and MB has little contribution to Gm
since MB works in the moderate inversion region. Here VGS is
the gate voltage of MA, and the gate voltage of MB is lower than
VGS by 0.3 V.

4. Measured results

Fig. 7. The simulated effective small-signal transconductance Gm of the LNA and

the contribution of MA and MB.

Fig. 8. The microphotograph of the presented LNA.

The LNA has been implemented in the 0.18-mm CMOS process.

Fig. 8 shows its microphotograph. The die area is about 0.6 mm2,
most of which is occupied by the on-chip inductance, PADs and
ESD protection circuits. The bare die is directly bondwired into a
PCB and all the measured results are calibrated with another
identical PCB without the die bondwired.
The measurements show that the power gain of the
1.35 GHz LNA is about 9.36 dB with an NF of 2.25 dB. Fig. 9
shows the measured power gain and NF versus frequency with
an Agilent noise gure analyzer. The gain is lower than the
simulated |S21| by about 3 dB and NF is higher than the simulated
one by about 1.2 dB. The reason may be due to the inaccuracy in
RF component models and the package parasitic effects which
could not be predicted correctly since our package is completed
by hand.
Two-tone test is used to obtain the IIP3 of the LNA. Two RF
tones located in 1.35 GHz750 kHz are input into the LNA, and the
two tones have the same power. Fig. 10 gives the measured IIP3 of
the LNA at different gate voltages VB of MB, here the gate voltage
VA of MA is xed at 0.767 V. It could be seen that the IIP3 of the
LNA achieves the highest value (11.92 dBm) when MB works in the
moderate inversion region, which is much higher than the case
when MB works in the weak inversion region and in the strong
inversion region. Consider that the power supply of the LNA is
only 1.8 V, and the IIP3 of 11.92 dBm is very superior.

Fig. 9. The measured power gain and NF versus frequency with an Agilent noise gure analyzer.

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S. Han et al. / Microelectronics Journal 40 (2009) 197201

60

VB = 0.281 V

VB = 0.467 V
50
40
30
20
10
0
IIP3 = 11.92 dBm
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-25 -20 -15 -10 -5 0 5 10 15 20
Pin (dBm)

20
IIP3 = 4.17 dBm

-20

Pout (dBm)

Pout (dBm)

40

-40
-60
-80
-25 -20 -15 -10 -5 0 5
Pin (dBm)

201

10 15 20

VB = 0.767 V

80
60
Pout (dBm)

40
20
0

IIP3 = 2.84 dBm

-20
-40
-60
-80
-25 -20 -15 -10 -5 0 5
Pin (dBm)

10 15 20

Fig. 10. The measured IIP3 of the LNA (VA 0.767 V).
Table 1
Comparison of state-of-the-art highly linear CMOS LNA
Work

Technology (mm)

Freq. (GHz)

Power gain (dB)

NF (dB)

IIP3 (dBm)

PDC (mA atV)

FOM

[1]
[6]
[4]
[7]
[5]
[8]
This work

0.25
0.25
0.35
0.35
0.35
0.18
0.18

0.9
2.2
0.9
0.9
0.9
2
1.35

15.5
14.9
10
2.5
1*
6.7*
9.36

1.65
3
2.85
2.8
2.95
1.4
2.25

+22
+16.1
+15.6
+18
+21
+13.3
+11.92

9.3 at2.6
9.4 at 2.5
7.82 at 2.7
15 at 3
9 at 2.5
8 at 1.8
7.5 at 1.8

452.8
118.4
17.1
2.5
4.1
34.9
19.8

Note: * means that the gain is deduced from the IIP3 measured gures.

The LNA draws 7.5 mA current from a 1.8 V power supply. If we

dene the gure of merit (FOM) of the LNA as follows:
FOM

Gain  IIP3 mW  f GHz

F  1  PDC mW

where F is the noise factor; a summary of the measured results of

the LNA is provided in Table 1 along with a comparison with the
state-of-the-art high linear CMOS LNA.

5. Conclusion
New implementation of a high linear LNA using the conventional
DS method is proposed. By making one transistor work in the
moderate inversion region instead of the weak inversion region, a
feasible source degeneration inductance is allowed to achieve a
good input impedance matching and low NF while keeping high
IIP3 improvement with the DS method. The LNA has been
implemented in the 0.18-mm CMOS process and the measured
results verify the feasibility of the proposed implementation.

References
[1] V. Aparin, L.E. Larson, Modied derivative superposition method for linearizing
FET low-noise ampliers, IEEE Trans. Microwave Theory Tech. 53 (2) (2005)
571581.
[2] D. Webster, J. Scott, D. Haigh, Control of circuit distortion by the derivative
superposition method, IEEE Microwave Guided Wave Lett. 6 (3) (1996)
123125.
[3] B. Kim, J.-S. Ko, K. Lee, A new linearization technique for MOSFET RF amplier
using multiple gated transistors, IEEE Microwave Guided Wave Lett. 10 (9)
(2000) 371373.
[4] T.W. Kim, B. Kim, K. Lee, Highly linear receiver front-end adopting MOSFET
transconductance linearization by multiple gated transistors, IEEE J. SolidState Circuits 39 (1) (2004) 223229.
[5] S. Ganesan, E. Sanchez-Sinencio, J. Silva-Martinez, A highly linear
low-noise amplier, IEEE Trans. Microwave Theory Tech. 54 (12) (2006)
40794085.
[6] Y.-S. Youn, J.-H. Chang, K.-J. Lee, et al., A 2 GHz 16 dBm IIP3 low noise amplier
in 0.25 mm CMOS technology, IEEE Int. Solid-State Circuits Conf. (2003)
452453.
[7] Y. Ding, R. Harjani, A +18 dBm IIP3 LNA in 0.35 mm CMOS, IEEE Int. Solid-State
Circuits Conf. (2001) 162163.
[8] T.S. Kim, B.S. Kim, Post-linearization of cascode CMOS low noise amplier
using folded PMOS IMD sinker, IEEE Trans. Microwave Wireless Components
Lett. 16 (4) (2006) 182184.