A UNIFIED POWER QUALITY CONDITIONER WITH VOLTAGE SAG/SWELL
COMPENSATION CAPABILITY
Maurício Aredes and Rodrigo M. Fernandes
UFRJ – Federal University of Rio de Janeiro
COPPE – Electrical Engineering Program
LEMT – Laboratory for Power Electronics and Medium Voltage Applications
www.lemt.ufrj.br; aredes@ufrj.br; rodrigo@eneltec.com.br
Abstract: Traditionally, Unified Power Quality Condi-
tioners (UPQCs) are designed for simultaneous compen-
sation of voltage and current harmonics and imbalances.
Moreover, the shunt active filter of the UPQC behaves as
a controlled current source to compensate the load cur-
rent, whereas the series active filter behaves as a con-
trolled voltage source to compensate the supply voltage.
Here, a dual configuration of UPQC, denominated as the
iUPQC, is presented. In contrast to the conventional
UPQC, the shunt active filter of the iUPQC behaves as an
ideal ac voltage source and the series one as an ideal ac
current source. One negative aspect in the conventional
approach of UPQC is the voltage and current PWM con-
trols of the power converters. The PWM controls must
deal with nonsinusoidal compensating voltage and cur-
rent references, with aleatory frequency spectra. In this
case, it is impossible to theoretically unsure zero steady-
state error in all frequencies components. Contrarily, the
iUPQC has a fundamental positive-sequence current ref-
erence for the series active filter and a fundamental posi-
tive-sequence voltage reference for the shunt active filter.
Beside all those compensation characteristics of the
UPQC, the iUPQC can also keep the load voltage con-
stant, at the nominal value. In other words, it has voltage
sag/swell compensation capability, with fast response,
comparable to that of a Dynamic Voltage Restorer
(DVR). Simulation and experimental results are pre-
sented to validate the proposed iUPQC controller.
Keywords – active filters, p-q theory, power quality,
unified power quality conditioners
I. INTRODUCTION
S IMULTANEOUS active filtering of grid voltage and
load current is becoming a real issue due to the actual
tendencies to restrict standards and grid codes from the har-
monic pollution point of view. On the other hand, the indus-
try and other sectors are employing an increasing number of
sensitive loads that requires high quality of electric power
supply [1]. Voltage sags and voltage swells cause serious
losses in the manufacture processes.
The Unified Power Quality Conditioner (UPQC) is a flexi-
ble approach for simultaneously active filtering the supply
voltage and the load current [2] to [7]. In other words, the
UPQC protects critical loads against voltage disturbance
propagating through the power system, and compensates the
current of these protected loads to ensure sinusoidal and ba-
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lanced current drained from the network.
Usually, the series active filter of a UPQC is used for
compensating the supply voltage, whereas the shunt one is
used for compensating the load current [4]. Therefore, the
series active filter behaves as a controlled voltage source and
the shunt active filter behaves as a controlled current source,
as shown in Fig. 1. Therefore, the conventional approach of
UPQC (Fig. 1) is controlled by nonsinusoidal voltage ( vC* )
and current ( iC* ) references.
The compensating voltage reference will comprises a fun-
damental component, if the UPQC controller is designed for
compensating voltage sag/swell or voltage imbalances, as
well as all harmonic components in the supply voltage vS
within a given frequency range to be compensated. On the
other hand, the compensating current reference comprises a
fundamental component to compensate the power factor of
the load and all harmonic currents of the nonlinear load.
This aleatory multiple-frequency characteristic of the voltage
and current references makes the design of the controls and
converters of the active filters very difficult. Actually, in a
practical implementation, the performance of the UPQC is
degenerated by the limited capability of the PWM controls to
track accurately their nonsinusoidal references.
To overcome the above mentioned drawbacks of the con-
ventional UPQC, this paper presents a dual approach, called
here as iUPQC. The idea consists in having both the series
and the shunt converter of the iUPQC being controlled as a
sinusoidal current source and as a sinusoidal voltage source,
respectively. This idea is not new. It was originally proposed
by Moran, in 1989 [8]. In that work, a single-phase universal
power conditioner based on current-sourced converters
(CSC) was proposed. Later, three-phase voltage-sourced
vC
iS iL
iC
L L
vS C vL
Vdc
vf PWM
voltage
vC* iC* PWM if
current
control control
vS
UPQC iL
iS controller
Fig. 1. Conventional arrangement of a Unified Power Quality
Conditioner (UPQC).
218

vL iS
vS
ϕ iC
vC iL
iS
iS
iC
vS iUPQC
vL vL
Fig. 2. The dual principle of Unified Power Quality Conditioner:
the iUPQC.
converters (VSC), in a similar configuration as the UPQC
shown in Fig. 1, were applied in UPS systems, but also hav-
ing the series converter as a controlled current source and the
shunt converter as a controlled voltage source [9][10].
Fig. 2 shows the principles of the iUPQC. The shunt ac-
tive filter generates a fundamental positive-sequence voltage
at nominal value. Thus, the compensated load is supplied
under regulated, sinusoidal and balanced voltage conditions
(vL). On the other hand, the series active filter imposes a
fundamental positive-sequence current (iS) to be drained
from the network. In steady state, the series active filter
drains a positive-sequence current in phase with the funda-
mental positive-sequence component of the supply voltage
vS. The magnitude of iS correspond to the average active
power demanded by the load, plus an active current compo-
nent to compensate for losses inside the iUPQC.
Since the shunt active filter of the iUPQC behaves as an
ideal positive-sequence voltage source, it offers ideally null
impedance for harmonic currents, whereas the series active
filter offers ideally infinite impedance. Hence, all harmonic
currents injected by the nonlinear load will be forced to flow
into the shunt active filter of the iUPQC. In other words, the
shunt converter of the iUPQC behaves also as an active filter
(iC) for the load current. Additionally, the shunt active filter
supplies also the reactive power of the load, since the series
active filter drains only the corresponding active portion (iS)
of the load current.
All voltage disturbances that may propagate in the power
system, including voltage sags or swells, harmonics and im-
balances, which may affect the supply voltage vS will remain
as a voltage drop across the terminals of the series active fil-
ter (vC = vL – vS), because the load voltage vL comprises only
a fundamental positive-sequence component, imposed by the
shunt active filter.
II. POWER CIRCUIT OF THE iUPQC
The power circuit of the iUPQC is the same of a conven-
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iL vC
iS iL
L L
vS C vL
Vdc
if vf
PWM i+1 v +1 PWM
current voltage
harmonic control control
sensitive
loads vS iUPQC iL
controller
Fig. 3. Power circuit of the iUPQC.
tional UPQC. Fig. 3 shows the power circuit and the voltag-
es and currents measurements that are needed as input sig-
nals in the iUPQC controller. The iUPQC is composed of
two PWM converters connected back-to-back through a
common dc link. Three single-phase transformers are em-
ployed to insert the series converter between the power sys-
tem and the load. The convenience of using or not shunt
transformer is more related to economical issues regarding
voltage/current levels and power ratings of the system and
power converters of the iUPQC.
The main difference between the UPQC (Fig. 1) and the
iUPQC (Fig. 3) consists in replacing the nonsinusoidal vol-
tage PWM control by a sinusoidal current PWM control in
the series converter, and replacing the nonsinusoidal current
PWM control by a sinusoidal voltage PWM control in the
shunt converter.
If compared with the conventional UPQC (Fig. 1), the
iUPQC (Fig. 3) has a simpler controller and reduced number
of measurements. Only the system voltage, the dc-link vol-
tage and the load current are necessary as inputs to the
iUPQC controller. The other two measurements, the shunt-
converter voltage (vf) and the series-converter current (if) are
used in the minor feedback loops of the PWM controls.
Since the series converter behaves as a controlled current
source that drains a fundamental positive-sequence current
(i+1) in phase with the supply voltage vS, it provides high im-
pedance for the harmonic currents of the nonlinear load. The
compensating voltage vC that appears across the series trans-
formers corresponds to the difference between the load vol-
tage vL, imposed by the shunt converter, and the supply vol-
tage vS. Since vL corresponds to a fundamental positive-
sequence voltage reference v+1, all voltage imbalance, vol-
tage sags or swells, as well as voltage harmonics that may
appear in vS are compensated by vC. The shunt converter of
the iUPQC provides low impedance for harmonic currents
coming from the nonlinear load, and adjusts the magnitude of
the load voltage vL, as well as supplies the fundamental reac-
tive current of the load (power factor compensation). Note
that the current reference i+1 of the series converter is in
phase with the fundamental positive-sequence component
V+1 of the supply voltage vS.
219
 Shunt active
filter control
v Sab vSα vα′
PLL
abc → αβ
v Sbc circuit
vS β vβ′
Synchronizing control
iS α
iLa
abc → αβ
p-q
Series active iLb Theory
iS β
filter control
_ Fig. 5 shows the voltage PWM control used in the shunt
v dc
dc-link voltage
regulator
Fig. 4. Basic control block diagram of the iUPQC controller.
III. THE iUPQC CONTROLLER
The controller of the iUPQC is very simple. It is based on
the p-q Theory [11]. A fundamental part of this controller is
the synchronizing control circuit based on a Phase Locked-
Loop (PLL), which tracks accurately the frequency and
phase angle of the fundamental positive-sequence component
of the supply voltage vS. Fig. 4 shows the complete control
block diagram of the iUPQC controller.
Since the present approach of iUPQC is designed for ap-
plication in three-phase three-wire systems (without neutral
conductor), zero-sequence components are out of interest.
Hence, simplified 2x2 matrixes of the Clarke Transforma-
tions [11], and a reduced numbers of measurements can be
employed as input signals for the iUPQC controller, as
shown in Fig. 4. In this case, two line-to-line voltages, vSab
and vSbc, of the power supply and two line currents, iLa and
iLb, of the load are used as inputs to the main part of the
iUPQC controller. Additionally, the dc-link voltage is used
as input in the dc-link voltage regulator of the iUPQC con-
troller.
The voltages and currents measurements in Fig. 4 are nor-
malized, such that they have unity amplitudes at nominal
conditions. The supply voltages vSab and vSbc are transformed
to αβ-variables [11], and given as inputs to a well-known to-
pology of PLL circuit, the q-PLL [12]. The two auxiliary
control signals vα′ and vβ′ produced by the q-PLL are pure
sinusoidal with constant unity amplitudes, and tracks conti-
nuously the frequency and phase angle of the fundamental
positive-sequence component ( V+1 ) of the supply voltage vS.
In terms of normalized values, these auxiliary signals corres-
pond to the desired voltage that the shunt converter of the
iUPQC has to generate to permanently supply the protected
load under nominal voltage conditions. A gain k is used to
properly adjust the amplitudes of the voltage references v+1α
and v+1β with respect to the dc-link voltage reference VdcRef,
such that they effectively produce the desired nominal vol-
tage through the voltage PWM control of the shunt converter.
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v+1α +
v+1α KV
v+1β + + S7
_ S8
vfab Sinus S9
abc → αβ αβ → abc S10
i+1α vfbc _
PWM
S11
current
+ S12
reference i+1β v+1β
+
KV
+
+
p +
Fig. 5. Voltage PWM control for the shunt converter of the
p iUPQC.
Low-pass
filter
PI–
Controller ploss converter of the iUPQC. Note that it has been implemented
+
Vdc Ref in terms of αβ-variables. This allows the use of only two
feed-forward control loops, which minimizes the errors in the
generated voltage vf at the secondary side of the shunt trans-
former. This feed-forward control utilizes just a gain KV to
multiply the voltage error. Hence, this control structure can-
not provide zero-error in steady state. It was preferred in this
initial stage of development of the iUPQC due to its simplici-
ty. In future developments, since the compensating voltage
references v+1α and v+1β are sinusoidal at a known frequency,
the feed-forward structure will be replaced by Proportional-
Resonant Controllers (PR-Controller) [13].
The current references i+1α and i+1β for the series converter
are calculated from the average real power ( p ) of the load,
the output signal ploss given by the dc-link voltage regulator,
and from the auxiliary signals vα′ and vβ′ produced by the
q-PLL. The Current Reference block in Fig. 4 realizes the
following equation.
⎡i+1α ⎤ ⎡( p + ploss ) vα′ ⎤
⎢ ⎥=⎢ ⎥ (1)
⎣i+1β ⎦ ⎣( p + ploss ) vβ′ ⎦
When the iUPQC is compensating voltage sags or swells,
the signal ploss is responsible for providing a circulating real
(active) power through the dc-link of the iUPQC that is ne-
cessary to keep the load being supplied under nominal vol-
tage. A simple example follows to better understand this fea-
ture. Assume that the supply voltage vS drops to 0.8 pu, and
the load voltage vL is maintained at 1.0 pu by the shunt con-
verter. For simplicity, assume that the load is draining 1.0 pu
of current with unity power factor. Under these conditions,
the PI-controller of the dc-link voltage regulator will adjust
the signal ploss, such that (1) will provide a 1.25 pu of current
reference (i+1) for the series converter, to provide energy bal-
ance inside the iUPQC. In other words, the signal ploss,
forces the series active filter to drain from the power system
the total energy delivered to the load. That is the unique
condition to keep constant the dc-link voltage of the iUPQC.
From (1), it is possible to see that the series active filter al-
ways drains only active current from the power system (unity
power factor). Therefore, in steady state, the power drained
from the network is equal to the power supplied to the load,
that is, pS = pL . Note that pS = vSiS = 0.8x1.25 = 1 pu.
220
Since the voltage on the series active filter is vC = vL – vS
= 0.2 pu, and the current passing through the series transfor-
mers is 1.25 pu, the series converter is injecting 0.25 pu of
active power into the system (pseries = vCiS). On the other
hand, the shunt converter drains a current iC = iS –
iL = 0.25 pu, which means that shunt converter drains
0.25 pu of active power into the dc link (pshunt = vLiC), pro-
viding energy balancing inside the iUPQC. As conclusion,
the a circulating power from (to) the shunt converter to
(from) the series converter of the iUPQC appears during vol-
tage sags or swells compensation.
Fig. 6 shows the implemented current PWM control for the
series converter of the iUPQC. The current references
i+1α and i+1β determined by the iUPQC controller (Fig. 4) are
the principal inputs of the current PWM control of the series
converter. Two feedback minor loops are implemented by
measuring the shunt converter current if, as shown in Fig. 3.
To improve the performance of the Proportional-Integral
controller (PI-controller) in Fig. 6, the estimated compensat-
ing voltages vCα and vCβ of the series active filter is provided
as "disturbances" in the PWM control system, in a similar
way as usually implemented in several applications of shunt
active filters [11]. Note that these compensating voltages are
estimated from the measured supply voltages and the voltage
references for the shunt converter, already available in the
iUPQC controller, as shown in Fig. 4. Finally, it should be
highlighted that the PI-controller in the current PWM control
cannot guarantee zero-error in steady state, because the
PWM control is implemented in the stationary αβ-reference
frames and the compensating current references i+1α and i+1β
have sinusoidal waveforms at the fundamental frequency.
Again, this control strategy should be replaced by
PR-Controllers, as presented in [13], in a future stage of de-
velopment of the iUPQC.
IV. COMPLETE DIGITAL MODEL OF THE iUPQC
For the purpose of fast developing the program code of the
digital controller of the iUPQC prototype that is based on a
fixed-point DSP (TMS320F2812), a user-defined library in
v+1α
_+ v Cα
vSα
+
+
i+1α PI
_ +
ifa
abc → αβ αβ → abc
Sinus
PWM
ifb _ S5
i+1β PI
+ +
_ +
vSβ
vCβ
+
v+1β
Fig. 6. Current PWM control for the series converter of
the iUPQC.
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the PSCAD/EMTDC electromagnetic transient program was
developed. It allows writing and testing the program code –
already written in fixed-point arithmetic – together with the
digital modeling of the power circuit of the iUPQC and the
experimental test setup that will be used in the laboratory, al-
together, in the PSCAD/EMTDC environment. This proce-
dure has saved much time and permitted to eliminate a labo-
rious task after simulations, that is the translation of the con-
trol system from the continuous-time domain to the discrete-
time domain (digital control system). Further, it reduced the
risks of damages in the experimental stage of development.
Basically, the extra user-defined blocks consist of interface
blocks that serves as I/O interface between the PSCAD elec-
trical system and control variables and the variables in the
digital controller of the iUPQC. An additional user-defined
block was created containing a header and a footnote to pro-
vide alias between PSCAD/EMTDC parameters/variables
and the program code parameters/variables of the iUPQC
digital controller. In the core of this user-defined block the
complete fixed-point program code is written and tested.
When finished, this core of program code can be transferred
directly to the DSP of the iUPQC experimental prototype.
The laboratorial test setup including the iUPQC prototype
was constructed for a power rating of 220 V, line-to-line vol-
tage, and 14 A, line current. The measured voltages and cur-
rents are normalized by their amplitude values, instead of
their rms values. Thus, 311 V and 20 A are used as basis for
the normalized measurements. The dc reference value, VdcRef,
for the dc-link voltage is 450 V.
The complete digital model of the laboratorial test setup
that was implemented in the PSCAD/EMTDC program con-
sists in three major blocks: the source, the iUPQC and the
non-linear load, as shown in Fig. 7. The three-phase voltage
source block consists of three ideal voltage sources com-
posed of a fundamental positive-sequence component that is
imbalanced with a fundamental negative-sequence compo-
nent and is distorted by a 7th-harmonic component, behind an
equivalent source impedance composed of a resistance of
50 mΩ in series with an inductance of 0.5 mH. A three-
phase diode rectifier with an RL dc load of 20 Ω and 10 mH
was used as the non-linear load. Three commutation induc-
tances of 0.5 mH were used in this rectifier.
Initially, The development of the experimental test setup of
S1
S2 the iUPQC was more useful for proving control concepts
S3
S4 than for optimizing system parameters. In other words, not
all parameters of the down-scaled iUPQC experimental pro-
S6
Va
In A Out A A
Three-phase iUPQC
Vb
Voltage Source In B Out B B LOAD
with unbalance Vc In C
& 7th harmonic
Out C C
Fig. 7. Major blocks of the complete digital model of the expe-
rimental test setup involving the iUPQC prototype.
221
 K1
A

B
ware that will be uploaded in the DSP of the iUPQC proto-
C type. This library was named as DSPSim/PSCAD Library.
K2 K2
InA

InB
A

B
A
B
OutA
Fig. 9 shows the control block structure that was build up in-
OutB
InC C C OutC side the DSP TMS320F2812 symbol shown in Fig. 8. The
*

fixed-point arithmetic based program code is inserted in the

20 [Ω]

20 [Ω]

20 [Ω]
Interruption Routine Block of Fig. 9.
*

K4

C
A

B
PWM1 PWM2 PWM3 PWM4 PWM5 PWM6
1e12 [Ω]

RL3

C
A

B
1 [mH] Leg 1 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 Leg 4 750 [μ H]

1 [mH]

1 [mH]
Leg 2
THREE-PHASE
Leg 5
750 [μ H]

750 [μH]
Several simulation cases were carried out to tune the RC
Leg 3
BACK-TO-BACK Leg 6

CONVERTER filters and adjust the gains of the control system. The follow-

20 [μF]

20 [μF]

20 [μF]
Vcc+
4 [uF]
4 [uF]

4 [uF]

V_cc Vcc-

PWM7 PWM8 PWM9 PWM10 PWM11 PWM12

ing figures show the final results, in steady-state conditions.

3.9 [Ω]

3.9 [Ω]

3.9 [Ω]
5 [Ω]

5 [Ω]

5 [Ω]

PWM7 PWM8 PWM9 PWM10 PWM11 PWM12

1e12 [Ω] 1e12 [Ω]

Fig. 10 shows the three-phase voltage generated by the shunt
iUPQC Power Circuit

iUPQC Control
PWM1 PWM3
PWM2
PWM5
PWM4 PWM6
converter of the iUPQC that supplies the non-linear load.
Acquisition & Conditioning
Ias
Ibs
Gain
41,322314
41,322314
MA1_AD1
MA2_AD2
Offset
1.5
1.5
AD_01
AD_02
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6 Din_01
Din_02
O1
O2 Inputs
Fig. 11 shows the three-phase current generated by the series
Vabs O3 from

converter of the iUPQC (source current) that is drained from

2.45098 MV1_AD3 1.5 AD_03 Din_03
Vbcs O4 command
Iaf
2.45098 MV2_AD4 1.5 AD_04 DSP Din_04
O5 buttons
41,322314 MA3_AD5 1.5 AD_05 Din_05
Ibf 41,322314 MA4_AD6 1.5 AD_06 TMS320F2812 Din_06

the power grid. As expected, the shunt converter of the

Vabf notused
2.45098 MV3_AD7 1.5 AD_07 Din_07
Vbcf notused
2.45098 MV4_AD8 1.5 AD_08 Din_08 0 H1
Iap notused erro
41,322314 MA5_AD9 1.5 AD_09 Dout_01
Ibp K2 K1
41,322314 MA6_AD10 1.5 AD_10 Dout_02 H2
Ibl K4 link
41,322314 MA8_AD11 1.5 AD_11 Dout_03
V_cc
Vabl
2.94118 MV5_AD12 0 AD_12 Dout_04
RL3
erro bypass
H3 References
Vbcl
2.45098
2.45098
MV6_AD13
MV7_AD14
1.5
1.5
AD_13
AD_14
Dout_05 serie
H4
Measures
Dout_06
Ial shunt serie
41,322314 MA7_AD15 1.5 AD_15 Dout_07
bypass
0.0 0 OFFSET 1.5 AD_16 PWM8 PWM10 PWM12 Dout_08 H5
PWM7 PWM9 PWM11 link shunt

PWM7 PWM9 PWM11

PWM8 PWM10 PWM12

Fig. 8. Digital model of the experimental test setup involving

the iUPQC prototype. 1

totype were optimized in this stage. For instance, an already 0.5

Voltage (pu)
existing large capacitance in the dc link, C = 9400 μF, was 0
left unchanged. The power converters of the iUPQC were
-0.5
mounted using 1200 V, 200 A, IGBTs. The switching fre-
-1
quency of the power converters is 10 kHz, whereas the sam- 8.4833 8.4875 8.4917 8.4958 8.5
pling frequency of the A/D converters is 20 kHz. Time (s)
Fig. 10. Three-phase voltage generated by the shunt converter of
Fig. 8 shows some details of the digital model of the the iUPQC that supplies the non-linear load.
iUPQC that was implemented in the PSCAD/EMTDC pro-
References
gram. No shunt transformer was used and two circuit- Measures

breakers switch on and off a resistor of 20 Ω for pre-charging

the dc-link capacitor. The shunt converter has L = 750 μH as
commutation inductance, and 3.9 Ω and 20.0 μF as RC filter.
The series transformers have 1:1 turn ratios with a nominal 1.5
1
power of 5 kVA. The commutation inductance of the series
Current (pu)

0.5
converter has 1.0 mH, and the RC filter has 5.0 Ω and 0
4.0 μF, respectively. -0.5
-1
In the lower part of Fig. 8 are two major blocks that con-
-1.5
tain all user-defined components of the library that was de- 8.4833 8.4875 8.4917 8.4958 8.5
Time (s)
veloped specially for directly testing of the embedded soft- Fig. 11. Three-phase current generated by the series converter of
the iUPQC (source current).
8-in & 8-out
digital I/O 12 PWM outputs 1
Shunt Source Load
DSP Measurements &
16 analog
Conditioning 0.5
Level #0 inputs
Current (pu)

A/D
conversion 0
PWM signals

interruption interruption
-0.5
clock routine
Legend:
Reference signals
Page Module
triangular -1
Sinus-PWM 4.4833 4.4875 4.4917 4.4958 4.5
carrier Fortran Block
Time (s)
Level #1
Fig. 12. a-phase currents of the load, the iUPQC shunt converter,
Fig. 9. The DSPSim/PSCAD User Library. and the source current.

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iUPQC behaves as a shunt active filter and supplies the reac- vLab iSb
tive power of the non-linear load, as shown in Fig. 12. iLb

voltage (pu) and current (pu)

V. EXPERIMENTAL RESULTS
After simulations, the program code was extracted from
the PSCAD environmental and uploaded in the DSP of the
iUPQC prototype. Fig. 13 shows an outlook of the mounted iCb
iUPQC prototype.
time (s)
The following experimental results confirm that the digital
model of the iUPQC that was implemented in the Fig. 14. Experimental results from the iUPQC prototype: connec-
tion of the nonlinear load.
PSCAD/EMTDC represented with sufficient accuracy the
real iUPQC prototype. The following results were obtained
with the iUPQC being supplied by vS = 220 V (line-to-line vSa vSb vSc
voltage), compensating a three-phase diode rectifier of 15 A
(dc current). The normalized scales (pu values) is
127x(2)1/2 V for voltages and 15 A for currents.

voltage (pu)
With the iUPQC already in operation, Fig. 14 shows the
instant (t ≈ 1 ms) when the load is connected. This figure
shows the line voltage vLab delivered to the load, the load cur-
rent iLb, the shunt converter current iCb, and the series conver-
ter current iSb. Ideally, the current iSb should be 150º lagging
the supply voltage vSab (not shown in this figure). The active
filtering characteristic of the shunt converter of the iUPQC is
time (s)
confirmed in this figure.
Fig. 15. Experimental results from the iUPQC prototype: imba-
The iUPQC prototype was tested under unregulated and lanced supply voltages (phase-to-neutral voltages).
imbalanced supply voltage conditions. Fig. 15 shows the
phase voltages vSa, vSb, and vSc that are being supplied by the vLc
vLa vLb
grid, whereas Fig. 16 shows the compensated voltages that
voltage (pu)

time (s)

Fig. 16. Experimental results from the iUPQC prototype: compen-

sated load voltages (phase-to-neutral voltages).

are being delivered to the non-linear load. It shows that the

iUPQC provides regulated and balanced voltages to the load.

Fig. 13. Outlook of the iUPQC prototype.
VI. CONCLUSIONS
An alternative approach of Unified Power Quality Condi-
tioner – the iUPQC – was developed. A user-defined library
– the DSPSim/PSCAD User Library – was developed to al-
low writing and testing the fixed-point arithmetic based pro-
gram code that serves as the embedded software in the DSP
of the controller of the iUPQC prototype. This procedure
saved time and reduced risks of damage in the experimental

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Authorized licensed use limited to: Synopsys. Downloaded on January 8, 2010 at 23:09 from IEEE Xplore. Restrictions apply.
stage of development.
A great advantage of the proposed iUPQC approach when
compared with previous proposal of UPQCs like those pre-
sented in [3], [4] and [11] is the fact that both PWM control
of the series and the shunt converters of the iUPQC deals
compensating reference signals that are pure sinusoidal at the
fundamental frequency.
The proposed iUPQC controller has a simpler structure if
compared with a similar approach that was used in a line-
interactive UPS system introduced in [10]. Further devel-
opment is being carried out to improve the dynamic response
of the iUPQC controller, especially during voltage sags com-
pensation, which will allow cost reduction in the energy sto-
rage capability in the dc link of the iUPQC.
REFERENCES
[1] H. Rudnick, J. Dixon, L. Moran, "Delivering clean and
pure power," IEEE Power and Energy Magazine, vol. 1,
no. 5, pp. 32- 40, Sep-Oct 2003.
[2] B. Han, B. Bae, H. Kim, S. Baek, "Combined operation
of unified power-quality conditioner with distributed
generation," IEEE Transactions on Power Delivery, vol.
21, no. 1, pp. 330- 338, Jan. 2006.
[3] H. Fujita and H. Akagi, "The Unified Power Quality
Conditioner: The Integration of Series- and Shunt-
Active Filters," IEEE Transactions on Power Electron-
ics, vol. 13, no. 2, pp. 315-322, March 1998.
[4] M. Aredes, K. Heumann, E. H. Watanabe, "An universal
active power line conditioner," IEEE Transactions on
Power Delivery, vol. 13, no. 2, pp. 545-551, Apr 1998.
[5] P. Rodriguez, L. Sainz, J. Bergas, "Synchronous double
reference frame PLL applied to a unified power quality
conditioner," in proc. of 10th International Conference
on Harmonics and Quality of Power, vol. 2, pp. 614-
619, 6-9 Oct. 2002.
978-1-4244-3370-4/09/$25.00 © 2009 IEEE
Authorized licensed use limited to: Synopsys. Downloaded on January 8, 2010 at 23:09 from IEEE Xplore. Restrictions apply.
[6] V. Khadkikar, P. Agarwal, A. Chandra, A. O. Barry, T.
D. Nguyen, "A simple new control technique for unified
power quality conditioner (UPQC)," in proc. of 11th In-
ternational Conference on Harmonics and Quality of
Power, pp. 289- 293, 12-15 Sept. 2004.
[7] B. Singh, V. Verma, A. Chandra, K. Al-Haddad, "Hybr-
id filters for power quality improvement," IEE Proceed-
ings - Generation, Transmission and Distribution, vol.
152, no. 3, pp. 365- 378, May 2005.
[8] Steven Moran, " A Line Voltage Regulator/Conditioner
For Harmonic-Sensitive Load Isolation," in proc. of the
1989 IEEE Industry Applications Soc. Ann. Meeting, pp.
947-951, Oct 1989.
[9] Farrukh Kamran and Thomas G. Habetler, "A Novel On-
Line UPS with Universal Filtering Capabilities," IEEE
Transactions on Power Electronics, vol. 13, no. 3, pp.
410-418, May 1998.
[10] S. A. O. Silva, P. F. Donoso-Garcia, P. C. Cortizo, "A
Three-Phase Line-Interactive UPS System Implementa-
tion With Series-Parallel Active Power-Line Condition-
ing Capabilities," IEEE Trans. on Industry Applications,
vol. 38, no. 6, pp. 1581-1590, Nov/Dec 2002.
[11] H. Akagi, E. H. Watanabe, M. Aredes, Instantaneous
Power Theory and Applications to Power Conditioning,
New Jersey: IEEE Press/Wiley-Interscience, 2007,
ISBN: 978-0-470-10761-4.
[12] L. G. B. Rolim, D. R. Costa Jr., M. Aredes, "Analysis
and Software Implementation of a Robust Synchronizing
PLL Circuit Based on the pq Theory," IEEE Trans. on
Industrial Electronics, vol. 53, no. 6, pp. 1919 1926,
Dec. 2006.
[13] A. Ortiz, M. Aredes, L. G. B. Rolim, E. Bueno, P. Ro-
driguez, “A New Current Control For The STATCOM
Based On Secondary Order Generalized Integrators,” in
Proc. of the PESC 2008 - 39th IEEE Ann. Power Elec-
tronics Specialists Conf., Rhodes, Greece, ISBN
9781424416684, pp. 1378-1383, 15-19 June 2008.
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