Introduction
Instructor: Dr. LAI, An-Chow
Course Info.
Email:
laiac@utar.edu.my
Office:
KB Block 8th floor Room 11(3)
Office hours: Tuesday 2pm-4pm, Thursday2pm-4pm, or
by appointment
Midterm: 31-July-2015, in class
Textbook:
Patterson D. A. / Hennessy J. L., (1998) 2nd Ed. Computer
Organisation and Design: The Hardware/ Software Interface, Morgan
Kaufmann.
Introduction
Evaluation
Weight breakdown
Final
Midterm
Assignments
Labs
60%
15%
15%;
10%
Coursework
5 tutorials
Start on 3rd week, i.e. 26-June-2015 (Thursday)
Randomly choose students to explain their works during tutorial
Part of tutorial questions are Assignment questions
Assignment answers are due before each tutorial starts
2 labs (group of 2)
Lab #1 planned on Week#4 (TBD)
Lab #2 planned on Week#10 (TBD)
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Introduction
data to memory.
Output: reads data from memory.
Memory: stores instructions and data.
Processor, which consists of:
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Real Stuff
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Levels of Abstraction
Hardware
System Software (e.g. Windows, Linux)
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Key ideas:
Examples?
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10
s w a p ( in t v [ ], in t k )
for human
{ in t te m p ;
High-level language
program (in C)
te m p = v [k ];
v [ k ] = v [k + 1 ];
v [k+ 1 ] = te m p ;
}
C compiler
Assembly (low-level)
language program (for MIPS)
sw ap:
m u li $ 2 , $ 5 , 4
a d d $ 2 , $ 4 ,$ 2
lw
$ 1 5 , 0 ($ 2 )
lw
$ 1 6 , 4 ($ 2 )
sw
$1 6, 0($2 )
sw
$1 5, 4($2 )
jr $ 3 1
Assembler
for machine
00000000101000010000000000011000
00000000100011100001100000100001
10001100011000100000000000000000
10001100111100100000000000000100
10101100111100100000000000000000
10101100011000100000000000000100
00000011111000000000000000001000
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Questions?
Some modern instruction set architectures:
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Operating system
Compiler
(Windows 98)
Assembler
I/O system
Digital design
Circuit design
Transistors
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Technology
13
Operating systems
Computer
Architecture
Programming languages
Applications
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14
Year
Technology used in
computers
Relative
performance
per unit cost
1951
Vacuum tube
1965
Transistor
35
1975
900
1995
2,400,000
2005
6,200,400,000
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Moores Law
15
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Processor:
Memory:
Disk:
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Suns Surface
10,000
Rocket Nozzle
1,000
Nuclear Reactor
100
8008 8085
1
Hot Plate
8086
10
40048080
1970
286
1980
386
Pentium
Processors
486
1990
2000
2010
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Harvard architecture
only one bus is used (shared) for data and instruction transfers
data transfers and instruction fetches must be scheduled;
because they cannot be performed at the same time
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23
Questions?
Copyright Dr. Lai An Chow
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Principle of abstraction
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