Abstract

In this EE-438: Processing for Microelectronics experiment, integrated circuits were

fabricated on silicon wafers over eleven laboratory sessions. After fabrication, the integrated
circuits were tested and characterized. Four different types of devices were tested. These
devices includes resistors, p-n diodes, capacitors, and metal oxide semiconductor field effect
transistors (MOSFETs). Results were tabulated and plotted in the various Figures and Tables
within the report.

Introduction
In the past few decades, microprocessors have completely revolutionized the world and
the economy. Microprocessors are integrated circuits that are formed on the surface of a silicon
wafer using various chemical and physical deposition techniques. In 1965, Gordon E. Moore
predicted that the number of transistors per unit area on a silicon wafer would approximately
double every year, while maintaining the same relative cost. Since then, his prediction has
shown to be true. Figure 1 illustrates Moores law by plotting the number of transistors of various
commercial computer chips vs time on a logarithmic scale.

Figure 1 Moores law with # of Transistors vs time

Obviously Moores law must have a physical limit. However due to tremendous amounts
of research performed to solve the problems of decreased device size, the shrinking of
microprocessors has maintained its pace. This experiment creates and tests devices such as
resistors, diodes, capacitors, and MOSFETs that have formed on the surface of a p-doped
silicon wafer.
Following the introduction, the report will briefly explain the theory behind the
measurements and testing techniques for resistors, p-n diodes, MOS capacitors, and
MOSFETs. Then the report will go over results from all of the experiments including tables of
calculated parameters and figures of the various trends found in testing. Next, the report will
briefly discuss the results and finish with some concluding remarks on the course. References
used will be listed at the end of the report.

Theory
Resistors
Resistors act to reduce current flow and lower voltage levels within circuits. Sheet
resistance is the resistance of then films that are nominally uniform in thickness. This
experiment aims to measure the sheet resistance of the resistors on the silicon wafer using two
different methods. These two methods are the Transmission Line Measurement (TLM) and the
Transfer Line Method (also TLM).
The total Resistance (RT) measured in this experiment is sum of the resistance due to
the wire & probe tips (usually small and neglected), plus the resistance due to the contact metal
(Rm), plus the resistance due to the metal-semiconductor contact (Ohmic Contact Rc) and the
resistance of the doped layer (Rs).

RT =2 R m+ 2 R c + R s Eqn(1)

Since Rm is generally small compared to Rc and Rs, it can be neglected, resulting in Eqn 2.

RT =2 R c +R s Eqn ( 2 )

Rs can be related to the Rsh in Eqn 3.

RS =Rshd / A Eqn ( 3 )

Using d1 & d2 as the distance between two points on the resistor and those points
corresponding measured total resistance of RT1 & RT2 the following equations can be obtained.

RT 1=2 Rc + R shd 1 / A Eqn ( 4 )

RT 2=2 Rc + R shd 2 / A Eqn ( 5 )

Rsh and Rc can now be solved giving:

Rc =

RT 1 d 2RT 2 d 1

Rsh=

2 ( d 1d 2 )

Eqn(6)

A(RT 1RT 2)
Eqn(7)
( d 1d 2 )

The disadvantage of the transmission line method for finding Rsh is that the A or the
cross sectional area of the carrier flow in the IC resistor is needed and that depends on the
junction depth (t) of the diffused layer at the end of the process, and we usually do not have this
number available. That is why the Transmission Line Measurement (TLM) is used more
commonly in which both Rc & Rm can be extracted simultaneously without much trouble
The transfer line measurement utilizes one structure with measurements taken at
various distances. The resistance vs the distance is then plotted, and Rc and Rsh can be
extracted from the y-intercept and the slope of the graph respectively.

Figure 2 shows the structures of the four resistors used in this experiment.

The sheet resistance can also be expressed in the following equation:

( WL )

R=R sh

Eqn( 8)

eff

Using this method, the length of the resistor needs to be corrected for the presence of the pads
and for corners.
PN Diodes
A p-n diode is made by joining a p-type semiconductor to an n-type semiconductor. This
causes current to be conducted in only one direction, with high resistance in the opposite
direction.

Figure 3 shows a cross section of a sample p-n diode

The potential difference that occurs naturally in the diode is known as the built in
potential (Vbi). The Vbi is given in the following equation:

( KTq ) ln ( N nP ) Eqn(9)
n

V bi =

2
i

The Vbi can also be calculated from a plot of the current vs potential bias. Current through the
diode as a function of potential bias is given in the following equation:

qV
1 Eqn(10)
nKT

( ( ) )

I =I 0 exp

Where V is the applied bias, n is a correction factor for non-ideality, and I0 is the reverse current.
Taking the natural log of Eqn 10 gives:

( ( ))

ln ( I )=ln ( I 0 ) + V

q
nKT

Eqn(11)

By making a linear plot of Eqn 11, I0 can be calculated from the y-intercept, and n can be
calculated from the slope.

Figure 4 shows a sample plot of Eqn 11. The three correction factors are derived from the slopes of the
three linear regions

Metal-Oxide-Semiconductor Capacitors
Capacitors are able to store charge when exposed to a potential difference. The three
types of biases that can be applied to capacitors are accumulation, depletion, and inversion.
Accumulation occurs when the gate voltage is less than the flat band voltage. Depletion occurs
when the threshold voltage is greater than the gate voltage. Finally, inversion occurs when the
gate voltage is greater than the threshold voltage.

Figure 5 shows a sample cross section of a capacitor

During wafer testing, the capacitance of a capacitor is measured against the applied bis.
A sample result is given in Figure 6. At very negative biases, the capacitance is equal to the
capacitance of silicon dioxide, the maximum capacitance. At very positive biases, the
capacitance is equal to that of silicon, the minimum capacitance. Eqn 12 gives the capacitance
of the surface of the capacitor.

Figure 6 shows a sample plot of capacitance vs voltage

1
1
1
=
+
Eqn(12)
C sf C SiO2 C Si

The thickness of the silicon dioxide layer can be calculated using Eqn 13,

t ox=

ox 0 A
Eqn(13)
C SiO 2

While Eqn 14 gives the thickness of the metal layer:

W=

ox 0 A
Eqn(14 )
C Si

Using the capacitance of the surface, the concentration of ions in the substrate Nsub can be
calculated using Eqn 15 and Eqn 16 through an iterative method.

f =

NA
KT
ln
Eqn(15)
q
ni

( )

4 f Csf
N =
Eqn(16)
2
q si 0 A
Using NA, the Deby length and subsequently the flat band capacitance can be calculated in Eqn
17 and Eqn 18 respectively.

Ld =

C FB=

si 0 KT
2

q Na

Eqn(17)

1
Ld
1
+
C ox si 0 A

Eqn(18)

Once the flat band capacitance has been calculated, the flat band voltage can be calculated.
This is done by performing a regression along the linear region in the capacitance vs voltage
plot. Solving for the flat band voltage then allows for the calculation of the fixed static surface
charge Qss using Eqn 19, 20, and 21.

Qss =C Sio 2 ( V FB ms ) Eqn(19)

m s Eqn ( 20 )
ms=
s=X si +

Eg
+ f Eqn(21)
2

Finally, the number of charges per unit area of the capacitor can be found by Eqn 22.

Nf =

Q ss
Eqn(22)
qA

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

8

Figure 7 shows an example cross section of a MOSFET

A MOSFET is a transistor that is used turn an electrical signal on or off. A potential difference
across the source and drain of the MOSFET causes a channel between the source and drain to
conduct, giving the MOSFET its on/off capabilities. In this experiment, the gate voltage was
varied between 1-13 volts while the voltage across the source and drain varied between 0-15
volts. In the linear region for the relationship between current and voltage the Square Law
model is applicable.

I ds =

C0W
V gs V th ) V ds 0.5V 2ds Eqn(23)
(
L

The relationship between the voltage of the drain to the source and the gate to the source is
given in Eqn 23.

V ds=V gs V th (Eqn24)
Substituting Eqn 24 into Eqn 23 gives:

I ds =

C0W
(V gs V th )2 Eqn( 25)
L

By plotting the square root of Eqn 25, fitting the plot to a line, the slope of the line can be used
to find the carrier mobility and the threshold voltage Vth. The saturation velocity is given by:

V s=

( V gsV th )
2L

Eqn(26)

If Idss is plotted against Vgs.

Transconductance (gm, gc, and gd) is the inverse of resistance, and is represented by the
relationship between Ids and Vgs or Vds.

g m=

I ds
V Eqn(27)
V gs ds

( )

I ds
V Eqn( 28)
V ds gs

( )

gd =

gc =

I ds
V Eqn(29)
V ds gs

( )

Transductance is the ability of charges to move through a given pathway. Voltage swing helps
determine the top 10% of the range of voltages in which the MOSFET will be operated. This is
calculated by plotting gm/gd vs Vgs.

Figure 8 shows an example plot of the ratio of gm to gd, giving the voltage swing

10

Results
Resistors
The transfer line method was used to measure the sheet resistance of the resistors (Rsh). The
sheet resistance was measured by placing the probe tips at varying distances and measuring
the resistance. The data was then plotted in Figure 9 and fitted with a linear line. Using the
slope of the line, Rsh was calculated to be 2.95 ohm/square. The y-intercept of the linear fit was
used to calculate the ohmic contact resistance Rc to be 18.6 ohms.

Resistance vs Length of Separation

120
100
f(x) = 0.15x + 38.17
R = 0.89

80

Resistance (ohm)

60
40
20
0

50

100

150

200

250

300

350

Distance (um)
Resistance vs Distance
Linear (Resistance vs Distance)

Figure 9 Resitance (ohm) vs Distance (um) for transfer line method

Table 1

Length
(um)

Correcte
d Length
(um)

Width
(um)

Resistan
ce
(ohm)

Rsh
(ohm/sqr
)

400

440

10

166

3.77

800

840

10

380

4.52

5400

5365.2

10

2750

5.13

Avg

4.47

11

400

STD

0.68

Three other Integrated circuit resistors were also used to calculate the sheet resistance
Rsh. Corrections for the pads were made for each of the three resistors by adding 40 um to the
nominal length. For the 5400 um resistor, a corner correction was needed for the 17 corners in
the resistor. The average sheet resistance was calculated to be 4.47 +/- 0.68 ohm/square as
shown in Table 1.

PN Diodes
Two diodes were tested in this experiment. The Current vs Voltage for the two diodes was
plotted in Figure 10 and Figure 11.

Current vs Voltage Diode 1

8.00E-03
6.00E-03

Current (A)

f(x) = 0.07x - 0
R = 1

4.00E-03
2.00E-03
0.00E+00

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16

-2.00E-03

V (volts)

Figure 10 shows the current vs voltage for diode #1

12

Current vs Voltage Diode 2

8.00E-03
6.00E-03

Current (A)

f(x) = 0.07x - 0
R = 1

4.00E-03
2.00E-03
0.00E+00
-2.00E-03

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16

V (volts)

Figure 11 shows the current vs voltage for diode #2

The linear region of each diode plot was fitted to a line. Using the x-intercept from the
diodes linear regression, the built in potential Vbi was calculated for each. The Vbi for the first
and second diodes was 0.57 and 0.58 volts respectively. The natural logarithm of the current for
each diode was taken and plotted against the voltage in Figure 12 and Figure 13.

Ln(I) vs Voltage (volts) DIode 1

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

-2
-4

f(x) = 61.09x - 12.48

R ==112.98x - 6.96
-6 f(x)
R = 1
- 19.29(n1)
ln(I)Ln(I)-8vs V f(x) =n1469.12xLinear
R = 0.84

n2

Linear (n2)

-10
-12
-14
-16

V (volts)

Figure 12 natural log of current vs voltage for diode #1

13

n3

Linear (n3)

Ln(I) vs V Diode 2
0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

-2
-4

f(x) = 66.01x - 12.7

R = 0.99
14.38x
- 7.18- 21.68
-6 f(x) =
f(x)
= 655.11x
R =R
1 = 0.84
vs V
n1
Linear (n1)
ln(I)ln(I) -8

n2

Linear (n2)

n3

Linear (n3)

-10
-12
-14
-16

V (volts)

Figure 13 natural log of current vs voltage for diode #2

For each diode, and subsequent plot of Ln(I) vs Voltage, there were three distinct linear regions.
For each linear region, a linear regression was performed and plotted in Figure 12 and Figure
13. Using the y-intercept of the third linear region, (the region measured closest to a voltage of
0), the reverse saturation current I0 was calculated and tabulated in Table 2. Also, using the
slopes of each linear region, the non-ideality factors n1, n2, and n3 were calculated and tabulated
in Table 2.
Table 2

Diode
1
Diode
2

Vbi
(volts)

Ln(I0)

I0 (Amps)

n1

n2

n3

0.57

-19.29

4.19E-09

3.00

0.64

0.083

0.58

-21.68

3.84E-10

2.71

0.59

0.059

14

Metal Oxide Semiconductor (MOS) Capacitors

Measurements were taken on two circular capacitors each with diameters of 400 um. For each
capacitor, the capacitance was plotted against the voltage as shown in Figure 14 and Figure 15.
The capacitance of the silicon oxide (CSiO2) was found using the flat region on the right hand side
of the graphs while the capacitance of silicon (CSi) was found using the flat region on the left
hand side of the graphs. Using the capacitance of the silicon oxide and the silicon, the surface
capacitance (Csf) was found using Equation 12. Also, using Equation 13 and 14 the oxide layer
and metal thickness were calculated (tox and W respectively). Next, iterating upon Equation 15
and Equation 16, the concentration in the silicon substrate (Nsub) was calculated. All iteration
calculations are tabulated in Tables 3 while the calculated values for each term are tabulated in
Table 4.
Table 3

Capacitor
1 Guess
#

1
2
3
4
5
6
7

Nsub (cm3)
1.00E+1
5
5.00E+1
5
2.50E+1
6
3.00E+1
6
3.70E+1
6
3.80E+1
6
3.87E+1
6

f (V)
2.88E01
3.30E01
3.71E01
3.76E01
3.81E01
3.82E01
3.83E01

Nsubcal
(cm3)
2.92E+
16
3.34E+
16
3.76E+
16
3.80E+
16
3.86E+
16
3.87E+
16
3.87E+
16

15

Capacit
or 2
Guess
#

1
2
3
4
5
6
7

Nsub
(cm3)

1.00E+
15
5.00E+
15
1.00E+
16
5.00E+
16
4.00E+
16
3.50E+
16
3.72E+
16

f (V)

Nsubcalc
(cm-3)

2.88E01
3.30E01
3.48E01
3.89E01
3.83E01
3.80E01
3.82E01

2.81E+
16
3.21E+
16
3.39E+
16
3.79E+
16
3.74E+
16
3.70E+
16
3.72E+
16

Capacitor 1
1.40E-10

Capacitor
1
Capacitance
(F)

f(x) = - 0x - 0 1.20E-10
1.00E-10
R = 1
8.00E-11
Linear Region
Linear (Linear Region)
6.00E-11
4.00E-11
2.00E-11

0.00E+00
-14.00 -12.00 -10.00 -8.00 -6.00 -4.00 -2.00 0.00

2.00

4.00

Voltage (V)

Figure 14 Capacitance vs Voltage for capacitor #1

Capacitor 2
1.40E-10
f(x) = - 0x - 0
R = 1
Capacitor
2
Capacitancer
(F)

Linear Region

1.20E-10
1.00E-10
8.00E-11
Linear (Linear Region)
6.00E-11
4.00E-11
2.00E-11

0.00E+00
-14.00 -12.00 -10.00 -8.00 -6.00 -4.00 -2.00 0.00

Voltage (V)

Figure 15 Capacitance vs Voltage for capacitor #2

Table 4

Area
(cm2)
tox (cm)
W (cm)

Capacitor 1

Capacitor 2

1.26E-07
3.69E-10
1.52E-09

1.26E-07
3.70E-10
1.56E-09
16

2.00

4.00

CSiO2 (F)
CSi (F)
Csf (F)
f (V)

1.17E-10
2.85E-11
2.29E-11
3.83E-01

1.17E-10
2.79E-11
2.25E-11
3.82E-01

Following the calculation of the ion concentration Nsub, other values can be calculated.
The Deby Length (Ld) can be calculated using Equation 17. Using the Deby Length and
equation 18, the flat band capacitance (CFB) can be calculated. To calculate the flat band voltage
VFB, a linear regression was performed for each capacitor on the linear regions of Figure 14 and
Figure 15. Using CFB and the linear regression, VFB was calculated. By plugging VFB into
equation 19, the fixed static surface charge Qss was calculated. Finally, by combing Equation 22
and Qss, the number of charges per unit area on the capacitors surface was calculated. All the
calculated values for the second half of the capacitor calculations are tabulated in Table 5.

Table 5

Ld (cm)
CFB (F)
VFB (V)
ms (V)
Qss (C)
Nf (cm-2)

Capacitor 1
5.19E+03
1.06E-10
-7.26E+00
-8.93E-01
-7.48E-10
-3.72E+16

Capacitor 2
5.29E+03
1.06E-10
-7.53E+00
-8.92E-01
-7.78E-10
-3.87E+16

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Two metal oxide semiconductor field effect transistors (MOSFETs) were tested in this
experiment. One MOSFET had a channel width of 40 m while there other had a channel width
of 80 m. Both MOSFETS had a gate length of 16 m. Measurements for each MOSFET were
taken in the linear range with drain to source voltages (Vds) between 0 and 1 volt, and the
saturated region, with Vds between 0 and 15 volts. The drain to source current (Ids) was plotted
against the Vds for the linear and saturated regions for both the 40 and 80 m wide channels in
Figure 16, Figure 17, Figure 18, and Figure 19.

17

W = 40m L = 16m Linear Region

4.50E-05
4.00E-05
3.50E-05
3.00E-05
2.50E-05

Drain to Source Current (Ids Amps)

2.00E-05
1.50E-05
1.00E-05
5.00E-06
0.00E+00
-5.00E-06

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Drain to Source Voltage (Vds)

Figure 16 Current Drain to source vs Drain to source voltage for W = 40 um and L = 16 um linear
region

W = 40 m L = 16 m Saturated
3.00E-03
2.50E-03
2.00E-03
1.50E-03
1.00E-03
5.00E-04
0.00E+00

10

12

14

16

18

-5.00E-04
Figure 17 Current Drain to source vs Drain to source voltage for W = 40 um and L = 16 um saturated
region

18

W = 80 m L = 16m Linear
9.00E-05
8.00E-05
7.00E-05
6.00E-05
5.00E-05
4.00E-05
3.00E-05
2.00E-05
1.00E-05
0.00E+00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure 18 Current Drain to source vs Drain to source voltage for W = 80 um and L = 16 um linear
region

W = 80 m L= 16 m Saturated
5.00E-03
4.50E-03
4.00E-03
3.50E-03
3.00E-03
2.50E-03
2.00E-03
1.50E-03
1.00E-03
5.00E-04
0.00E+00

10

12

14

16

18

Figure 19 Current Drain to source vs Drain to source voltage for W = 80 um and L = 16 um saturated
region

19

The threshold voltage (Vth) and the average carrier mobility () were calculated by
plotting the square root of Ids vs the gate to source voltage (Vgs) and performing a linear
regression on Figure 20. Vth was extracted from the x-intercept and was calculated using the
slope of the line.
0.05
0.05

f(x) = 0x - 0.01
R = 1

0.04
0.04
W = 40 um

Linear (W = 40 um)

0.03

W = 80 um

(Lds)^(1/2) (Amps^1/2) 0.03

0.02
0.02
0.01
Linear (W = 80 um)0.01
0

f(x) = 0x - 0.01
R = 0.97
2

10

12

14

Gate to Source Voltage (Vgs)

Figure 20 square root of Ids vs Gate to Source Voltage

The saturation velocity (Vs) was calculated by plotting Idss vs Vgs in Figure 21. A
regression was performed on the linear section of Figure 21, and using the slope of the line, Vs
was calculated.

20

Idss vs Vgs
0
0
W =040 um

Linear (W = 40 um)

f(x) = 0x - 0
R = 0.99 Linear (Linear (W = 40 um))

Idss (mA)

0
0

f(x) = 0x - 0
R = 0.99

0
0
W = 80 um
0
0

Linear (W = 80 um)
2

Linear (Linear (W = 80 um))

10

12

14

Vgs (V)

Figure 21 Idss vs Vgs

The next calculation performed was to plot the transconductance (gm) of the MOSFETs
as a function of Vgs. This was done by choosing a Vds in the saturated region, and calculating the
difference in Idss between adjacent Vgs values and dividing by the difference in Vgs. The results of
gm/W vs Vgs for both the 40 and 80 um wide channel MOSFET were plotted in Figure 22.

gm/W vs Vgs
1.20E+01
1.00E+01
8.00E+00

gm/W (mS/mm)

6.00E+00
W = 40 um

W = 80 um

4.00E+00
2.00E+00
0.00E+00

10

12

14

Vgs (volts)

Figure 22 transductance gm per width vs Vgs

Figure 22 clearly does not show a maximum value of gm. This can also be seen by
examining Figure 17 and Figure 19. Both figures show an increasing space between each line,
with not maximum space. In order to find gmmax, larger Vgs voltages should be tested.

21

Following the calculation of gm, the output conductance gd was calculated. This was done by
choosing two Vds values and calculating the ratio of the corresponding difference in Idss against
the difference in Vds. The results of gd/W vs Vgs were plotted in Figure 23 while the results of
gm/gd were plotted in Figure 24.

gd/W vs Vgs
12
10
8
6 40 um
gd/W (mS/mm) W =

W = 80 um

4
2
0

10

12

14

Vgs (volts)

Figure 23 transductance gd per width vs Vgs

gm/gd vs Vgs
1.20E+01
1.00E+01
8.00E+00
W = 40 um
gm/gd 6.00E+00

W = 80 um

4.00E+00
2.00E+00
0.00E+00

Vgs (volts)

Figure 24 gm.gd vs Vgs

22

10

12

14

Finally, the channel conductance (gc) was plotted against Vgs in Figure 17. A
linear regression of the data was performed allowing for the extraction of the carrier
mobility in the linear region (linear) and the linear threshold voltage V thlinear.

gc vs Vgs
9.00E-05
f(x) = 0x - 0
R = 0.99

8.00E-05
7.00E-05
6.00E-05
5.00E-05

gc

Linear ()

4.00E-05

W = 80 um

Linear (W = 80 um)

f(x) = 0x - 0
R = 0.98

3.00E-05
2.00E-05
1.00E-05
0.00E+00

10

12

Vgs (volts)

Figure 25 gc vs Vgs (linear region)

The results from all of the calculations of the extracted terms are tabulated in Table 6.
Table 6

Vth (V)
lsat (cm2
/V*s)
Vs (cm/s)
gmax
(mS/mm)
Vgsmax (V)
Vswing (V)
linear (cm2
/V*s)

W = 40 um
3.08E+00

W = 80 um
4.64E+00

1.44E+02

6.44E+00

7.15E+05

6.79E+05

4.54E+02

8.68E+02

1.20E+01
8.00E-01

1.20E+01
1.10E+00

1.05E+02

1.84E+02

23

14

Discussion
Due to extreme difficulty, high levels of accuracy were difficult to obtain. However, for the
most part, the data in this experiment showed the general trends expected from the physical
models used. Just about all of of the extracted values for the various electrical parameters were
within the expected range. However, some parameters did not show the expected behavior. For
example, the transductance gm/W was expected to behave in a parabolic manner when plotted
against Vgs, with a maximum value of gm/W. This experiment showed almost the exact opposite,
with the transductance looking as if it was diverging rather than reaching a maximum. This could
have been simply due to too small of voltages Vgs being tested. Future experiments should test
Vgs voltages greater than 13 volts, and maybe a maximum transductance can be found. Also,
threshold voltages were expected to be negative. However, the produced quite large and
positive threshold voltages.

Conclusion
Overall, EE-438 has been a great experience. I have learned many new concepts that I
would never have been exposed to otherwise. EE-438 is a very practical class and has helped
me gain a glimpse and some knowledge of how microprocessors work. As stated before, this
class could be improved by breaking up the lecture into two sessions. I find the content
extremely interesting, however it is still difficult to remain focused late on a Friday afternoon
after a full week of classes.

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References
Kian Kaviani, University of Southern California, EE-438 Microelectronics Processing, lecture
slides, Electrical Characterization of the Finished Wafers Part 1
Kian Kaviani, University of Southern California, EE-438 Microelectronics Processing, lecture
slides, Electrical Characterization of the Finished Wafers Part 2
Kian Kaviani, University of Southern California, EE-438 Microelectronics Processing, lecture
slides, Solid State Processing and Integrated Circuit Laboratory

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