04 Silica Xilinx

XILINX Aerospace solutions
Olivier MEHAIGNERIE / SILICA

Joel LE MAUFF / XILINX
December 2008
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Aerospace & Defense introduction
Avionics solutions
Products offering
Atmospheric Environement Testing & Results
RTCA DO-254 / EUROCAE ED-80
Space solutions
Product offering
Space Environment Testing & Results
Mitigations techniques
XTMR architecture & TMRtool
Summary
2008-12-02_Xilinx-CNES CCT FPGA-JLM 2
Xilinx Confidential
Xilinx Facts
Worldwide leader in programmable solutions
Founded in 1984
$1.8B in revenues in FY 08
~3,500 employees worldwide
20,000+ customers worldwide
Pioneer of the fabless semiconductor model

Inventor of the FPGA
First to 180nm, 150nm, 130nm, 90nm and 65nm
Currently ship over 98% of high-end 65nm production FPGAs in the world
50% PLD market segment share

Larger than all competitors combined
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Innovation at Xilinx
Industrys first 65-nm FPGAs with
1,325 Patents
Xilinx Patent Hall
30% higher performance *

35% lower dynamic power *
65-nm ExpressFabric technology
2nd Generation Triple-oxide technology
Embedded PCIe and GbE interfaces
Enhanced Sparse Chevron packaging
Columnar architecture (ASMBL)
ChipSync
IP immersion
Differential clock tree
Optional FIFO logic
XtremeDSP slice
Tri-Mode hard Ethernet MAC
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* Compared to 90nm Virtex-4 FPGAs
Digital Convergence Drives Demand

The Core Infrastructure ( Virtex )
Performance & capability
are premium
Power & cost constrained
Longer time-in-market
The Expanding Edge ( Spartan )
Cost and flexibility are key
Moderate Performance
Shorter time-in-market
Voice
Data
In-The-Hand ( CoolRunner II )
Cost and size are premium
Power is key
Shortest time-in-market
Video
Xilinx Confidential
Xilinx Serves
a Wide Range of Markets
Communications
Automotive
Aerospace
and Defense
Consumer
Industrial Scientific
and Medical
Infrastructure
Wireless
Infotainment
Instrumentation
Crypto MilComm
Space Avionics
Displays
Handhelds
Surveillance
Test and Measurement
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Programmable Methodology
Abstracting Away the Hardware
DSP
Logic
System Generator
ISE Foundation
System Design
Processor
Simulation
Simulation
IP
Platform Studio
Timing Analysis
Utilization
Power Analysis
ChipScope Pro
HW in the Loop
Xilinx Confidential
ISE Design Suite 10.1

1 Environment for Logic, Embedded and DSP Design
ISE
Foundation
Efficient logic
implementation
PlanAhead
ChipScope
Pro
Design
analysis &
planning
Interactive
system
debugging
EDK / Xilinx
Platform
Studio
System
Generator
AccelDSP
Flexible
embedded
system design
& programming
DSP system
design
(Simulink)
DSP algorithm
development
(MATLAB)
Electronic fulfillment for fast access to updates to updates and evaluation
Xilinx Confidential
Intellectual Property Cores

Augment Your Own R&D to
Maximize Productivity and Reduce risk
Programmable hard IP
Immersed in FPGA fabric
Advantage over soft IP
2x performance
10x lower power
10x less area
Customizable soft IP
Built on FPGA fabric
Examples
LogiCORE (from Xilinx)

AllianceCORE (from partners)
Reference Designs
Advantage over hard IP
Library of >400 blocks
Most flexible
Example IP for Virtex-5 Platform FPGAs
IP
Basic
Hard
BlockRAM/FIFO,
System Monitor
Connectivity PHY (ser./par.), PCIe,
GE, timing critical I/O
logic & clocking
Processing PowerPC 440,
Crossbar switch, DMA,
MCI, Bus I/F
DSP
XtremeDSP slice
(MAC)
System
functions
Xilinx Confidential
Soft
BaseBlox,
Memory I/Fs
Serial and
parallel I/F
protocols
MicroBlaze,
peripherals,
accelerators
Algorithms,
FEC
Traffic
Manager
Features
Products Solutions
3 Product Families: CPLDs + Spartan + Virtex

3 Categories: XC, XA, XQ(R)
I-gra
&
C
XC XA
des
a
r
g
&IXC C XA
s
rade des
g
I
&
ra
XC C I to B-g rades
V -g
om
r
o
f
t
XQ rom M
f
XQR
des
High-Volume FPGAs
SRAM-based
Feature Rich
Low Cost
CPLDs
Low Power
512MC
High-End
FPGAs
High Reliability Products
SRAM-based
Feature Rich
High Performance
75KLC
Xilinx Confidential
330LC
Density
OUTLINE
Xilinx introduction
Products overview

Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Xilinx Continuous Commitment

Virtex-4QV FPGAs: 2008
Virtex-4 QPro FPGAs: 2007
Xilinx Single-chip Crypto: 2006
Xilinx on Mars: 2004
Virtex-II QPro FPGAs: 2004
SEE Consortium formed: 2002
Rad-tolerant Virtex devices : 2000
First Rad-Tolerant devices: 1998
First device qualified to MIL-STD-883: 1989
First field programmable gate array (FPGA): 1985
Xilinx founded: 1984
1985
1990
Source: Company reports
1995
2000
Xilinx Confidential
2005
2010
Xilinx in Aerospace & Defense

A&D drives cutting edge technology
Point of Xilinx Technology Spear
2nd Largest vertical segment within Xilinx

>$240M segment for Xilinx overall
Fastest growing segment within Xilinx
Major area of investment and focus
leveraging existing commercial technology
Xilinx is the market leader in A & D with over 50% market share
Xilinx Confidential
Growth Focused
on Transformation
Networked, space-based, precisionguided, rapidly deployable, joint service,
modular, and secure.
FPGAs are the perfect fit!
Flexible and Reconfigurable

Solve new complex Signal Processing
demands
System On Chip Capabilities
(Feeds SWAP-C *)
Time to Market
Security of HARDWARE vs Software
(*) SWAP-C stands for Size, Weight, Power and Cost
Xilinx Confidential
Xilinx Aerospace & Defense

Integration Solutions
Reduce system complexity and size with integrated
features
PowerPC processor cores

Ethernet MAC
PCIe endpoint blocks
DSP acceleration engines
Digital Clock Management
Increase reliability
Less PCB connections / complexity
SWAP-C: Reduced size, weight, power and cost

Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Spartan-3 family
Optimized Platforms Save Cost

Spartan-3 Platform
For Highest Density & Pin-count Appls
Spartan-3E Platform
Logic Cells
Logic Optimized
Spartan-3A DSP Platform

DSP Optimized
Spartan-3A &
Spartan-3AN Platform
I/O Optimized
I/Os
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Hibernate mode
Suspend mode
Device DNA
Non-Volatile version
Etc
Virtex-5 FPGA Family

The Ultimate System Integration Platform
65-nm platforms
LX
LXT
SXT
FXT
Logic + Serial
DSP + Serial
Emb. + Serial
YES
YES
Samples Now
High-performance
logic
High-perf. logic w/
low-power serial I/Os
Logic
YES
DSP and memoryProcessing and memoryintensive apps w/ lowintensive apps w/

power serial I/Os
highest-speed serial I/Os
Logic
On- chip RAM
DSP Capabilities
Parallel I/Os
Serial I/Os
PowerPC
In Production
EasyPath low-risk, conversion-free cost reduction for all platforms: 30-75% cost savings
Xilinx Confidential
Xilinx FPGA roadmap

Mont
Blanc
Greater Logic capacity
Flexible On-Chip Memory

Greater performance and more
I/O standards
TXT
Broad spectrum of Serdes solutions
Abundand DSP resources
St.
Reducing Power Through Advanced Design and
Process
Andrews
St. Andrews: The Lowest Cost, Easy to Use FPGA
Mont Blanc: Highest Performance, Most Advanced FPGA
Spartan-3
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Terrestrial SEE testing

methodology
1- Qcrit simulation
- when process ground rules available
2- Accelerated SEE testing @ LANSCE
- when 1st silicon out of fab
3- Atmospheric testing / Rosetta Platforms
- when large quantity of packaged silicon available
a) Low Noise Underground testing for Reference 0
b) Altitude testing (higher is better)
Xilinx Confidential
SRAM Cell SEU Simulations

This activity is still running
Under Xilinx IM2NP ONERA
collaboration
Goal:
Better understanding at
component level (CMC, BRAM)
of physical phenomena induced
by SEU / MBUs,
SER prediction
Xilinx Confidential
Accelerated SEE testing

Los Alamos Neutron Science CEnter
Goal:
Get access to Cross Sections
Testing done on
Virtex (220nm)
Virtex-E (180nm)
Virtex-II (150nm)
Virtex-IIpro (130nm)
XPLA3 (350nm) (*)
CoolRunner-II (180nm)
Virtex-4 (90nm)
Spartan-3 (90nm)
Spartan-3E/3A (90nm)
Virtex-5 (65nm)
Virtex-II became Calibration component

Xilinx Confidential
Low Noise Underground Testing

OCA-LSBB Reference level
LSBB scientific and technical characteristics insure that
no Soft Error can occur coming from other sources
e.g. noise.
(No sensitivity from thermal neutrons have been revealed because XILINX devices don't use Bore 10 or BPSG)
200 Virtex-IIpro 130nm

2 CMC & 0 BRAM upsets
3,060,000 devices hours
CMC: 54 FIT/Mb, from 7 to 197FIT/Mb
@ 95% confidence interval
BRAM: 86 FIT/Mb, from 0 to 316FIT/Mb
100 Virtex-5 / 65nm

663,000 devices hours
Xilinx Confidential
Altitude testing
OMP + CMB sites
300 Virtex-5 / 65nm

2884m and 3794m altitude
13,800,000 devices hours
Xilinx Confidential
The Rosetta (SEU) Stone

Process
FPGA
Lithography Family
220nm
180nm
150nm
130nm
90nm
90nm
90nm
65nm
Virtex
Virtex-E
V2
V2P
S3
V4
S3E/A
V5
LANSCE >10MeV
Cfg MC
BRAM
ROSETTA
Cfg MC BRAM
cm2
cm2
FIT/Mb
FIT/Mb
0.99E-14
1.12E-14
2.56E-14
2.74E-14
2.40E-14
1.55E-14
1.31E-14
0.67E-14
0.99E-14
1.12E-14
2.64E-14
3.91E-14
3.48E-14
2.74E-14
2.73E-14
3.96E-14
157
177
396
375
190
240
104
138
157
177
431
608
373
380
293
701
(1)
Notes:
Calculations according JESD89A Valid for NYC: 40.7N lat, 286.0 long, Sea-level, Neutron flux= 1.000
(1) Error estimates for each Rosetta measurement @ 95% confidence interval:
o 90nm S3 [-50,+80]%, 90nm S3E [-80, 90]%
o 250nm +/-20%, 180nm +/-20%, 150nm V2 +/-8.2%, 130nm V2P +/-11.1%, 90nm V4 +/-17.7%, 65nm V5 [-27, +34]%
(2) Not enough Rosetta Gbit-years for useful prediction accuracy at this point (experiment running), predicted from LANSCE
(3) All data as of 26aug08
*Config FIT/Mb does not include SEUPI= 10 (no de-rating factor). Divide configuration FIT/Mb by ten to get 1-sigma worst case
(most pessimistic) de-rating factor.
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
DO-254

Product of RTCA SC-180 and EUROCAE WG-46
RTCA: Requirements and Technical Concepts for Aviation

EUROCAE: EURopean Organisation for Civil Aviation Equipment
Title:
Design Assurance Guidance for Airborne Electronic Hardware (AEH)

For PLDs, FPGAs and ASICs
A design flow with checkpoints, verification and expert review
Certification pronounced by
Designated Engineering Representative (DER) in NA, representing FAA,
EASA (European Aviation Safety Agency), directly in Europe.
Represents a consensus of best practices for aviation

Xilinx Confidential
DO-254
DO-254 Section 3
HW Design Life Cycle
3 Key Processes / 5 Design phases
(A-B-C)
(1-2-3-4-5)
Validation & Verification process (section 6)
Configuration Management (section 7)
Process Assurance (section 8)
Certification Liaison (section 9)
System Process
APlanning
process
(section 4)
B- Development Process
-1Requirements
Capture
-2Conceptual
Design
-3Detailed
Design
(section 5.1)
(section 5.2)
(section 5.3)
Derived Requirements
Xilinx Confidential
-4Implementation
(section 5.4)
-5Production
Transition
(section 5.5)
Manufacturing Process
C- Correctness Process
DO-254
DO-254 FPGA Design flow

Project Plans: PHAC,
PA/QA plan, CM plan, Dev. plan, Ver. plan
Planning
System Requirements
Requirements
Capture
Requirements
Review
Conceptual
Design
Detailed Design
Design
Validation & Verification
RTL Design
Verify
Verify RTL
RTL Design
Design
Synthesis
Verify
Verify
Gate-Level
Gate-Level Design
Design
Implementation
Debug
Maping
Design Review
Translate
Device Level
Works OK?
YES / NO => Back to HDL Design
Place & Route
System Safety Analysis

System architecture
SW & HW allocation
HW requirements: Feasible, Verifiable
HW Design: RTL design, Synthesis, P&R

HW Test
Functional tests
Normal range tests
Robustness tests:
Power supplies,
TC, Vibrations & shocks,
Radiations
Coverage analysis
Tracaebility: Correlation between reqs,
design, implementation and verification.
Verification
Review
System Level
Works OK?
YES / NO => Investigate
Download
Bitstream
Silicon
into
FPGA device
Xilinx Confidential
HAS: Identify & Justify Deviations vs PHAC.
Xilinx DO-254
partnership
Training and consulting partnerships
Tools for a requirements-driven
design methodology
ReqTracer
HDL Designer*
ModelSim SE
0-In CDC*
Precision,
HW packages and business models
geared for the aviation market
* Customized for a Xilinx Flow
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Challenges for Designing

Space Applications
Becoming increasingly sophisticated
High data rates and packet processing
ASICs are capable of high performance, but
Long development times, re-spin risk, and NRE are problems
Space unit volumes are better addressed by FPGAs
Previous FPGA solutions
Not capable of high-performance applications
Not reprogrammable
No built-in processing or I/O capabilities
Designers Need High-Performance FPGAs
Capable of Embedded and Signal Processing in Space
Xilinx Confidential
Single-Chip Solution Addresses

Performance Requirements
High-performance applications
Video (compression, encode, decode)

Communications (filtering, processing)
Radar (filtering, processing)
Encryption (AES, 3DES, proprietary)
Packet Processing (802.3, web server)
Control applications
Motor control (low and high-performance)
Bus management (Ethernet, Fiber channel, etc.)
Xilinx Confidential
Xilinx Solutions for Space

Highest Performance, Largest Capacity FPGAs in Space
Selected advanced FPGA products for application in

Space-based systems
Complete Single Event Effects testing and analysis
Tools and techniques for SEU mitigation & management

Applications solutions
Configuration Management & Scrubbing

Special architectural feature considerations
Embedded Processing
Reference Designs
TMRTool Software
Automated Triple Module Redundancy implementation tool
Xilinx Confidential
Guaranteed Quality for Space

Radiation-hardened military ceramic package (QML in process)
True Class-V
Flows
Guaranteed
TID of 300 krad (Si)
SEL
Immunity >125
MeVcm2/mg
Aerospace
Corporation
Certification
Full Military Temperature Range (-55C to +125C)

Xilinx Confidential
Xilinx QPro Aerospace Products

Aerospace QPro-R Radiation Tolerant FPGAs
SEL Immunity
Device
Core
Mfg Grades
Packages
TID (krad)
(MeV-cm^2/mg)
XQR4VLX200
1.2V
CF1509
300
>80
XQR4VSX55
1.2V
CF1140
300
>80
XQR4VFX140
1.2V
CF1144
300
>80
XQR4VFX60
1.2V
CF1509
300
>80
QPro-R Virtex-II
XQR2V3000
XQR2V6000
1.5V
1.5V
M, V
H
BG728, CG717
CF1144
200
200
>160
>160
QPro-R Virtex
XQVR300
XQVR600
2.5V
2.5V
M, V
M, V
CB228
CB228
100
100
125
125
QPro-R Virtex-IV
Aerospace QPro-R Radiation Tolerant Configuration PROMs

SEL Immunity
QPro-R PROMs
Device
Core
Storage Bits
Mfg Grades
Packages
TID (krad)
(MeV-cm^2/mg)
XQR1701L
3.3V
1M
M, V
CC44
50
>120
XQR17V16
3.3V
16M
M, V
CC44, VQ44
50
>120
Enhanced Rad Hard by Design products in development

Xilinx Confidential
Relative Performance
Space Products Roadmap
Rad Tolerant
FPGAs
Rad Hard by
Design
FPGAs
SIRF
Rad Tolerant
FPGAs
XQR4VSX55
XQR4VFX60
XQR4VLX200
XQR2V6000
300KRad
200KRad
2004
>300KRad
XQR4VFX140
XQR2V3000
2002
XQRS5VFX130T
2006
Xilinx Confidential
2008
2010
Xilinx Virtex-4QV
New in 2008!
Multi-platform FPGA family with embedded hard IP

High-performance logic platform
Embedded / Ethernet MACs platform
DSP optimized platform
Unmatched capacity and system integration

Radiation tolerant devices meet Class-V requirements
Reprogrammable technology enables changes at any time
XQR4VSX55
XQR4VFX60
XQR4VFX140
XQR4VLX200
Logic Cells
55,296
56,880
142,128
200,448
CLB Flip-Flops
49,152
50,560
126,336
178,176
Distributed RAM (Kbits)
384
395
987
1392
Xilinx Confidential
U.S. Government Agency Controls
US Dept. of Commerce
US Department of State
Bureau of Industry & Security
Directorate of Defense Trade Controls
Export Administration Regulations

Dual Use products/ technologies
Commerce Control List
International Traffic in Arms Regulations

Inherently military products/ technologies
U.S. Munitions List
US Department of Treasury
Office of Foreign Assets Controls
Administration of US economic
sanctions & embargoes
Xilinx Virtex-4QV are under US DoC EAR

Administered by Bureau of Industry and Security (BIS)
Xilinx Confidential
SIRF
(Single-Event Immune Reconfigurable FPGA)
Key Development Objectives
Deliver Radiation Hardened by Design, Space qualified Virtex-5

FPGA by CY2010
Minimize design complexities and overhead required Space
applications of FPGAs
Eliminate additional design effort and chips for configuration management,
scrubbing, TMR and state recovery
Maintain compatibility with commercial V-5 product for rapid

development
Feature set, floor plan and footprint compatible with commercial product
Address critical SEE sensitive circuits and eliminate all SEFIs
Transparent to S/W Development Tools
Xilinx Confidential
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM

Xilinx Confidential
BRAM
BRAM
BRAM
BRAM
BRAM
x2
BRAM
GTX
BRAM
x2
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
x2
GTX
BRAM
BRAM
IO BANK
BRAM
BRAM
PCI EXPRESS
GTX
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
IO BANK
BRAM
BRAM
DSP
BRAM
DSP
DSP
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
DSP
DSP
PCI EXPRESS
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
DSP
DSP
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
IO BANK
BRAM
BRAM
DSP
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
PCI EXPRESS
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
x2
GTX
BRAM
BRAM
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
DSP
BRAM
BRAM
IO BANK
Speed
Speed Characterization
Characterization
Static
Static and
and Dynamic
Dynamic SEE
SEE
Total
Total Dose
Dose
Dose
Dose Rate
Rate
BRAM
BRAM
BRAM
DSP
IO BANK
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
IO BANK
Comprehensive
Comprehensive Testing
Testing
BRAM
IO BANK
BRAM
BRAM
C M T
BRAM
C L O C K
IO
BRAM
C O N F IG
IO
DSP
C O N F IG
IO
DSP
C M T
DSP
C L O C K
IO
BRAM
C M T
BRAM
C L O C K
IO
BRAM
BRAM
BRAM
DSP
DSP
C O N F IG
IO
BRAM
BRAM
BRAM
DSP
DSP
BRAM
C L O C K
BRAM
BRAM
DSP
DSP
BRAM
BRAM
BRAM
C O N F IG
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
C O N F IG
IO
BRAM
BRAM
BRAM
DSP
BRAM
BRAM
BRAM
BRAM
C M T
BRAM
BRAM
BRAM
DSP
DSP
BRAM
BRAM
BRAM
IO BANK
C L O C K
IO
DSP
BRAM
BRAM
DSP
DSP
BRAM
BRAM
BRAM
IO BANK
C M T
BRAM
DSP
DSP
BRAM
BRAM
IO BANK
C O N F IG
IO
BRAM
BRAM
P
O
W
E
R
P
C
C M T
DSP
BRAM
BRAM
BRAM
BRAM
BRAM
IO BANK
P
O
W
E
R
P
C
C L O C K
IO
DSP
DSP
DSP
BRAM
BRAM
BRAM
BRAM
IO BANK
Configuration
Configuration Memory
Memory
Configuration
Configuration Controller
Controller
CLB
CLB
IOB
IOB
BRAM
BRAM Configuration
Configuration
BRAM
BRAM
BRAM
BRAM
BRAM
IO BANK
FX-1
FX-1 SEE
SEE Hardening
Hardening
BRAM
BRAM
IO BANK
BRAM
IO BANK
SIRF Phases 3 & 4

Determine
Determine performance
performance and
and
mitigation
mitigation strategies
strategies
Implement
Implement feasible
feasible enhancement
enhancement
to
DSP,
BRAM,
CMT,
to DSP, BRAM, CMT, PPC
PPC and
and MGT
MGT
as
require
as require
FX-2
FX-2 SEE
SEE Design
Design Hardening
Hardening
SIRF Radiation Goals & Device

Total Dose
> 300 krad (Si) (requirement)
FX130T
SEE
Latch up
Upset
Functional
Interrupt
Dose Rate
Latch up
Upset
Immune LET > 100 MeV-cm2/mg
Logic Cells
131,072
Total Block RAM (Kbits)
10,836
DSP48E Slices
301
RocketIO GTP Channels
RocketIO GTX Channels
20
PPC440 Cores
PCIe Subsystem Blocks
10/100/1000 EMACs
Error rate < 1 10-10 errors/bit-day

Error rate < 1 10
-10
errors/bit-day
> 1 10 10 rad(Si)/sec
> 1 10 9 rad(Si)/sec
Xilinx Confidential
Package
Size
FF1738
42.5
840
U.S. Government Agency Controls
US Dept. of Commerce
US Department of State
Bureau of Industry & Security
Directorate of Defense Trade Controls
Export Administration Regulations

Dual Use products/ technologies
Commerce Control List
International Traffic in Arms Regulations

Inherently military products/ technologies
U.S. Munitions List
US Department of Treasury
Office of Foreign Assets Controls
Administration of US economic
sanctions & embargoes
Xilinx SIRF will be US DoD ITAR

Xilinx Confidential
QA flows
QPRO V-Grade Ceramic
X
Specification Control
Xilinx Data Sheet
X
Mask Control
Per XILINX Controlled Doc.
X
QML Qualified WaferFab
Per Mil - PRF 38535
X
Wafer Lot Acceptance
Per Internal Param etric Speci
X
Lot RHA
Per TM1019 / Per WaferFab Lo
X
QML Qualified Assem bly
Per Mil - PRF 38535
X
Destructive Bond Pull
Per TM2011, Sam ple, SPC
X
Internal Visual
Per TM2010B, 100%
X
Tem perature Cycling
Per TM1010, 100%
X
Constant Acceleration
Per TM2001, 100%
X
Fine/Gross leakage
Per TM1014, 100%
X
Pind-Test
Per TM2020
X
Radiography Insp / X-Ray
Per TM2012, Sam ple, SPC
X
Pre-BI Test @ 25C
Per SMD or DataSheet
X
Static Burn-in (240 hours) Per TM1015B, 100%
X
Post BI Test @ 25C
X
PDA Calculation
Per TM5004
X
+125C Electrical Test
X
-55C Electrical Test
X
Marking Perm anency
Per TM2015
X
DPA
Per TM1580
X
QC Sam pling Plan
Per TM5005, Group A (0/116)
X
QCI
Per TM5005, Groups B, C & D
X
External Visual Inspection Per TM2009, 100%
TEST
Methodology
Xilinx Confidential
M-Grade Ceramic
X
X
X
X
X
X
Sample
X
M-Grade Plastic
X
X
X
X
X
X
Sample
Com. Std
Com. Std
Xilinx Spaceflight Heritage
MARS Lander (JPL) Pyrotechnics

MARS Rover (JPL) Motor Control
MRO (Ball Aerospace) HiRISE Camera
GRACE (NASA) Sensor
Venus Express (ESA) Multiple Virtex designs
FedSat (Univ. Southern Australia)
OPTUS (Raytheon) - DSP
TACSAT2 (NASA)
CIBOLA (LANL) Remote Sensing
National Nuclear Security Administration's
reconfigurable supercomputing payload
50 new programs underway
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Xilinx Radiation Test Consortium

Founding partner of
Radiation Test Consortium
SEE testing and qualification with Space industry leaders
JPL, Sandia National Laboratories, Aerospace Inc.,
NASA Goddard, Los Alamos National Laboratories,
SEAKR, Boeing, Northrop Grumman, General Dynamics,
Lockheed Martin, IBSI, and many others
European SEE consortium: To restart soon.
Static and Dynamic SEE and TID testing

Full validation of SEU mitigation methods
Results published in peer-reviewed journals
Xilinx Confidential
Mature Test Methods & Apparatus
Xilinx Confidential
Qpro-R Virtex-II
Weibull Curve Summary
CELL/SEFI
CONFIG
BRAM
POR1
SMAP2
JCFG3
CELLS PER DEVICE

2V1000 2V3000
2V6000
ONSET POWER WIDTH

LIMIT
Cm
Heavy Ion
(Proton)
2787740 7347524 16395508
1.0
0.8
33
4.37E-8
(3.0)
(0.5)
(12)
(3.8E-14)
737280 1769472 2654208
1.0
0.9
17
4.19E-8
(3.0)
(0.6)
(12)
(4.1E-14)
1
1
1
1.5
1.2
22
2.50E-6
(7.0)
(1.0)
(12)
(3.74E-13)
1
1
1
1.5
1.0
17
1.72E-6
(6.5)
(0.5)
(12)
(5.72E-13)
1
1
1
1.5
1.0
17
2.51E-7
(6.0)
(0.5)
(12)
(2.86E-13)
2
MeV-cm /mg
(MeV)
1. Single Event Functional Interrupt clears configuration memory.

2. Single Event Functional Interrupt deactivates configuration memory read/write access from SelectMAP Port.
3. Single Event Functional Interrupt deactivates configuration memory read/write access from JTAG Port.
Xilinx Confidential
Qpro-R Virtex-II Orbital Rates
Best Case
(Full TMRed)
Worst Case
(No mitigation)
Configuration Memory Cells

Upsets/Device-Day
Typical Solar Conditions
Orbit
LEO
LEO
POLAR
CONST.
GEO
400
800
833
1,200
36,000
Inclination
51.6
22.0
98.7
65.0
XQR2V3000
0.30
4.0
2.7
11.0
0.21
XQR2V6000
0.67
9.0
6.0
25.0
0.47
5.44E-06
2.74E-05
2.00E-06
503
100
1,369
Altitude (km)
Functional Interrupts (All Virtex-II)

Upsets/Device-Day
POR + SMAP + JCFG
2.33E-06
9.87E-06
Device-Years/Event
All SEFIs (Combined)
2,185
277
Xilinx Confidential
Virtex-4 Static SEU Plots
10
-9
-10
10
10
10
20
40
60
80
100
-8
-8
Configuration Cells
10
-7
-9
BRAM Cells
-10
120
20
10
-14
-15
Configuration Cells
10
-16
10
10
20
40
60
80
100
120
Energy (MeV)
SX55
FX60
LX200
-7
10
POR SEFI
-8
10
120
20
40
60
80
100
120
Effective LET (MeV-cm 2 /mg)

-11
10
-13
-14
-15
BRAM Cells
10
100
-13
Cross Section (cm /device)
10
80
-6
10
Effective LET (MeV*cm /mg)
Cross Section (cm /bit)
10
60
-5
10
Effective LET (MeV*cm /mg)

10
40
10
10
-7
10
-16
-12
10
SX55
FX60
LX200
-13
10
POR SEFI
-14
10
20
40
60
80
Energy (MeV)
Xilinx Confidential
100
120
20
40
60
Energy (MeV)
80
100
120
Virtex-4QV Orbital Rates

Configuration Memory Cells
Upsets/Device-Day
Worst Case
(No mitigation)

Orbit
LEO
LEO
POLAR
CONST.
GEO
400
800
833
1,200
36,000
Inclination
51.6
22.0
98.7
65.0
XQR4VSX55
0.76
7.43
5.12
20.0
4.20
XQR4VFX60
0.80
7.79
5.36
20.9
4.40
XQR4VFX140
XQR4VLX200
2.15
21.0
14.5
56.5
11.9
Altitude (km)
Best Case
(Full TMRed)
Functional Interrupts (All Virtex-4)

Upsets/Device-Day
POR
2.83E-06
2.73E-05
1.85E-05
7.36E-05
1.21E-05
SMAP+FAR
2.25E-06
2.45E-05
1.69E-05
6.71E-05
9.46E-06
GSIG
1.57E-06
2.41E-05
1.57E-05
6.47E-05
4.87E-06
53
13.3
103
Device-Years/Event
All SEFIs (Combined)
412
36
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Mitigating SEEs
We cant PREVENT SEUs and SETs

We can only MITIGATE their effects
Xilinx Confidential
Mitigation Schemes
Xilinx Confidential
No Mitigation
Also known as Power Cycle
Clear all issues
May not be applicable
Xilinx Confidential
Scrubbing
Also Known as configuration management
Process of correcting configuration upsets through partial reconfiguration
Doesnt alter FD value
SRL16/LUTRAM a problem until V4 and later

BRAM
Complete solution includes SEFI detection and correction
Hosted externally or internally
Xilinx Confidential
Traditional
Config Management Setup
Xilinx Confidential
Single FPGA Self Scrubbing Setup

FPGA
PROM
XQR18V04/17V16
DATA (0:7)
BUSY*
OE/RESET
CE
CLK
Virtex (II) Series

DATA (0:7) IO (2:0)
BUSY
IO (2:0)
IO (2:0)
INIT
IO (2:0)
DONE
IO (2:0)
CCLK IO(0:7)(2:0)
IO (2:0)
PROG
IO (2:0)
RDWR
IO (2:0)
CS
IO (2:0)
*17v16 only
OSC
SEFI
Reset
WATCH
DOG
Master SelectMAP PROM Boot with Internal Scrub Controller

Xilinx Confidential
PULSE
XTMR
Automate triplication of design
Voter insertion
Auto resync for any FD with feedback
path. (ie. Counter, FSM)
Primitive level triplication

Half Latch, SRL16 extraction
Custom Macro for primitives/design
modules too complicated for simple
triplication
DCM, BRAM, bi-directional IO
Xilinx Confidential
MAJORITY
VOTER
MAJORITY
VOTER
MAJORITY
VOTER
Redundant Devices
Multiple FPGAs used
2, 3, 4+ FPGA schemes
4+ scheme: 3 as primary, others as
backup
Most robust mitigation

Resync
Coding more challenging
May not be feasible for all designs
Xilinx Confidential
Mitigation Survey
Cost and Benefit table
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
XTMR architecture
A
B
BEFORE
COMB
LOGIC
CLK
AFTER
COMB
LOGIC
MAJORIY
VOTER
A
B
CLK
MINORITY
VOTER
COMB
LOGIC
MAJORIY
VOTER
MINORITY
VOTER
COMB
LOGIC
MAJORITY
VOTER
Xilinx Confidential
MINORITY
VOTER
TMRTool
Result of Xilinx/Sandia National Labs partnership
An Application that will automatically implement TMR
techniques on a user design
Allows user to implement custom TMR logic
Support all design entry methods and HLLs
NGO & NGC based input
EDIF based output
OS Support
Windows 2000/XP GUI Support
Windows/UNIX PERL Command Line Support
Linux TBD
Supports ISE 9.2i, will support ISE10.1i by Q1CY09
Production Release : Now (TMRtool10.1i available by Feb09)
Xilinx Confidential
Design Flow
MAP
PAR
BitGen
It is recommended to run Step1 up to the design validation

and come back to Step2 of TMRtool design flow
Xilinx Confidential
OUTLINE
Xilinx introduction
Products overview
Avionics solutions
Products offering
Space solutions
Product offering
Summary
Xilinx Confidential
Summary
Leading commercial technology has been leveraged for the
Aerospace and Defense Industries:
Density, performance, and reconfigurability
Established Military/High Reliability manufacturing flows
Comprehensive SEE Characterization:
Static SEU characterization of all internal storage and control cells

Dynamic functional & transient response and SEFI/error mechanisms
quantified/characterized
Full public disclosure of all test results through the SEE Consortium
Mitigation methods evaluated, demonstrated, and verified

RadHard by Design program initiated
Increase hardness levels and eliminate SEFI modes and the requirements for TMR
Techniques developed for the Space community synergistic with Avionics and
Terrestrial requirements for future technologies
Xilinx Confidential
Xilinx Confidential

04 Silica Xilinx

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XILINX Aerospace solutions

Olivier MEHAIGNERIE / SILICA

Pioneer of the fabless semiconductor model

50% PLD market segment share

Xilinx Patent Hall

2008-12-02_Xilinx-CNES CCT FPGA-JLM 4

30% higher performance *

Digital Convergence Drives Demand

2008-12-02_Xilinx-CNES CCT FPGA-JLM 6

2008-12-02_Xilinx-CNES CCT FPGA-JLM 8

ISE Design Suite 10.1

Electronic fulfillment for fast access to updates to updates and evaluation

2008-12-02_Xilinx-CNES CCT FPGA-JLM 9

Intellectual Property Cores

LogiCORE (from Xilinx)

Advantage over hard IP

Library of >400 blocks

2008-12-02_Xilinx-CNES CCT FPGA-JLM 10

Example IP for Virtex-5 Platform FPGAs

3 Product Families: CPLDs + Spartan + Virtex

High Reliability Products

Aerospace & Defense introduction

Xilinx Continuous Commitment

2008-12-02_Xilinx-CNES CCT FPGA-JLM 13

Source: Company reports

Xilinx in Aerospace & Defense

2nd Largest vertical segment within Xilinx

Flexible and Reconfigurable

2008-12-02_Xilinx-CNES CCT FPGA-JLM 15

Xilinx Aerospace & Defense

PowerPC processor cores

SWAP-C: Reduced size, weight, power and cost

Optimized Platforms Save Cost

For Highest Density & Pin-count Appls

Spartan-3A DSP Platform

Virtex-5 FPGA Family

DSP and memoryProcessing and memoryintensive apps w/ lowintensive apps w/

2008-12-02_Xilinx-CNES CCT FPGA-JLM 19

Xilinx FPGA roadmap

Greater Logic capacity

Flexible On-Chip Memory

2008-12-02_Xilinx-CNES CCT FPGA-JLM 20

Terrestrial SEE testing

SRAM Cell SEU Simulations

2008-12-02_Xilinx-CNES CCT FPGA-JLM 23

Accelerated SEE testing

Virtex-II became Calibration component

Low Noise Underground Testing

200 Virtex-IIpro 130nm

100 Virtex-5 / 65nm

300 Virtex-5 / 65nm

The Rosetta (SEU) Stone

RTCA DO-254 / EUROCAE ED-80

RTCA: Requirements and Technical Concepts for Aviation

Design Assurance Guidance for Airborne Electronic Hardware (AEH)

Represents a consensus of best practices for aviation

2008-12-02_Xilinx-CNES CCT FPGA-JLM 30

DO-254 FPGA Design flow

Place & Route

System Safety Analysis

HW Design: RTL design, Synthesis, P&R

2008-12-02_Xilinx-CNES CCT FPGA-JLM 31

HAS: Identify & Justify Deviations vs PHAC.

Challenges for Designing