323-1521-102.r06 Circuit Pack Descriptions

323-1521-102
Nortel Networks
OPTera Connect DX
optical switch
Circuit Pack Descriptions
Standard Rel 6 Issue 1 April 2004
Whats inside...
Circuit pack descriptions
Copyright 20002004 Nortel Networks, All Rights Reserved

The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in
writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose the information only to
its employees with a need to know, and shall protect the information, in whole or in part, from disclosure and dissemination to third
parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except
as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein.
Nortel Networks, the Nortel Networks logo, the Globemark, OPTera, and Preside are trademarks of Nortel Networks.
Printed in Canada and in the United Kingdom
iii
Contents
About this document

v
1-1
Circuit pack LEDs 1-4

Optical interface circuit pack LEDs 1-5
Quad T/R interfaces (NTCA33, NTCA36) 1-7
HD OC-3 T/R interfaces (NTCA35AA, NTCA35AB) 1-13
OC-12 half-height T/R interface (NTCA31B) 1-18
OC-48 short reach T/R interface (NTCA30AL/CK) 1-22
OC-48 long reach T/R interface (NTCA30AN) 1-26
OC-48 DWDM T/R interface (NTCA30xK) 1-30
Quad OC-48 T/R interfaces (NTWR31) 1-34
Dual OC-48 short reach T/R interface (NTWR30AA) 1-38
Dual OC-48 intermediate reach T/R interface (NTWR30BA) 1-41
Dual OC-48 long reach T/R interface (NTWR30CA) 1-44
STS-48 T/R electrical interface (NTCA34) 1-47
Dual Gigabit Ethernet extended reach interface (NTCA90GA) 1-49
Dual Gigabit Ethernet long reach interface (NTCA90CA) 1-55
Dual Gigabit Ethernet short reach interface (NTCA90EA) 1-61
OC-192 T/R interface (NTCA06) 1-67
OC-192 DWDM TriFEC T/R interface (NTCF06) 1-74
OC-192 short reach T/R interface (NTWR06AB) 1-78
OC-192 intermediate reach T/R interface (NTWR06CA) 1-82
OC-192 long reach T/R with APD interface (NTWR06B) 1-86
OC-192 XR (NTCA04) 1-90
OC-192 merged XR/WT (NTCF04) 1-94
OC-192 DWDM transmit interface (NTCA01) 1-99
OC-192 DWDM regenerator/transmit interface (NTCA03) 1-103
OC-192 short reach receive interface (NTCA02) 1-106
OC-192 demultiplexer (NTCA05) 1-110
Switch module (NTCA26, NTCA24) 1-113
MOR (NTCA11) 1-123
MOR Plus (NTCA11) 1-129
Partitioned OPC 1-134
OPC controller (NTCA50) 1-136
OPC interface (NTCA52) 1-139
OPC storage (NTCA51AA and NTCA51AB) 1-142
OPC removable media (NTCA53) 1-145
Orderwire (NTCA47) 1-146
Circuit Pack Descriptions 323-1521-102 Rel 6 Iss 1 Standard Apr 2004
iv Contents
Shelf controller (NTCA41) 1-146
Maintenance interface (NTCA42) 1-151
External synchronization interface (NTCA44, NTCE44)
Message exchange (NTCA48) 1-160
Parallel telemetry (NTCA45AA) 1-163
Breaker/filter module (NTCA40AA) 1-166
Fan module (NTCA85BA, NTCA85EA) 1-169
Filler card (NTCA49/59) 1-172
1-155
OPTera Connect DX optical switch 323-1521-102 Rel 6 Iss 1 Standard Apr 2004
About this document

This document describes the OPTera Connect DX optical switch (referred to
as OPTera Connect DX in this document) and OC-192 circuit packs.
Audience
The following members of your company are the intended audience of this
Nortel Networks technical publication (NTP):
planners
provisioners
network administrators
transmission standards engineers
vi About this document
OPTera Connect DX SONET NTP Library

Planning a
Network
Installing,
Commissioning and
Testing a Network
Managing and
Provisioning
a Network
Maintaining and
Troubleshooting
a Network
Supporting
documentation for
the OPTera
Connect DX
SONET Library
Application Guide for
OPTera Connect DX
using OPTera Metro
5200 OFA
(NTCA69ZB)
Change Application
Procedures
(CAPs)
About the OPTera

Connect DX SONET
NTP Library
(323-1521-090)
OPTera Connect DX
SONET Planning and
Ordering Guide
(NTRR10DG)
SONET Orderwire
User Guide
(NTCA66CA)
Network Interworking
Guide
(NTCA68CA)
Network
Interoperability Guide
(NTCA68CB)
Data Communications
Network Planning
Guide
(NTR710AM)
Gigabit Ethernet
Data User Guide
(NTCA65YA)
SONET Network
Element Deployment
Guide
(NTCA67CG)
User Interface
Connection Procedures
(323-1521-301)
Installation
Procedures
(323-1521-201)
External Interface
Configuration
Procedures
(323-1521-302)
Powering up and
Commissioning
Procedures
(323-1521-220)
Software
Administration
Procedures
(323-1521-303)
System
Commissioning and
Testing Procedures
(323-1521-222)
Data Administration
Procedures
(323-1521-304)
Security Management
Procedures
(323-1521-305)
Performance
Monitoring Procedures
(323-1521-520)
Trouble Clearing and
Module Replacement
(323-1521-543)
Log Reference
(323-1521-840)
OC-3/OC-12 NE TBM
NTP Library
OC-48 DWDM
Tributary Application
Note
(NTRR12AC)
OC-48 Lite Multiplexer
NTP Library
OC-48 NTP Library
OPTera Long Haul

1600 NTP Library
OPTera Metro
Connect SONET
User Guide
(NTCA69XA)
Provisioning and
Operations Procedures
(323-1521-310)
Protection
Switching Description
and Procedures
(323-1521-311)
Optical Networks
Applications Library
Circuit
Pack Descriptions
(323-1521-102)
TL1 Interface
Description
(323-1521-190)
NE User Interface
Description
(323-1521-195)
OPC User Interface
Description
(323-1521-196)
Preside
documentation
About this document vii
References
This document refers to the following Nortel Networks technical publications
(NTPs) that are specific to the OPTera Connect DX NTP Library:
SONET Planning and Ordering Guide NTRR10DG
This document refers to the following supporting documentation:
OC-48 DWDM Tributary Application Note (NTRR12AC)
Optical Networks Applications Library (NTCA66BA)
OPTera Long Haul 1600 Release 7 Repeater NE Network Application
Guide (NTY316AG)
viii About this document
1-1
1-
This chapter describes the circuit packs that are supported in the OPTera
Connect DX and OC-192 network elements, and Regenerators (Regens). Each
description includes a functional block diagram and a mechanical view of the
circuit pack.
In the circuit pack descriptions contained in this chapter, the transmit
direction is from line to tributary. The receive direction is from tributary to
line.
Note: References to OC-192 network elements in this chapter are to
OC-192 network elements running OPTera Connect DX software.
Table 1-1 lists the circuit packs supported in the OPTera Connect DX and
OC-192 network elements and Regenerators. For a full description of the
variants of each circuit pack supported in the OPTera Connect DX network
element, refer to SONET Planning and Ordering Guide NTRR10DG . For a
full description of the variants of each circuit pack supported on the OC-192
network element and Regenerator, refer to SONET Planning and Ordering
Guide NTRR10DG.
1-2 Circuit pack descriptions

Table 1-1
Summary of circuit pack usage
Circuit pack
PEC
Tributaries
Quad OC-3 transmit/receive (T/R) interface with
one SDCC
NTCA33B
Quad OC-3 T/R interface with four SDCC
NTCA33C
Quad OC-12 T/R interface with one SDCC
NTCA36B
Quad OC-12 T/R interface with four SDCC
NTCA36C
Hexadeca (HD) OC-3 T/R interface with 0 SDCC NTCA35AA
OPTera OC-192 Regen Page

Connect
DX
1-7
1-7
1-7
1-7
1-13
HD OC-3 T/R interface with 16 SDCC
NTCA35AB
OC-12 half-height T/R interface
NTCA31B
OC-48 short reach T/R interface
NTCA30AL/CK
OC-48 long reach T/R interface
NTCA30AN
OC-48 DWDM T/R interface
NTCA30xK
Quad OC-48 short reach T/R interface
NTWR31AB
Quad OC-48 intermediate reach T/R interface
NTWR31BA
Dual OC-48 short reach T/R interface
NTWR30AA
Dual OC-48 intermediate reach T/R interface
NTWR30BA
Dual OC-48 long reach T/R interface
NTWR30CA
STS-48 electrical T/R interface
NTCA34
Dual Gigabit Ethernet (GE) long reach (ZX)

interface
NTCA90GA
Dual Gigabit Ethernet (GE) long reach (LX)

interface
NTCA90CA
1-55
Dual GE short reach (SX) interface
NTCA90EA
1-61
Line
OC-192 T/R interface
NTCA06
OC-192 DWDM triple forward error correction

(TriFEC) T/R interface
NTCF06
OC-192 short reach T/R interface
NTWR06AB
OC-192 intermediate reach T/R interface
NTWR06CA
OC-192 long reach T/R with Avalanche Photo

Diode (APD) interface
NTWR06Bx
OC-192 XR interface
NTCA04
OC-192 merged XR/WT interface
NTCF04
1-13
1-18
1-22
1-26
1-30
1-34
1-34
1-38
1-41
1-44
1-47
1-49
1-67
1-74
1-78
1-82
1-86
1-90
1-94
Circuit pack descriptions 1-3

Table 1-1 (continued)
Circuit pack
PEC
OC-192 DWDM transmit interface
NTCA01
OC-192 DWDM Rg/Tx interface
NTCA03
OC-192 short reach receive interface
NTCA02
OC-192 demultiplexer
NTCA05
Switch modules
DX65 switch module
NTCA26AA
DX100 switch module
NTCA26BA
DX140 switch module
NTCA26CA
DOS switch module
NTCA24

Connect
DX
MOR and MOR Plus circuit packs

MOR
NTCA11AK
NTCA11BK
NTCA11CK
MOR plus
NTCA11NK
NTCA11PK
NTCA11JK
NTCA11KK
Control shelf
OPC controller
NTCA50BA
OPC interface
NTCA52AA
OPC storage
NTCA51AA
NTCA51AB
OPC removable media
NTCA53AA
NTCA53BA
Orderwire
NTCA47AA
Shelf controller
NTCA41BA
NTCA41CA
Maintenance interface (MI)
NTCA42AA
NTCA42BA
1.544 Mbit/s External synchronization interface

(ESI)
NTCA44AA
2 Mbit/s/2 MHz External synchronization interface NTCE44AA

(ESI)
2 MHz External synchronization interface (ESI)
NTCE44BA
Message exchange (MX)
NTCA48AA
1-99
1-103
1-106
1-110
1-113
1-113
1-113
1-113
1-129
1-136
1-139
1-142
1-145
1-146
1-146
1-151
1-155
1-123
1-155
1-155
1-160

Table 1-1 (continued)
Circuit pack
PEC

Connect
DX
Parallel telemetry
NTCA45AA
Breaker/filter module
NTCA40AA
NTCA40BA
Fan module
NTCA85BA
NTCA85EA
Filler card (transport shelf - tributary or line)
NTCA49AA
Filler card (double-width switch module slot)
NTCA49AB
Filler card (single, half-height)
NTCA49AC
Filler card (Control shelf)
NTCA59AA
1-163
1-166
1-169
1-172
1-172
1-172
1-172
Circuit pack LEDs

Two or more LEDs are present on each OPTera Connect DX circuit pack to
indicate the status of the circuit pack. A green LED indicates that the circuit
pack is active and a red LED indicates a failure (an Autoprovisioning
mismatch alarm can also turn the red LED on).
See Figure 1-1 for the circuit pack LED symbols.
CAUTION
Risk of service interruption
Do not take any trouble clearing actions based only on

the LED states. Always review the active alarms and
follow the required alarm-clearing procedures. Before
you remove a circuit pack, use the NE UI to make sure
that the circuit pack does not carry any live traffic.
Red LED
Each circuit pack has a red LED. When on, the red LED indicates that there is
a provision mismatch or the circuit pack is partially or completely failed. The
red LED turns off when the circuit pack is out of service.
Yellow LED
Only circuit packs that receive a signal external to the shelf (for example the
OC-192 T/R interface) have a yellow LED. When on, the yellow LED
indicates a loss of signal (LOS) condition on the circuit pack where the signal
terminates. The facility state has an effect on the yellow LED. When the
facility is out of service, the yellow LED turns off.
Note: For the Dual GE circuit pack, when the yellow LED is on this
indicates an LOS condition or auto-negotiation issue.
Green LED
When on, this LED indicates the service providing status of the circuit pack.
Normally the green LED is off when the red LED is on. If there is an
unprotected failure on the circuit pack, both the green and red LEDs are on.
Figure 1-1
Circuit pack LED symbols for OPTera Connect DX bay
F3189
Yellow
Red
FW-3189
Green
Optical interface circuit pack LEDs

Table 1-2 lists the number of LEDs on optical interface circuit packs.
Table 1-2
Number of LEDs on optical interface circuit packs
Circuit pack
Number of LEDs
Dual GE
Quad OC-3
HD OC-3
Quad OC-12
OC-48
STS-48
Dual OC-48
Quad OC-48
OC-192 T/R
Each optical interface circuit pack, except the HD OC-3 circuit pack, includes
the following LEDs:
one red LED
one green LED
one yellow LED for each port
The HD OC-3 circuit pack includes the following LEDs:

two yellow LEDs (one yellow LED for ports 1 though 8, and one yellow
LED for ports 9 through 16)
Note: When on, a yellow LED indicates that at least one of the 8
corresponding ports has an LOS.
2 green circular LEDs that indicate the status of receive traffic only (one
green circular LED for ports 1 through 8, and one green circular LED for
ports 9 through 16)
Note: When on, a green circular LED indicates that at least one of the 8
corresponding ports is in service and carrying traffic.
one green rectangular LED that indicates the service providing status of the
circuit pack.
Quad T/R interfaces (NTCA33, NTCA36)

The Quad transmit/receive (T/R) interfaces include:
four low-speed interface circuits for processing SONET based traffic
a backplane interface circuit, which interfaces the tributaries with the
switch modules
a distributed processing control architecture
The main transport shelf (and the extension shelf on the OPTera Connect DX
bay) can contain the following types of Quad circuit pack:
Quad OC-3 T/R interface (NTCA33Bx) with one section data
communications channels (SDCC)
Quad OC-3 T/R interface with four SDCC (NTCA33Cx)
Quad OC-12 T/R interface with one SDCC (NTCA36Bx)

Quad OC-12 T/R interface with four SDCC (NTCA36Cx)
Note: The Quad OC-3 and Quad OC-12 circuit packs operate as Class 1
laser devices (IEC hazard level 1).
The NTCA33, and NTCA36 interfaces have a vertically mounted handling

tray that provides access to the optical fiber connections for connector
cleaning.
The Quad OC-3 and Quad OC-12 interfaces with one SDCC (NTCA33B and
NTCA36B) support SDCC on port 1 and line DCC (LDCC) on port 2. The
Quad OC-3 Quad OC-12 interfaces (NTCA33C and NTCA36C) supports
SDCC on all four ports and line DCC (LDCC) on port 1.
In OPTera Connect DX and OC-192 network elements running OPTera
Connect DX Release 4 or earlier, circuit packs NTCA33C and NTCA36C
provide SDCC on port 1 only. In OPTera Connect DX and OC-192 network
elements running OPTera Connect DX Release 4.1 or later, circuit packs
NTCA33C and NTCA36C provide SDCC on all four ports.
The Quad T/R interface circuit pack performs the following functions:
provide OC-12 or OC-3 transmit and receive facility terminations
process overhead
perform performance monitoring
synchronize data to shelf timing
Figure 1-2 and Figure 1-3 show functional block diagrams for the Quad optical
interface circuit packs. Figure 1-4 shows an external view of a Quad optical
interface circuit pack. Except for the identification label, both types of Quad
optical interface circuit pack have the same external appearance.
Transmit direction
The bidirectional backplane interface (BIBI) receives data inputs from switch
module A or switch module B, depending on which is active. Each input
consists of four 622 Mbit/s data streams. Switch modules A and B form a
working and protection pair.
The BIBI divides the 311 MHz backplane clock down to 19 MHz and uses this
as reference for the phase-locked loop (PLL). The PLL contains a 155 MHz
voltage-controlled crystal oscillator (VCXO) that provides 19 MHz and
39 MHz timing for the circuit pack. The BIBI demultiplexes the 622 Mbit/s
serial data streams down to byte-wide 78 Mbit/s data streams for four STS-3
or STS-12 channels.
The BIBI passes the byte-wide 78 Mbit/s data to each of the four overhead
processor and synchronizer (OOPS) circuits together with a 78 MHz clock.
The OOPS inserts the line and section overhead.
Following overhead processing, the OOPS scrambles the data to remove long
sequences of 1s or 0s, and outputs the data as:
eight 78 Mbit/s data streams (STS-12 interface circuit packs)
eight 19 Mbit/s data streams (STS-3 interface circuit packs)
Each OOPS passes the tributary data to an associated tributary interface
circuit.
The electro-optical interface (EOI) circuits perform electrical to optical
conversion. Each EOI contains the following circuits:
A SONET transmit interface (STX) multiplexes the parallel data from the
OOPS into a serial data stream. The serial output is:
622 Mbit/s for the OC-12 interface circuit packs
155 Mbit/s for the OC-3 interface circuit packs
A laser driver accepts the data stream and generates a modulation current
to drive the laser diode module (LDM). The laser driver provides a bias
current to maintain the LDM at the correct bias threshold.
The LDM converts the electrical data stream into an amplitude modulated
optical output for transmission.
Receive direction
The photodiode module (PDM) in the EOI converts the incoming optical
signal into an electrical signal. For OC-3 interfaces, the incoming signal is
155 Mbit/s. For OC-12 interfaces the input is at 622 Mbit/s. The PDM drives
a post amplifier through a low pass filter, which limits the bandwidth of the
receive channel. The SONET receive interface (SRX) demultiplexes the signal
into a byte-wide parallel output with a recovered clock and parity. For the
OC-3 optical interfaces the byte-wide parallel output is at 19 Mbit/s. For the
OC-12 optical interfaces, the parallel output is at 78 Mbit/s.
Each OOPS receives the signal from the EOI. The main functions of the OOPS
are as follows:
synchronize the incoming optical fiber data to system (shelf) timing
terminate and process the transport overhead
monitor the path overhead
pass the output as 78 Mbit/s byte-wide data to the BIBI
Note: This output is 78 Mbit/s byte-wide for all versions of the circuit
pack. The Quad OC-3 interfaces use only 25% of the data.
The BIBI multiplexes the incoming byte-wide data from the four OOPS
circuits to four 622 Mbit/s serial data streams. The BIBI produces two groups
of four 622 Mbit/s outputs. One group goes to switch module A and the other
to switch module B. The OOPS then sends the data to the switch modules by
way of the shelf backplane.
Support circuits
Four circuits support the Quad OC-12 and Quad OC-3 T/R interfaces, they are
as follows:
the EOI controller
the transport control subsystem, second generation (TCS+)
the phase-locked loop (PLL)
the point-of-use power supply (PUPS)
The EOI controller subsystem monitors control signals from the Rx and Tx
channels. The EOI controller also provides status and alarm information to the
TCS+ processor through a synchronous serial peripheral interface (SPI).
The TCS+ provides performance monitoring, fault handling, propagation of
status information to the shelf controller, and circuit pack provisioning.
The PLL uses the backplane clock to the BIBI to produce the 19 MHz clock.
The PLL provides system timing to the circuit pack. The PUPS uses the 48 V
battery voltage from the shelf to produce the supplies required by the Quad T/R
interface.

Figure 1-2
Quad OC-3 T/R optical interface block diagram
DX1382_SONET
To
backplane
TCS+
SPI
EOI controller
Analog MUX
622Mbit/s data from the Switch Modules
155 Mbit/s
78 Mbit/s
Tx data 1
8
Data 1
Data 3
A
Data 2
Data 4
78 Mbit/s
Rx data 1
311 MHz
8
CLK1
19 Mbit/s
Tx data
8
STX
Laser
driver
SRX
Post 155 Mbit/s LP

amp
filter
OOPS 1
Rx data
EOI 1
19 Mbit/s
8
OC-3
Photo
diode
module
155 Mbit/s
311 MHz
Tx data 2
Data 1
Data 3
Data 2
Data 4
Rx data 2
CLK2
78 Mbit/s
19 Mbit/s
Tx data
OOPS 2
78 Mbit/s
Rx data
19 Mbit/s
8
SRX
8
19 Mbit/s
8
SRX
Laser
driver
EOI 4
STX
SRX
Post 155 Mbit/s LP

amp
filter
OC-3
Laser
diode
module
OC-3
Photo
diode
module
OC-3
Laser
diode
module
OC-3
Photo
diode
module
Clamp
Legend
=
=
=
=
=
=
=
=
=
=
EOI 3
Post 155 Mbit/s LP
amp
filter
155 Mbit/s
78 Mbit/s
Tx data 4
Tx data 19 Mbit/s
8
Data 1
8
Data 3
OOPS 4
Data 2
Data 4
78 Mbit/s
19 Mbit/s
Rx data
Rx data 4
8
8
155 MHz
VCXO
BIBI
EOI
LP
OOPS
PLL
PUPS
SRX
STX
TCS
VCXO
Laser
driver
STX
CLK2
PLL
OC-3
Photo
LP
diode
filter module
Post
amp
155 Mbit/s
19 Mbit/s
CLK1
OC-3
Laser
diode
module
EOI 2
Tx data 3 78 Mbit/s
Tx data
8
Data 1
Data
3
OOPS
3
A
Data 2
Data 4
78 Mbit/s
Rx data
Rx data 3
311 MHz
8
311 MHz
Laser
driver
STX
BIBI
622Mbit/s data to the Switch Modules
OC-3
Laser
diode
module
Bi-directional backplane interface

Electro-optical interface
Low pass
OC-3 overhead processor and synchronizer
Phase-locked loop
Point-of-use power supply
SONET receive interface
SONET transmit interface
Transport control subsystem, 2nd generation
Voltage controller crystal oscillator
+5.0V
-48V
PUPS
+3.3V
BATRET
DC to DC
converter
-4.5V
Board
power
rails

Figure 1-3
DX1381_SONET
To
backplane
TCS+
SPI
EOI controller
Analog MUX
622Mbit/s data from the Switch Modules
622 Mbit/s
78 Mbit/s
Tx data 1
8
Data 1
Data 3
A
Data 2
Data 4
78 Mbit/s
Rx data 1
311 MHz
8
CLK1
78 Mbit/s
Tx data
8
STX
Laser
driver
SRX
Post 622 Mbit/s LP

amp
filter
OOPS 1
Rx data
EOI 1
78 Mbit/s
8
Photo
diode
module
622 Mbit/s
311 MHz
Tx data 2
Data 1
Data 3
Data 2
Data 4
Rx data 2
CLK2
78 Mbit/s
8
78 Mbit/s
Tx data
8
OOPS 2
78 Mbit/s
Rx data
78 Mbit/s
8
SRX
Tx data 3 78 Mbit/s
8
Data 1
Data 3
OOPS 3
A
Data 2
Data 4
78 Mbit/s
Rx data
Rx data 3
311 MHz
8
78 Mbit/s
8
SRX
78 Mbit/s
Tx data 4
Tx data 78 Mbit/s
8
Data 1
8
Data 3
OOPS 4
Data 2
Data 4
78 Mbit/s
78 Mbit/s
Rx data
Rx data 4
8
8
Laser
driver
EOI 4
STX
SRX
Post 622 Mbit/s LP

amp
filter
Photo
diode
module
Laser
diode
module
Photo
diode
module
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
+5.0V
-48V
PUPS
Legend
=
=
=
=
=
=
=
=
=
=
EOI 3
Post 622 Mbit/s LP
amp
filter
Laser
diode
module
OC-12
Clamp
155 MHz
VCXO
BIBI
EOI
LP
OOPS
PLL
PUPS
SRX
STX
TCS
VCXO
Laser
driver
622 Mbit/s
CLK2
PLL
EOI 2
Photo
Post 622 Mbit/s LP
diode
amp
filter module
STX
CLK1
Laser
diode
module
622 Mbit/s
78 Mbit/s
Tx data
8
311 MHz
Laser
driver
STX
BIBI
622Mbit/s data to the Switch Modules
Laser
diode
module
Bi-directional backplane interface

Low pass
OC-12 overhead processor and synchronizer
Phase-locked loop
SONET receive interface
SONET transmit interface
Transport control subsystem, 2nd generation
Voltage controller crystal oscillator
+3.3V
BATRET
DC to DC
converter
Board
power
rails
-4.5V

Figure 1-4
Quad T/R optical interface circuit pack (external view)
DX0410
Fiber carrier
Latch
Carrier
handles
Optical
connectors
1-2 3-4
QUAD
OC-12
STM-4
T/R
D
QUA 2
1
OC- 4
M
T
S
T/R
OUT 3
IN
OUT 4
IN
Carrier
handle
OUT
IN
OUT
IN
1
2
3
4
1
2
3
4
Latch
Dual fiber
cables
Side view
Front view
HD OC-3 T/R interfaces (NTCA35AA, NTCA35AB)

Note: The hexadeca (HD) transmit/receive (T/R) interface circuit pack is
used in OPTera Connect DX bays only.
The HD OC-3 T/R interface is a high density, tributary circuit pack that can
process up to 16 facilities at OC-3 rates, allowing access to 2.5 Gbit/s of
bandwidth.
The shelf can contain the following types of HD circuit pack.
HD OC-3 T/R optical interface (NTCA35AA):
This circuit pack does not support SDCC, unidirectional path switched ring
(UPSR) configuration, and intermediate path performance monitoring
(IPPM).
HD OC-3 T/R optical interface with 16 section data communications
channels (SDCC) (NTCA35AB):
This circuit pack supports SDCC, unidirectional path switched ring
(UPSR) configuration, and intermediate path performance monitoring
(IPPM).
Figure 1-5 shows an interface block diagram of the HD OC-3 T/R optical
interface (NTCA35AA). Figure 1-6 shows an interface block diagram of the
HD OC-3 T/R optical interface with 16 SDCC (NTCA35AB). Figure 1-7
shows an external view of an HD OC-3 T/R optical interface.
Transmit direction
The backplane receiver (BPR) in the bidirectional backplane interface (BIBI)
receives two sets of four STS-12 data streams one from switch module A and
the other from switch module B, depending on which switch module is active.
Switch modules A and B form a working and protection pair. Each STS-12
data stream is accompanied by two 311 MHz clock signals. The BPR divides
the 311 MHz backplane clock down to 19 MHz and uses this as reference for
the on-board 155.52 MHz phase-locked loop (PLL).
The BPR locates the frame boundary in the incoming data, performs interchip
integrity checking and then unscrambles the incoming data. The BIBI outputs
four byte-wide STS-12 data streams at 78 Mbit/s.
The PLL contains an on-board 155 MHz voltage-controlled crystal oscillator
(VCXO) and provides 38 MHz and 622 MHz timing for the circuit pack.
The BIBI passes the four byte-wide 78 Mbit/s data streams to the HEX ASIC.
Within the HEX ASIC, each OC-3 Tx circuit demultiplexes the 78 Mbit/s
STS-12 data from the BIBI down to 19 Mbit/s for the Tx framer. The framer
then formats the data into a SONET frame and inserts the section and line
overhead.
Each of the 16 serial Tx output streams pass to the daughter card. The optical
daughter card translates the scrambled serial NRZ STM-1 signal to a 1310 nm
optical signal.
Receive direction
In each of the 16 OC-3 optical interfaces, 16 optical modules receive the
optical signal and converts it to a serial STS-3 NRZ signal. Each of these
signals connects to the mother board HEX ASIC.
In the optical interface circuit packs, each Rx circuit receives the signal from
the EOI. The main functions of the Rx circuit are as follows:
synchronize the incoming optical fiber data to system (shelf) timing
terminate and process the transport overhead
monitor the path overhead
pass the output as 78 Mbit/s byte-wide data to the BIBI
The first stage of the HEX ASIC Rx circuit performs clock and data recovery
on the inputs from the 16 optical serial data streams. The deserialized and
decoded data is passed to the SONET Rx framer, which locates the SONET
frame and extracts the section and line overhead. The path overhead is
monitored, but passed through unchanged. The circuit then performs write and
read pointer processing and calculates bit interleave parity (BIP).
The BIBI converts the incoming byte-wide data from the HEX ASIC to four
622 Mbit/s serial data streams. The BIBI produces two groups of four
622 Mbit/s outputs. One group goes to switch module A and the other to
switch module B. The backplane drivers (BPD) of the BIBI then sends the data
to the switch modules by way of the shelf backplane.

Figure 1-5
HD OC-3 T/R optical interface block diagram
DX2987_R3_SON
To
backplane
TCS
HEX ASIC
311 MHz
78 MHz
Clock
generation
Clock
STS-3 Rx/Tx
16 OC-3 Optical line interfaces
Data
STS-3
Tx framer
EOI-1
155.52 Mbits
NRZ Tx data
FIFO
78 MHz
4:1
622 Mbit/s
1:4
BPR
OC-3
optical
output
Laser
module
8
8
Data
CDR
STS-3
Rx framer
1:4
4:1
78 MHz
BIP
8
622 Mbit/s
Optical Rx
module
155.52 Mbits
NRZ Rx data
2
OC-3
optical
input
SD
Signal detect
8
311 MHz
BPD
Clock
generation
EOI-16
Clock
622Mbit/s data and 311 MHz clocks to/from the Switch Modules
BIBI
16 channels
+5.0V
PLL
-48V
Clamp
PUPS
155 MHz
VCXO
Legend
BIBI
BIP
BPD
BPR
CDR
EOI
FIFO
LP
+3.3V
BATRET
DC to DC
converter
= Bi-directional backplane interface

= Bit interleaved parity
= Backplane driver
= Backplane receiver
= Clock data recovery
= Electro-optical interface
= First-in first-out
= Low pass
PLL
PUPS
TCS
VCXO
Board
power
rails
+1.8V
= Phase-locked loop
= Point-of-use power supply
= Transport control subsystem
= Voltage controller crystal oscillator

Figure 1-6
HD OC-3 T/R optical interface with 16 SDCC block diagram
DX4707p
To
backplane
TCS
Line/section interface
TSDCC RLDCC
TLDCC
+clk
+clk
+clk
RSDCC
+clk
SDCC processing
2
311 MHz
78 MHz
Clock
generation
8
Clock
LDCC processing
HEX ASIC
STS-3 Rx/Tx
16 OC-3 Optical line interfaces
4
Data
STS-3
Tx framer
EOI-1
155.52 Mbits
NRZ Tx data
FIFO
78 MHz
4:1
BPR
1:4
8
622 Mbit/s
OC-3
optical
output
Laser
module
8
8
Data
CDR
STS-3
Rx framer
1:4
4:1
78 MHz
BIP
8
622 Mbit/s
Optical Rx
module
155.52 Mbits
NRZ Rx data
2
OC-3
optical
input
SD
Signal detect
8
311 MHz
BPD
Clock
generation
EOI-16
Clock
622Mbit/s data and 311 MHz clocks to/from the Switch Modules
BIBI
16 channels
+5.0V
PLL
-48V
Clamp
PUPS
155 MHz
VCXO
Legend
BIBI
BIP
BPD
BPR
CDR
EOI
FIFO
= Bi-directional backplane interface

= Bit interleaved parity
= Backplane driver
= Backplane receiver
= Clock data recovery
= Electro-optical interface
= First-in first-out
+3.3V
BATRET
DC to DC
converter
LDCC
LP
PLL
PUPS
SDCC
TCS
VCXO
= Line data communications channel

= Low pass
= Phase-locked loop
= Section data communications channel
+1.8V
Board
power
rails

Figure 1-7
HD OC-3 T/R optical interface circuit pack (external view)
DX2655p
Optical connector
(Output) Port #2
Optical connector
(Input) Port #2
Optical connector
(Output) Port #1
Optical connector
(Input) Port #1
OC-12 half-height T/R interface (NTCA31B)

Note: The half-height T/R interface is used in the OC-192 bays only.
The OC-12 transmit/receive (T/R) interface is a low-speed T/R tributary
interface. The OC-12 T/R interface circuit pack performs the following
functions:
provide OC-12 transmit and receive facility terminations
process overhead
Figure 1-8 shows a functional block diagram. Figure 1-9 shows an external
view of the OC-12 T/R interface circuit pack.
Transmit direction
In the transmit direction, the backplane receive (BPR) interface receives
622 Mbit/s data from the switch module and demultiplexes it to byte-wide
78 Mbit/s. The overhead processor and synchronizer (OOPS) receives the
data, and processes line and section overhead.
The BPR divides the 311 MHz backplane clock to 19 MHz and uses this as a
reference for the phase-locked loop (PLL) in the backplane driver (BPD).
The electro-optical interface (EOI) receives the signal from the overhead
processor and synchronizer (OOPS). The EOI contains the following circuits:
SONET transmit (STX) multiplexes the 78 Mbit/s byte-wide data from the
OOPS into a 622 Mbit/s, STS-12 data stream
a laser driver in the laser module accepts the data stream and generates a
modulation current to drive a laser diode (the laser driver provides a bias
current to maintain the laser diode at the correct threshold)
the LDM converts the electrical data stream into an amplitude modulated
OC-12 optical output for transmission
Receive direction
In the receive direction, the photodiode module in the EOI converts the
incoming OC-12 optical signal into an STS-12 electrical signal at 622 Mbit/s.
The SONET receive (SRX) demultiplexes the signal into byte-wide 78 Mbit/s
parallel output with a recovered clock and parity.
The OOPS receives the byte-wide data from the EOI, processes transport
overhead, and passes the signal to the backplane driver (BPD). The BPD
multiplexes the data to 622 Mbit/s and sends it to the switch module by way of
the shelf backplane.
Support circuits
Three circuits support the OC-12 T/R interface:
the electro-optical controller (EOC)
the transport control subsystem (TCS)
The EOC monitors control signals from the Rx and Tx channels. The EOC also
interfaces with the TCS processor through a serial interface.
The TCS provides communication between the shelf controller and the OC-12
T/R interface. The TCS also generates alarms and activates the light-emitting
diodes (LEDs) on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-12 T/R interface.

Figure 1-8
OC-12 T/R interface block diagram
DX1374_SONET
From switch
modules A and B
622 Mbit/s
A
78 Mbit/s
78 Mbit/s
311 MHz Clk

BPR
STX
622 Mbit/s
OC-12
Laser
module
622 Mbit/s
B
311 MHz Clk
OOPS
EOI
19 MHz ref
To switch
modules A and B
622 Mbit/s
A
EOC
78 Mbit/s
78 Mbit/s
311 MHz Clk
SRX
622 Mbit/s
Photo
diode
module
OC-12
BPD
622 Mbit/s
B
311 MHz Clk
To/from EOC
TCS
Active (green)
Optical signal
fail (yellow)
Fail (red)
To/from
shelf controller
+3.3 V
Legend:
BPD =
BPR =
EOC =
EOI =
OOPS =
PUPS =
SRX =
STX =
TCS =
Backplane Driver
Backplane Receive
Electro-Optical Controller
Electro-Optical Interface
Overhead Processor and Synchronizer
Point-of-Use Power Supply
SONET Receive
SONET Transmit
Transport Control Subsystem
-48 V
PUPS
+5 V

Figure 1-9
OC-12 T/R interface circuit pack (external view)
F3480-192
Optical signal
fail (Yellow)
Fail (Red)
Active(Green)
OC-48 short reach T/R interface (NTCA30AL/CK)

The OC-48 short reach (SR) transmit/receive (T/R) interface is a low-speed
tributary T/R interface that combines a 1310 nm short reach transmitter, a
positive intrinsic negative (PIN) receiver and a demultiplexer into one circuit
pack.
Note: The OC-48 SR T/R circuit pack operates as a Class 1 laser device
(IEC hazard level 1).
The OC-48 SR T/R interface circuit pack performs the following functions:
provide OC-48 transmit and receive interface ports
process the overhead
This circuit pack features a bottom latch release sensor. The sensor alerts the
system of circuit pack removal and switches the traffic if the circuit pack is
active and protection is available. Figure 1-10 shows a functional block
diagram. Figure 1-11 shows an external view of the OC-48 SR T/R interface
circuit pack.
Transmit direction
OC-48 data in the form of four 622 Mbit/s data streams from each switch
module and demultiplexes it. The transmit overhead processor (TOHP)
receives the data and then multiplexes it.
The parallel to serial (P/S) module multiplexes the signal again to provide an
STS-48 serial signal for the laser module. The 1310 nm laser module converts
the OC-48 electrical signal into an OC-48 optical signal and launches it into
the optical fiber.
Receive direction
In the receive direction, the PIN converts the incoming OC-48 optical signal
into an electrical signal. The automatic gain control (AGC) module receives
the STS-48 signal and maintains a constant output level.
The data regenerator module receives the STS-48 serial signal and
demultiplexes it into a parallel STS-48 signal. The receive overhead processor
(ROHP) receives the STS-48 signal. The ROHP finds the SONET frame and
extracts overhead and demultiplexes the data. The synchronizer (SYNC)
module receives and aligns the data with the shelf clock and then passes it to
the backplane driver (BPD). The BPD multiplexes the incoming data then
sends it to the switch module by way of the shelf backplane.
Support circuits
The following three circuits support the OC-48 SR T/R interface:
the receive (Rx) controller
The PUPS generates all the voltages required by the OC-48 SR T/R interface.
The Rx controller samples the quality of the data streams and controls the
phase adjustment of the data and the PIN bias. The Rx controller also provides
the TCS with status information.
The TCS controls the operation of the OC-48 SR T/R interface. The TCS
provides communication between the shelf controller and the OC-48 SR T/R
interface. The TCS also generates alarms and activates the LEDs on the circuit
pack faceplate.

Figure 1-10
OC-48 SR T/R interface block diagram
DX4978p
From Switch Modules

A and B
A
P/S
STS-48 Laser
module
module
TOHP
4 x 622 Mbit/s BPR
OC-48
Active
(green)
Optical signal fail
(yellow)
Fail
(red)
TCS+
Rx
Control
To/from
shelf controller
A
PIN
module
OC-48
AGC
module
Data
regenerator
module
ROHP
SYNC
module
BPD
module
B
To Switch
Modules
A and B
STS-48
Legend:
AGC
BPD
BPR
PIN
PUPS
ROHP
TCS
TOHP
SYNC
= Automatic Gain Control

= Backplane Driver
= Backplane Receive
= Positive Intrinsic Negative
= Point-of-Use Power Supply
= Receive OverHead Processor
= Transport Control Subsystem
= Transmit Overhead Processor
= Synchronizer
-48 V
PUPS
+12V
-12V
+3.3V
+5V
-5.2V

Figure 1-11
OC-48 SR T/R interface circuit pack (external view)
DX4979p
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)
OC-48 long reach T/R interface (NTCA30AN)

The OC-48 LR T/R interface is a low-speed tributary T/R interface that
combines transmit, receive and demultiplex functions in one circuit pack. The
OC-48 T/R interface circuit pack performs the following functions:

diagram. Figure 1-13 shows an external view of the OC-48 LR T/R interface
circuit pack.
Transmit direction
STS-48 serial signal for the external modulated DFB laser module. The
external modulated DFB laser module converts the OC-48 electrical signal
into an OC-48 optical signal with a wavelength locked to an ITU-T grid and
launches it into the optical fiber.
Receive direction
In the receive direction, the avalanche photodiode (APD) converts the
incoming OC-48 optical signal into an electrical signal. The automatic gain
control (AGC) module receives the STS-48 signal and maintains a constant
output level.
Support circuits
The following three circuits support the OC-48 LR T/R interface:
The PUPS generates all the voltages required by the OC-48 LR T/R interface.
phase adjustment of the data and the APD bias. The Rx controller also provides
The TCS controls the operation of the OC-48 LR T/R interface. The TCS
provides communication between the shelf controller and the OC-48 LR T/R
interface. The TCS also generates alarms and activates the LEDs on the circuit
pack faceplate.

Figure 1-12
OC-48 LR T/R interface block diagram
DX1375_SONET
From Switch Modules

A and B
A
P/S
STS-48 Laser
module
module
TOHP
4 x 622 Mbit/s BPR
OC-48
Active
(green)
Optical signal fail
(yellow)
Fail
(red)
TCS+
Rx
Control
To/from
shelf controller
A
APD
module
OC-48
AGC
module
Data
regenerator
module
ROHP
SYNC
module
BPD
module
B
To Switch
Modules
A and B
STS-48
Legend:
APD
AGC
BPD
BPR
PUPS
ROHP
TCS
TOHP
SYNC
= Avalanche Photo-Detector
= Backplane Driver
= Backplane Receive
= Synchronizer
-48 V
PUPS
+12V
-12V
+3.3V
+5V
-5.2V

Figure 1-13
OC-48 LR T/R interface circuit pack (external view)
DX4979p
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)
OC-48 DWDM T/R interface (NTCA30xK)

The OC-48 DWDM T/R interface is a low-speed tributary T/R interface that
combines transmit, receive and demultiplex functions in one circuit pack. The
OC-48 T/R interface circuit pack performs the following functions:
diagram. Figure 1-15 shows an external view of the OC-48 DWDM T/R
interface circuit pack.
Transmit direction
STS-48 serial signal for the external modulated DFB laser module. The
external modulated DFB laser module converts the OC-48 electrical signal
into an OC-48 optical signal with a wavelength locked to an ITU-T grid and
launches it into the optical fiber.
Receive direction
In the receive direction, the avalanche photodiode (APD) converts the
incoming OC-48 optical signal into an electrical signal. The automatic gain
control (AGC) module receives the STS-48 signal and maintains a constant
output level.
OC-48 DWDM T/R wavelengths

For information on the variants of this circuit pack refer to SONET Planning
and Ordering Guide NTRR10DG.
For information on OC-48 DWDM tributary applications, refer to the OC-48
DWDM Tributary Application Note (NTRR12AC).
Support circuits
The following three circuits support the OC-48 DWDM T/R interface:
The PUPS generates all the voltages required by the OC-48 DWDM T/R
interface.
phase adjustment of the data and the APD bias. The Rx controller also provides
The TCS controls the operation of the OC-48 DWDM T/R interface. The TCS
provides communication between the shelf controller and the OC-48 DWDM
T/R interface. The TCS also generates alarms and activates the LEDs on the
circuit pack faceplate.

Figure 1-14
OC-48 DWDM T/R interface block diagram
DX1375_SONET
From Switch Modules

A and B
A
P/S
STS-48 Laser
module
module
TOHP
4 x 622 Mbit/s BPR
OC-48
Active
(green)
Optical signal fail
(yellow)
Fail
(red)
TCS+
Rx
Control
To/from
shelf controller
A
APD
module
OC-48
AGC
module
Data
regenerator
module
ROHP
SYNC
module
BPD
module
B
To Switch
Modules
A and B
STS-48
Legend:
APD
AGC
BPD
BPR
PUPS
ROHP
TCS
TOHP
SYNC
= Avalanche Photo-Detector
= Backplane Driver
= Backplane Receive
= Synchronizer
-48 V
PUPS
+12V
-12V
+3.3V
+5V
-5.2V

Figure 1-15
OC-48 DWDM T/R interface circuit pack (external view)
DX4979p
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)
Quad OC-48 T/R interfaces (NTWR31)

The Quad OC-48 transmit/receive (T/R) interfaces include:
four low-speed interface circuits for processing SONET based traffic
a backplane interface circuit, which interfaces the tributaries with the
switch modules
a distributed processing control architecture
The universal slots on main transport shelf can contain the following types of
Quad OC-48 circuit pack:
Quad OC-48 short reach T/R interface (NTWR31AB)
Quad OC-48 intermediate reach T/R interface (NTWR31BA)
Note: The Quad OC-48 circuit packs operate as Class 1 laser devices (IEC
hazard level 1).
The Quad OC-48 transmit/receive (T/R) interfaces have a vertically mounted
handling tray that provides access to the optical fiber connections for
connector cleaning.
The Quad OC-48 interfaces (NTWR31AB/BA) support SDCC and LDCC on
all four ports.
The Quad OC-48T/R interface circuit pack performs the following functions:
process overhead
perform performance monitoring
Figure 1-16 show functional block diagrams for the Quad OC-48 optical
interface circuit packs.Figure 1-17 shows an external view of a Quad OC-48
optical interface circuit pack. Except for the identification label, both types of
Quad OC-48optical interface circuit pack have the same external appearance.
Transmit direction
For each independent port, the Columbo Overhead Processor/Synchronizer
(OPS) receives 622 Mbit/s data and associated 311 MHz clock from switch
module A and switch module B. The Columbo OPS selects between the two
groups of data, depending on the active switch, and provides overhead
processing (insertion) for the transmit path data. The Columbo OPS provides
nibble-wide 622 Mbit/s data and clock to the electrical transceiver which
converts the data to a 2.5 Gbit/s serial stream. The electro-optic components
convert the electrical data stream into a modulated optical output for
transmission.
Receive direction
For each independent port, the opto-electric components convert the incoming
2.5 Gbit/s optical signal into an electrical signal. The electrical transceiver
converts the serial 2.5 Gbit/s signal into nibble-wide 622 Mbit/s data and
clock. The 622 Mbit/s data and clock are provided to the Columbo Overhead
Processor/Synchronizer (OPS) which provides the SONET framing, error
monitoring, overhead processing (extraction) and shelf synchronization on the
incoming data. The Columbo OPS generates 2 copies of the data at 622 Mbit/s,
one group goes to switch module A and the other to switch module B.
Support circuits
Four circuits support the Quad OC-48 T/R interfaces, they are as follows:
Columbo Overhead Processor/Synchronizer (OPS)
Optical/Electric and Electric/Optical convertor (O/E, E/O Conversion)
clock distribution
electrical transceiver
The Columbo Overhead Processor/Synchronizer (OPS) provides the system
synchronization, SONET framing, error monitoring, and overhead processing
on a 2.5 Gbit/s data path.
The clock distribution block receives 39 MHz reference clocks from the switch
modules (A and B). The reference from the active module is used to
synchronize the clock reference on the design to the system timing. The clock
distribution block provides shelf synchronous clocks to the Columbo OPS and
the electrical transceivers.
The electrical transceiver converts the serial 2.5 Gbit/s signal into nibble-wide
622 Mbit/s data and clock.
The TCS provides performance monitoring, fault handling, propagation of
The PUPS use the -48V battery voltage from the shelf to produce the supplies
required by the Quad OC-48 interface.

Figure 1-16
DX5510p

Figure 1-17
Quad OC-48 T/R optical interface circuit pack (external view)
DX5509p
Fiber
carrier
Latch
Carrier
handles
Optical
connectors
1-2 3-4
QUAD
OC-48
STM-16
D
QUA 8
4
OC- 16
M
T
S
OUT 3
IN
OUT 4
IN
Carrier
handle
OUT
IN
OUT
IN
1
2
3
4
1
2
3
4
Latch
Dual fiber
cables
Side view
Front view
Dual OC-48 short reach T/R interface (NTWR30AA)

The Dual OC-48 short reach T/R is a full-height circuit pack that supports two
OC-48 facilities for a maximum capacity of 5.0 Gbit/s.
Note 1: The Dual OC-48 SR T/R interface circuit pack is used in OPTera
Connect DX bays running Release 4.1 or above.
Note 2: The Dual OC-48 SR T/R circuit pack operates as a Class 1 laser
device.
Figure 1-18 shows a functional block diagram of the Dual OC-48 SR T/R
interface. Figure 1-19 shows an external view of the Dual OC-48 SR T/R
Support circuits
The following three circuits support the Dual OC-48 SR T/R interface:
the electro-optics controller (EOC)
The TCS controls the operation of the Dual OC-48 SR T/R interface. The TCS
provides communication between the shelf controller and the Dual OC-48 SR
The PUPS generates all the voltages required by the Dual OC-48 SR T/R
interface.
The electro-optics controller controls the receive and transmit optical
channels. The EOC also provides the TCS with status information about the
optical control loops and alarms.

Figure 1-18
Dual OC-48 SR T/R interface block diagram
DX4003p
Dual digital card
Dual short reach optics card
PUPS
-48V
622M
622M
SYDR
311M
TCS
2xDCC
1xOH
2xDCC
1xOH
Backplane connector
Magic
FPGA
8-pin Mini DIL
311M
311M
TROHP
311M
Demux
2.5G
2.5G
Rx39M
39M
Ck Sel
MUX
2.5G
MPC860
Merge
Drvr
2.5G
311M
SYDR
8-pin Mini DIL

FP laser
8-pin Mini DIL
311M
TROHP
311M
311M
Demux
2.5G
AGC
2.5G
Rx39M
39M
SCG
622M
PIN/
Preamp
OC-48
Out SR
EOC
860
622M
622M
AGC
OC-48
In SR
Ck Sel
MUX
2.5G
M93
Drvr
2.5G
OC-48
In SR
PIN/
Preamp
8-pin Mini DIL

FP laser
OC-48
Out SR
622M
VCXO
PLL
Legend
AGC = Automatic gain control
Ck Sel = Clock selector
DIL = Dual in line
Demux = Demultiplexer
Drvr = Driver
EOC = Electro-optical controller
FP = Fabry-Perot
FPGA = Field programmable gate array
MUX = Multiplexer
PIN = Positive intrinsic negative

PLL = Phase-locked loop
PUPS = Point of use power supply
SCG = System clock generator
SR = Short reach
SYDR = Sync driver/receiver
TROHP = Transmit/receive overhead processor
VCXO = Voltage controlled crystal oscillator

Figure 1-19
Dual OC-48 SR T/R interface circuit pack (external view)
DX4693
LOS for port #1

(Yellow)
LOS for port #2
(Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output) Port #2
Optical connector
(Input) Port #2
Optical connector
(Output) Port #1
Optical connector
(Input) Port #1
Dual OC-48 intermediate reach T/R interface (NTWR30BA)

The Dual OC-48 intermediate reach (IR) T/R is a full-height circuit pack that
supports two OC-48 facilities for a maximum capacity of 5.0 Gbit/s.
Note 1: The Dual OC-48 IR T/R interface circuit pack is used in OPTera
Connect DX bays running Release 4.1 or above.
Note 2: The OC-48 IR T/R circuit pack operates as a Class 1 laser device
(IEC hazard level 1).
Figure 1-20 shows a functional block diagram of the Dual OC-48 IR T/R
interface. Figure 1-21 shows an external view of the Dual OC-48 IR T/R
Support circuits
The following three circuits support the Dual OC-48 IR T/R interface:
The TCS controls the operation of the Dual OC-48 IR T/R interface. The TCS
provides communication between the shelf controller and the Dual OC-48 IR
The PUPS generates all the voltages required by the Dual OC-48 IR T/R
interface.

Figure 1-20
Dual OC-48 IR T/R interface block diagram
DX4696p
Dual digital card
Dual optics card
PUPS
-48V
622M
622M
SYDR
311M
TCS
2xDCC
1xOH
2xDCC
1xOH
Backplane connector
Magic
FPGA
OC-48
In IR
311M
311M
TROHP
311M
Demux
2.5G
2.5G
Rx39M
39M
Ck Sel
MUX
2.5G
MPC860
Merge
Drvr
2.5G
311M
SYDR
Uncooled DFB
laser
OC-48
Out IR
OC-48
In IR
311M
TROHP
311M
311M
Demux
2.5G
AGC
2.5G
Rx39M
39M
SCG
622M
PIN/
Receiver
EOC
860
622M
622M
AGC
Ck Sel
MUX
2.5G
M93
Drvr
2.5G
PIN/
Receiver
Uncooled DFB
laser
OC-48
Out IR
622M
VCXO
PLL
Legend
DIL = Dual in line
DFB = Distributed feedback
Drvr = Driver
IR = Intermediate reach
MUX = Multiplexer
PIN = Positive intrinsic negative

Figure 1-21
Dual OC-48 IR T/R interface circuit pack (external view)
DX4693p
LOS for port #1

(Yellow)
LOS for port #2
(Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output) Port #2
Optical connector
(Input) Port #2
Optical connector
(Output) Port #1
Optical connector
(Input) Port #1
Dual OC-48 long reach T/R interface (NTWR30CA)

The Dual OC-48 long reach (LR) T/R is a full-height circuit pack that supports
two OC-48 facilities for a maximum capacity of 5.0 Gbit/s.
Note 1: The Dual OC-48 LR T/R interface circuit pack is used in OPTera
Connect DX bays running Release 5 or above.
Note 2: The OC-48 LR T/R circuit pack operates as a Class IIIb laser
device (IEC hazard level 1).
Figure 1-22 shows a functional block diagram of the Dual OC-48 LR T/R
interface. Figure 1-23 shows an external view of the Dual OC-48 LR T/R
Support circuits
The following three circuits support the Dual OC-48 LR T/R interface:
The TCS controls the operation of the Dual OC-48 LR T/R interface. The TCS
provides communication between the shelf controller and the Dual OC-48 LR
The PUPS generates all the voltages required by the Dual OC-48 LR T/R
interface.

Figure 1-22
Dual OC-48 LR T/R interface block diagram
DX4870p
Dual digital card
Dual optics card
PUPS
-48V
622M
311M
622M
SYDR
311M
TCS
2xDCC
1xOH
2xDCC
1xOH
Backplane connector
Magic
FPGA
OC-48
In LR
311M
TROHP
311M
Demux
2.5G
2.5G
Rx39M
39M
Ck Sel
MUX
2.5G
MPC860
Merge
Drvr
2.5G
311M
SYDR
Uncooled DFB
laser
OC-48
Out LR
OC-48
In LR
311M
TROHP
311M
311M
Demux
2.5G
AGC
2.5G
Rx39M
39M
SCG
622M
APD/
Receiver
EOC
860
622M
622M
AGC
Ck Sel
MUX
2.5G
M93
Drvr
2.5G
APD/
Receiver
Uncooled DFB
laser
OC-48
Out LR
622M
VCXO
PLL
Legend
APD = Avalanche photodiode
DIL = Dual in line
DFB = Distributed feedback
Drvr = Driver
LR = Long reach
MUX = Multiplexer

Figure 1-23
Dual OC-48 LR T/R interface circuit pack (external view)
DX4693p
LOS for port #1

(Yellow)
LOS for port #2
(Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output) Port #2
Optical connector
(Input) Port #2
Optical connector
(Output) Port #1
Optical connector
(Input) Port #1
STS-48 T/R electrical interface (NTCA34)

The STS-48 T/R electrical interface is a low-speed tributary transmit/receive
(T/R) interface that combines STS-48 transmit, receive and demultiplex
functions into one circuit pack. The STS-48 T/R circuit pack performs the
following functions:
provide STS-48 transmit and receive facility terminations
Figure 1-24 shows a functional block diagram. Apart from the external label,
the T/R interface circuit pack looks identical to the OC-48 T/R interface circuit
pack shown in Figure 1-11.
Transmit direction
In the transmit direction, the backplane receive (BPR) interface receives data
from the switch module and demultiplexes it. The transmit overhead processor
(TOHP) receives and multiplexes the data. The P/S module multiplexes the
signal again to provide an STS-48 serial signal that it sends through a coaxial
link.
Receive direction
The automatic gain control module (AGC) receives the STS-48 signal and
maintains a constant output level. The data regenerator module receives this
serial signal and demultiplexes it to a parallel signal. The ROHP receives the
STS-48 signal and finds the SONET frame. The ROHP also extracts overhead
and demultiplexes the data. The SYNC module receives and aligns the data
with the shelf clock, then passes the data to the BPD. The BPD multiplexes the
incoming data before sending it to the switch module by way of the shelf
backplane.
Support circuits
Three circuits support the STS-48 T/R interface:
the Rx controller
phase adjustment of the data. The Rx controller also provides the TCS with
status information.
The TCS controls the operation of the STS-48 T/R interface and TCS provides
communication with the shelf controller. The TCS also generates alarms and
activates the LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the STS-48 T/R interface.

Figure 1-24
STS-48 T/R interface block diagram
DX1369_SONET
4
A
4 x 622 Mbit/s
from Switch
modules A and B
B
BPR
P/S
module
TOHP
STS-48
Active
(green)
Optical signal fail
(yellow)
Fail
(red)
TCS+
Rx
control
To/from
shelf controller
A
STS-48
Legend
AGC
BPD
BPR
FEC
P/S
PUPS
ROHP
Rx
TCS
TOHP
SYNC
=
=
=
=
=
=
=
=
=
=
=
AGC
module
Data
regenerator
module
Automatic gain control

Backplane driver
Backplane receive
Forward error correction
Parallel to serial
Receive overhead processor
Receive
Transport control subsystem
Transmit overhead processor
Synchronizer
ROHP
SYNC
module
BPD
module
4 x 622 Mbit/s
to Switch
modules A and B
+12V
-12V
-48 V
PUPS
+3.3V
+5V
-5.2V
Dual Gigabit Ethernet extended reach interface (NTCA90GA)

The Dual Gigabit Ethernet (GE) extended reach (ZX) circuit pack allows
native Ethernet traffic to be mapped and carried in the SONET synchronous
payload envelope. This allows for Ethernet traffic to be carried over an OC-192
SONET backbone in a point-to-point configuration.
The Dual GE ZX circuit pack is a full height circuit with two independent
Ethernet ports.
Note 1: The Dual GE ZX circuit pack can only be used as an unprotected
tributary circuit pack. However, the network element in which it is
provisioned can be either protected or unprotected. Matched nodes are not
supported where the Dual GE ZX circuit pack is the gateway.
Note 2: The Dual GE ZX interface circuit pack is used in OPTera Connect
DX bays running Release 5 or above.
Figure 1-27 shows a block diagram of the Dual GE ZX circuit pack.
Figure 1-28 shows an external view of the Dual GE ZX circuit pack.
The Dual GE ZX circuit pack has the following characteristics:
two optical interfaces that support 1000Base-ZX (1550 nm) single-mode
optical fiber (80 km reach) for each port
support for IEEE 802.3 (1998) provisionable automatic negotiation and
flow control (pause frame capability in the transmit direction only)
support for transparent pass through of IEEE 802.1Q VLAN tags
support for transparent pass through of IEEE 802.1p priority fields

ability to handle Ethernet frames up to 2048 bytes
support for signal label for terminated Dual GE payloads
layer 3 transparency support for transparent pass through of routing
information protocol (RIP) and OSPF information
supports point-to-point Ethernet connection provisioning (STS-3c,
STS-6c, STS-12c or STS-24c per port)
supports mixed tributaries, subject to protection group restrictions
supports Internet Protocol (IP), according to RFC79; User Data Protocol
(UDP) according to RFC768; and, TCP according to RFC791
support for ICMP echo in accordance with RFC792
The hardware consists of the following functional blocks:

Electro-optical interfaces (EOI)
Serializer/deserializer (SERDES)
Gigabit Media Access Control (GMAC)
Dual scalable mapper (DSCAM)
Bi-directional backplane interlace (BIBI)
Transmit direction
The backplane receiver (BPR) in the BIBI receives data inputs from either
switch module A or switch module B, depending on which switch module is
active. The input from the active switch module consists of four 622 Mbit/s
data streams. The data is accompanied by two 311 MHz clocks. Switch
modules A and B form a working and protection pair.
The backplane receiver in the BIBI performs the following functions:
locates the frame boundary
performs inter-chip integrity checking
unscrambles the incoming data streams
outputs four STS-12 byte-wide data busses.
serial data streams down to four byte wide 77.76 Mbit/s data streams (referred
to as 78 Mbit/s data streams in this document) and passes these to the DSCAM
circuit.
The BPR in the BIBI extracts an 8 kHz system timing signal from the position
of the framing pattern in the incoming data and uses this as a reference signal
for the PLL. The locked outputs of the PLL are fed back into the BIBI and used
as a clock for the BPR.
The DSCAM provides point-to-point connections between the byte-wide
STS-12 outputs from the BIBI and the GMAC devices. The DSCAM uses up
to 8 Mbytes of external Synchronous Dynamic RAM (SDRAM) in the GE to
SONET direction in order to buffer frames for data bursts into a port that
supports a lower data rate. No buffering is provided in the SONET to GE
direction since there is no flow control mechanism on the SONET side. The
DSCAM uses the 8 kHz timing signal from the BIBI as a reference for pointer
processing. The DSCAM performs the following functions:
processes the SONET overhead
performs a demapping function, in which the Internet Protocol (IP) frames

are extracted from the SONET payload
sends the IP data to the GMAC devices at 78 Mbit/s
In each GMAC device, the IP data is fed into a 2 kbytes first-in-first-out

(FIFO). Using the data contained in the FIFO, the GMAC devices generate the
following as part of the outgoing Ethernet packet:
preamble
start of frame delimiter (SFD)
32-bit cyclic redundancy check (CRC) data.
An 8-bit to 10-bit encoder in each GMAC device encodes the 32-bit data
stream into 10-bit symbols, in accordance with IEEE 802.3z. A 125 MHz
clock signal from the SERDES transfers the data from each GMAC device to
the SERDES.
The SERDES accepts the two streams of 10-bit symbols at 125 Mbit/s and
serializes the data into two single 1.25 Gbit/s data streams at ports 1 and 2.
conversion. A laser driver in the EOI accepts the data stream and generates a
modulation current to drive the laser diode module (LDM). The laser driver
provides a bias current to maintain the LDM at the correct bias threshold. The
LDM converts the electrical data stream into an amplitude modulated optical
output for transmission.
Receive direction
The Dual GE ZX circuit pack receives two optical data streams at 1.25 Gbit/s.
The two data streams are applied to associated EOI circuits, which convert the
optical signals to electrical signals. The two electrical data streams are passed
to the SERDES, which deserializes the data into two parallel 10-bit outputs at
125 Mbit/s. The SERDES recovers a clock from the incoming 1.25 Gbit/s data
to produce two 62.5 MHz clocks, which are used to latch out the 10-bit data
from the SERDES to each GMAC device.
Each GMAC device accepts the input data in the form of 10-bit parallel
symbols and clocks each group of four symbols into a 40-bit register at
125 MHz. An encoder converts each group of four 10-bit symbols to 8-bit
form in accordance with IEEE 802.3z, producing a 32-bit word, which is
output every fourth clock cycle.
The GMAC device receive module operates on each incoming Ethernet frame
as follows:
removes the preamble symbols
removes the SFD
checks the frame check sequence (FCS)

checks for the correct frame length
captures the MAC control frames in the receive direction and initiates a
response along the transmit direction
captures and stores statistics from the received frames, allowing the receive
statistics to be appended to frames sent to the DSCAM
The DSCAM maps the data between the Ethernet side and the OC-12side. The
receive circuits in the DSCAM accept the 32-bit data at 78 Mbit/s from the
GMAC device and the DSCAM performs point-to-point mapping, inserting
the IP frames into the SONET payload. The DSCAM outputs four groups of
8-bit parallel data at 78 Mbit/s and passes these to the BIBI.
The outputs from the DSCAM are passed to the backplane driver (BPD)
circuits of the BIBI. The BPD has a programmable frame offset that can be
adjusted to align the SONET framing pattern with the system 8 kHz framing
pulse on the switch module. This keeps the Dual GE ZX circuit pack locked to
the OC-192 system timing. The BPD scrambles the data and outputs the data
as two groups of four data streams at 622 Mbit/s to the backplane. One group
of four data streams is routed via the backplane to switch module A and the
other group to switch module B.
Support circuits
The following three circuits support the Dual GE ZX circuit pack:
the transport control subsystem, second generation (TCSII)
The TCSII provides performance monitoring, fault handling, propagation of
The PLL provides system timing to the circuit pack.
The PUPS uses the 48 V battery voltage from the shelf to produce the
supplies required by the Dual GE ZX circuit pack.

Figure 1-25
Dual GE ZX circuit pack interface block diagram
DX3067_R3_SON
TCS
EOI
G-MAC
Dual
SERDES
1.25 Gbit/s
GE traffic
78 Mbit/s
STS-Nc
78 MHz
1 Gbit/s
125
Mbit/s
1.25
Gbit/s
10
8
32
DSCAM
G-MAC
EOI
10
Switch
A
BIBI
8
32
8
Legend
BIBI =
DSCAM =
EOI =
GE =
GMAC =
N=
SERDES =
STS =
TCS =
622 Mbit/s
(STS-Nc)
4 Switch
B
Bi-directional Backplane Interface

Dual scalable mapper
Gigabit Ethernet
Gigabit Ethernet Media Access Control
3, 6, 12, or 24
Serializer/deserializer
Synchronous Transport Signal

Figure 1-26
Dual GE ZX circuit pack (external view)
DX3650p
Optical connectors
(4 places)
Fiber carrier
1-2
Upper
latch
Dual GE
1-2
Carrier
handle
lGE
iDua
OUT
OUT 1
IN OUT
IN
IN
OUT 2
1
2
IN
Fiber clip
1
2
Lower
latch
Side view
Front view
Dual Gigabit Ethernet long reach interface (NTCA90CA)

The Dual Gigabit Ethernet (GE) long reach (LX) circuit pack allows native
Ethernet traffic to be mapped and carried in the SONET synchronous payload
envelope. This allows for Ethernet traffic to be carried over an OC-192 SONET
backbone in a point-to-point configuration.
The Dual GE LX circuit pack is a full height circuit with two independent
Ethernet ports.
Note: The Dual GE LX circuit pack can only be used as an unprotected
supported where the Dual GE LX circuit pack is the gateway.
Figure 1-27 shows a block diagram of the Dual GE LX circuit pack.
Figure 1-28 shows an external view of the Dual GE LX circuit pack.
The Dual GE LX circuit pack has the following characteristics:
two optical interfaces that support 1000Base-LX (1300 nm) single-mode
optical fiber (10 km reach) for each port


Transmit direction
serial data streams down to four byte wide 77.76 Mbit/s data streams (referred
to as 78 Mbit/s data streams in this document) and passes these to the DSCAM
circuit.
STS-12 outputs from the BIBI and the GMAC devices. The DSCAM uses up

sends the IP data to the GMAC devices at 78 Mbit/s
In each GMAC device, the IP data is fed into a 2 kbytes first-in-first-out

(FIFO). Using the data contained in the FIFO, the GMAC devices generate the
preamble
An 8-bit to 10-bit encoder in each GMAC device encodes the 32-bit data
stream into 10-bit symbols, in accordance with IEEE 802.3z. A 125 MHz
clock signal from the SERDES transfers the data from each GMAC device to
the SERDES.
Receive direction
The Dual GE LX circuit pack receives two optical data streams at 1.25 Gbit/s.
from the SERDES to each GMAC device.
Each GMAC device accepts the input data in the form of 10-bit parallel
symbols and clocks each group of four symbols into a 40-bit register at
125 MHz. An encoder converts each group of four 10-bit symbols to 8-bit
form in accordance with IEEE 802.3z, producing a 32-bit word, which is
output every fourth clock cycle.
The GMAC device receive module operates on each incoming Ethernet frame
as follows:
removes the SFD

The DSCAM maps the data between the Ethernet side and the OC-12side. The
GMAC device and the DSCAM performs point-to-point mapping, inserting
the IP frames into the SONET payload. The DSCAM outputs four groups of
8-bit parallel data at 78 Mbit/s and passes these to the BIBI.
pulse on the switch module. This keeps the Dual GE LX circuit pack locked to
Support circuits
The following three circuits support the Dual GE LX circuit pack:
supplies required by the Dual GE LX circuit pack.

Figure 1-27
Dual GE LX circuit pack interface block diagram
DX3067_R3_SON
TCS
EOI
G-MAC
Dual
SERDES
1.25 Gbit/s
GE traffic
78 Mbit/s
STS-Nc
78 MHz
1 Gbit/s
125
Mbit/s
1.25
Gbit/s
10
8
32
DSCAM
G-MAC
EOI
10
Switch
A
BIBI
8
32
8
Legend
BIBI =
DSCAM =
EOI =
GE =
GMAC =
N=
SERDES =
STS =
TCS =
622 Mbit/s
(STS-Nc)
4 Switch
B

Gigabit Ethernet
3, 6, 12, or 24

Figure 1-28
Dual GE LX circuit pack (external view)
DX3650p
Optical connectors
(4 places)
Fiber carrier
1-2
Upper
latch
Dual GE
1-2
Carrier
handle
lGE
iDua
OUT
OUT 1
IN OUT
IN
IN
OUT 2
1
2
IN
Fiber clip
1
2
Lower
latch
Side view
Front view
Dual Gigabit Ethernet short reach interface (NTCA90EA)

The Dual Gigabit Ethernet (GE) short reach (SX) circuit pack allows native
Ethernet traffic to be mapped and carried in the SONET synchronous payload
envelope. This allows for Ethernet traffic to be carried over an OC-192 SONET
backbone in a point-to-point configuration.
The Dual GE SX circuit pack is a full height circuit with two independent
Ethernet ports.
Note: The Dual GE SX circuit pack can only be used as an unprotected
supported where the Dual GE SX circuit pack is the gateway.
Figure 1-29 shows a block diagram of the Dual GE SX circuit pack.
Figure 1-30 shows an external view of the Dual GE SX circuit pack.
The Dual GE SX circuit pack has the following characteristics:
two optical interfaces that support 1000Base-SX (850 nm) multi-mode
fiber (550 m reach using 50um multi-mode fiber) for each port


Transmit direction
serial data streams down to four byte wide 78 Mbit/s data streams and passes
these to the DSCAM circuit.
STS-12 outputs from the BIBI and the GMAC circuits. The DSCAM uses up
sends the IP data to the GMAC circuits at 77.76 Mbit/s
In each GMAC, the IP data is fed into a 2 kbytes first-in-first-out (FIFO).

Using the data contained in the FIFO, the GMAC transmit circuits generate the
preamble
An 8-bit to 10-bit encoder in each GMAC encodes the 32-bit data stream into
10-bit symbols, in accordance with IEEE 802.3z. A 125 MHz clock signal
from the SERDES transfers the data from each GMAC to the SERDES.
Receive direction
The Dual GE SX circuit pack receives two optical data streams at 1.25 Gbit/s.
from the SERDES to each GMAC.
Each GMAC accepts the input data in the form of 10-bit parallel symbols and
clocks each group of four symbols into a 40-bit register at 125 MHz. An
encoder converts each group of four 10-bit symbols to 8-bit form in
accordance with IEEE 802.3z, producing a 32-bit word, which is output every
fourth clock cycle.
The GMAC receive module operates on each incoming Ethernet frame as
follows:
removes the SFD
The DSCAM maps the data between the Ethernet side and the OC-12 side. The
GMAC and the DSCAM performs point-to-point mapping, inserting the IP
frames into the SONET payload. The DSCAM outputs four groups of 8-bit
parallel data at 78 Mbit/s and passes these to the BIBI.
pulse on the switch module. This keeps the Dual GE SX circuit pack locked to
Support circuits
The following three circuits support the Dual GE SX circuit pack:
supplies required by the Dual GE SX circuit pack.

Figure 1-29
Dual GE SX circuit pack interface block diagram
DX3067_R3_SON
TCS
EOI
G-MAC
Dual
SERDES
1.25 Gbit/s
GE traffic
78 Mbit/s
STS-Nc
78 MHz
1 Gbit/s
125
Mbit/s
1.25
Gbit/s
10
8
32
DSCAM
G-MAC
EOI
10
Switch
A
BIBI
8
32
8
Legend
BIBI =
DSCAM =
EOI =
GE =
GMAC =
N=
SERDES =
STS =
TCS =
622 Mbit/s
(STS-Nc)
4 Switch
B

Gigabit Ethernet
3, 6, 12, or 24

Figure 1-30
Dual GE SX circuit pack (external view)
DX3650p
Optical connectors
(4 places)
Fiber carrier
1-2
Upper
latch
Dual GE
1-2
Carrier
handle
lGE
iDua
OUT
OUT 1
IN OUT
IN
IN
OUT 2
1
2
IN
Fiber clip
1
2
Lower
latch
Side view
Front view
OC-192 T/R interface (NTCA06)

Note: The OC-192 transmit/receive (T/R) circuit pack is used in OPTera
Connect DX bays only.
The OC-192 T/R interface circuit pack transmits and receives aggregate
OC-192 traffic signals. Forty different variants of the circuit pack provide forty
optical wavelength options. For more information, refer to SONET Planning
In the receive direction, the OC-192 T/R interface circuit pack performs the
receive optical OC-192 traffic from the line and convert the traffic data to
an STS-192 electrical signal
remove the overhead bytes and demultiplex the electrical traffic data into
16 STS-12 (622 Mbit/s) data streams
pass the 16 data streams through the backplane to the switch modules.
In the transmit direction, the OC-192 T/R interface circuit pack performs the
receive 16 STS-12 data streams through the backplane from the switch
modules
multiplex the data streams up to the STS-192 data rate and insert the
overhead bytes
convert the signal from electrical to optical form and transmit the signal as
OC-192 to the line
A microcontroller performs the control and monitoring functions for the T/R
circuit pack and communicates with the shelf controller. An electro-optical
controller (EOC) controls the electrical and optical functions in the circuit
pack.
The circuit pack contains a motherboard and a daughterboard. The
motherboard is the transmitter/receiver digital assembly (TRDA). The
daughterboard is the optical transmit/receive (OTR) circuit. Figure 1-31 shows
a block diagram of the OC-192 T/R circuit pack. Figure 1-32 shows an
external view of the circuit pack.
Transmitter/receiver digital assembly (TRDA)

The TRDA contains the following functional blocks:
synchronization driver receiver (SYDR)
transmit/receive overhead processor (TROHP)
622 MHz voltage controlled crystal oscillator (VCXO)
system clock generator (SCG)
transmit control subsystem (TCS)
phase detector
SYDR
Four SYDR circuits provide a total of 16 STS-12 (622 Mbit/s) T/R interfaces,
each SYDR containing four interfaces.
In the transmit direction, the function of the SYDR is as follows:
receive data through the backplane bus from either of the switch modules
A or B
locate the frame in the incoming data and descramble the data streams
perform forward error correction (FEC) and arrange the overhead (OH)
bytes
pass the data to the TROHP as 32 311 Mbit/s data streams with a clock
signal
In the receive direction, the function of SYDR is as follows:
accept 32 311 Mbit/s data streams from the TROHP with a 311 MHz clock
locate the frame in the incoming data and descramble the data streams
perform error correction and arrange the OH bytes
arrange the data into 16 622 Mbit/s data streams and pass the data to the
backplane bus to the switch modules
TROHP
The TROHP performs overhead processing in both the transmit and receive
directions.
In the transmit direction, the function of the TROHP is as follows:
receive 32 311 Mbit/s data streams from the four SYDRs and perform
frame location and parity checking
descramble the incoming data streams and convert the data from STS-12
to STS-192 format
generate and insert line and section overhead information and scramble the
data
convert the data to eight 1.2 Gbit/s data streams and pass the data to the
multiplexer driver on the OTR circuit
In the receive direction, the function of the TROHP is as follows:

receive eight 1.2 Gbit/s data streams from the multiplexer driver on the
OTR circuit
perform frame location and parity checking
descramble the data streams
calculate line and section errors and extract the K-bytes
extract the overhead bytes
format the data into 32 311 Mbit/s data streams and pass the data to the
SYDR circuits
generate a 39 MHz clock which drives a phase detector
VCXO
The VCXO provides the master clock signal for the system clock generator.
System clock generator (SCG)
The SCG functions as a transmit clock generator. The SCG receives a 39 MHz
clock signal from each of the switch modules and a 622 MHz clock from the
VCXO. The circuit provides a differential phase output to lock the VCXO. The
SCG also provides clock signals of 39 MHz and 622 MHz for the SYDRs.
Clock selection circuit
In this application, the clock selection circuit defaults to selection of the

39 MHz clock signal from the SCG. The output from the circuit drives a phase
detector that provides a control output for the 10 GHz PLL on the OTR.
Optical transmit/receive (OTR)
The OTR contains the following functional blocks:
T/R optical assembly
1:8 demultiplexer
electro-optical controller (EOC)
8:1 multiplexer
phase-locked loop (PLL)
continuous wave (CW) laser
modulator
T/R optical assembly
The T/R optical assembly receives an optical OC-192 signal from the line and
converts it to an electrical signal using a photodiode. A low noise preamplifier
then amplifies the signal to provide the STS-192 output to the demultiplexer
module.

Demultiplexer module
The demultiplexer module receives STS-192 traffic data from the T/R optical
assembly and recovers a clock signal from the incoming data. The recovered
clock signal clocks the 1:8 demultiplexer, producing 8-bit wide data at
1.2 Gbit/s. The module passes the eight data streams to the TROHP on the
TRDA motherboard. The module also performs automatic gain control (AGC)
on the incoming data.
Multiplexer driver
The multiplexer driver module contains a multiplexer and a driver. The

multiplexer part multiplexes the 8-bit wide data from the TROHP into a single
10 Gbit/s (STS-192) data stream. The driver part of the module then amplifies
the signal and passes it to the modulator.
Modulator
The modulator receives the output signal from the multiplexer driver module
and modulates this signal onto the light source from a continuous wave (CW)
laser. The optical wavelength of the laser depends on the variant of OC-192
T/R circuit pack fitted. The modulator transmits the signal with enough power
to launch the signal through 80 km of optical fiber.
PLL
The PLL circuit provides the 10 GHz line timing for the multiplexer driver
module. The control input for the PLL is from the phase detector circuit on the
TRDA.
Dither
The analog maintenance (AM) dither signal is a low frequency signal that is
modulated into the laser output. The signal consists of a transmitted pattern
representing the optical power level. The AM dither signal is recovered at the
receiving end, where it is used to set the optical power of the outgoing signal
to the correct level.
To reduce the occurrence of crosstalk with certain optical frequencies, two AM
dither frequency options are provided, AM1 and AM2.
Support circuits
The following three circuits support the OC-192 T/R circuit pack:
EOC
The EOC circuit monitors the optical and electrical performance of the
receiver modules and generates alarms. The EOC communicates its status and
the condition of the input signal with the transport control subsystem (TCS)
through a serial link. The TCS monitors this information and reports to the
shelf controller (SC) if necessary. The EOC also stores calibration data.
PUPS
The PUPS generates all the voltages required by the OC-192 T/R interface.
TCS
The TCS controls the operation of the OC-192 T/R circuit pack and allows it
to communicate with the shelf controller. The TCS also generates alarms and

Figure 1-31
OC-192 T/R interface block diagram
DX0632_SONET
OTR
TCS
Photodiode, STS-192
preamp,
AGC
OC-192
CW
Laser
Control
Control
EOC
1:8
demux
STS-192
8:1
mux
10 GHz
Clock clock (rec)
recovery
PUPS
1.2 Gbit/s data
1.2 GHz clock
1.2 GHz clock
TRDA
Phase
detector
TROHP
8
311 Mbit/s
data
SYDR
48V d.c.
EOC
1.2 Gbit/s data
d.c. supplies
8
311 Mbit/s
data
4
A
4
B
SYDR
OC-192
Modulator
PLL
8
d.c.
supplies
Driver
4 4
8
311 Mbit/s
data
8
311 Mbit/s
data
SYDR
SCG
SYDR
4 4
TCS
4
A
VCXO
4
B
A
B
39 MHz
16 x 622 Mbit/s data + 311MHz clocks

to/from Switch Modules A and B
Legend
CW
EOC
OTR
PLL
PUPS
SC
SCG
SYDR
TCS
TRDA
TROHP
VCXO
= Continuous wave
= Electro-optical controller
= Optical Transmit Receive
= Phase-locked loop
= Point of use power supply
= Shelf Controller
= System clock generator
= Sync driver/receiver
= Transmitter receiver digital assembly
= Transmit/receive overhead processor
= Voltage controlled crystal oscillator
SC

Figure 1-32
OC-192 T/R interface circuit pack (external view)
DX0631
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector (Output)

Optical connector (Input)
OC-192 DWDM TriFEC T/R interface (NTCF06)

Note: The OC-192 DWDM T/R with triple forward error correction
(TriFEC) interface circuit pack is only used in OPTera Connect DX
network elements running OPTera Connect DX Release 2 or above.
The OC-192 DWDM TriFEC T/R interface circuit pack includes the
functionality of the existing OC-192 DWDM T/R circuit pack with TriFEC.
The OC-192 DWDM TriFEC T/R interface circuit pack provides TriFEC
encoding in the transmit direction and TriFEC decoding in the receive
direction. The OC-192 DWDM T/R circuit pack uses a single forward error
correction (FEC) scheme to correct bit errors. To increase the FEC capability,
TriFEC is implemented in the current SYDR 3 ASIC. This new ASIC (called
TriFEC1 ASIC) is capable of performing: no FEC, FEC and TriFEC.
Transmit direction
The transmit circuitry of the OC-192 DWDM TriFEC T/R interface circuit
pack receives 16 STS-12 serial streams from the backplane in switched
applications. These signals are multiplexed together to form a serial NRZ
electrical signal that is then converted to an optical signal. The OC-192
DWDM TriFEC T/R interface circuit pack performs the transmit and receive
functions simultaneously.
Receive direction
The receive circuitry of the OC-192 DWDM TriFEC T/R interface circuit pack
receives an optical signal and converts it to an electrical NRZ signal. The
signal then demultiplexes to 16 STS-12 serial streams. The backplane interface
is differential current mode logic (CML) with clocks for every two data links.
Section and line overhead bytes are also monitored and inserted in both the
transmit and receive paths. Selective path overhead monitoring is also
performed. Backplane data can be active on either one of the two planes (A
or B) in switched applications. The OC-192 DWDM TriFEC T/R interface
circuit pack also receives two external clock signals, one from each switch for
synchronization. One is selected to synchronize both the 622MHz and 10GHz
phase locked loops (PLL).
See Figure 1-33 for a functional block diagram of the OC-192 DWDM TriFEC
T/R interface. See Figure 1-34 for an external view of the OC-192 DWDM
TriFEC T/R interface circuit pack.
OC-192 DWDM TriFEC T/R wavelengths

For information on the plan of DWDM wavelength allocation, refer to the
Optical Networks Applications Library (NTCA66BA).
Support circuits
The following four circuits support the OC-192 DWDM TriFEC T/R interface:
transport control subsystem (TCSII)
point-of-use power supply (PUPS)
phase-locked loops (PLLs)
The EOC controls:
the operation of the electro-optical module and multiplexer driver
the Receive supermodule
the modulator
the positive-intrinsic-negative (PIN) preamplifier module.
The TCSII controls the operation of the OC-192 DWDM TriFEC interface and
provides communication between the shelf controller and this circuit pack.
The TCSII also generates alarms and activates the LEDs on the OC-192
DWDM TriFEC circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 DWDM TriFEC
interface.
Phase-locked loops are used to generate low-jitter, highly stable OC-192 data
and clock signals.

Figure 1-33
OC-192 DWDM TriFEC T/R interface block diagram
DX4698p
STS12
4x622M Data differential

2xCKD311M differential
Tx
D9, 11 (A,B)
P1SA
FRMD8N, P
D10, 12
FRM8QN, P
1:4 Clock
From BPR
Distribution
10 ECL
8 Data
9 11 10 12
1 CK differential
Q9, 11
TriFEC
D5, 7
622M 39M
2
D1, 3
P1SB
Q(1, 3)
TIM_CLK
1 2 3 4
Q5, 7
TriFEC
Q10, 12
622M 39M
2
STS12
P1SC
D14, 16
TROHP
8 Data
REF
1 CK differential
ERRSIG
TriFEC
Q14, 16
622M 39M
2
XOR
REF_CLK
Tx
Rx
5 7 6 8
D2, 4
Q2, 4
Q6, 8
To 10G PLL
on module board
2
FRMD8N, P
1.2G
Socket
To modules
13 15 14 16
STS12
TriFEC
622M 39M
2
2
FRMD8N, P
Legend
CML
Q13, 15
D6, 8
P1SD
11
FRMD8N, P
D13, 15
1.2G
Socket
8 Data
From modules
REF
1 CK differential
2
FRMD8N, P
STS12
11
8KHz Framing
Pulse for BPD
4x622M
CK
differential
8
4x39M
CK
differential
8
39M SCG/PLL
622M VCXO
Switch or TDC
PLL
= Phased-locked loop
Rx
= Receive
SCG = System clock generation
TriFEC = Triple forward error correction
TROHP = Transmit receive overhead processor
Tx
= Transmit
VCXO = Voltage control crystal oscillator
Clock Selection
Logic

Figure 1-34
OC-192 DWDM TriFEC T/R interface circuit pack (external view)
DX3686p
LOS (Yellow)
Fail (Red)
Active (Green)

OC-192 short reach T/R interface (NTWR06AB)

Note: The OC-192 short reach (SR) T/R interface circuit pack is only used
in OPTera Connect DX network elements running OPTera Connect DX
Release 2 or above.
The OC-192 SR T/R interface circuit pack combines the functionality of the
existing OC-192 SR T/R interface circuit pack with TriFEC. The existing
circuit pack uses a single FEC scheme to correct bit errors. To increase forward
error correction capabilities, an ASIC (called TriFEC1 ASIC) is introduced
that is capable of performing no FEC, FEC and TriFEC.
Note: Although the OC-192 SR TriFEC T/R interface circuit pack is
equipped with the new TriFEC1 ASIC, only no FEC and single FEC are
performed in OPTera Connect DX Releases 3 and 4.
Transmit direction
The transmit circuitry of the OC-192 SR T/R interface circuit pack receives 16
STS-12 serial streams from the backplane in switched applications. These
signals are multiplexed together to form a serial NRZ electrical signal that is
then converted to an optical signal (the OC-192 SR T/R interface circuit pack
performs the transmit and receive functions simultaneously).
Receive direction
The receive circuitry of the OC-192 SR T/R interface circuit pack receives an
optical signal and converts it to an electrical NRZ signal. The signal then
demultiplexes to 16 STS-12 serial streams. The backplane interface is
differential CML with clocks for every two data links. Section and line
overhead bytes are also monitored and inserted in both the transmit and receive
paths. Selective path overhead monitoring is also performed. Backplane data
can be active on either one of the two planes (A or B) in switched
applications. The OC-192 SR T/R interface circuit pack also receives two
external clock signals, one from each switch for synchronization. One is
selected to synchronize both the 622MHz and 10GHz phase locked loops
(PLL).
Figure 1-35 shows a functional block diagram of the OC-192 SR TriFEC T/R
interface. Figure 1-36 shows an external view of the OC-192 SR TriFEC T/R

Support circuits
The following four circuits support the OC-192 SR T/R interface circuit pack:
transport control subsystem (TCS)
phase-locked loops (PLL)
The EOC controls the operation of both the electro-optical module and
multiplexer driver, the Receive supermodule, the modulator and the
positive-intrinsic-negative (PIN) preamplifier module.
The TCS controls the operation of the OC-192 SR T/R interface circuit pack
and provides communication between the shelf controller and this circuit pack.
The TCS also generates alarms and activates the LEDs on the circuit pack
faceplate.
The PUPS generates all the voltages required by the OC-192 SR T/R interface
circuit pack.
and clock signals.

Figure 1-35
OC-192 SR T/R interface block diagram
DX3699p_SONET
Control
EOC
Control
1:8
Demux
Driver
OC-192
EML
8
1.2 Gbit/s data
d.c. supplies
8
1.2 GHz clock
10 GHz
clock
(rec)
OC-192
8:1
Mux
1.2 GHz clock
Clock
recovery
STS-192
1.2 Gbit/s data
Photodiode,
preamp,
AGC
OC-192
OTR
TCS
PLL
EOC
TRDA
d.c. supplies
PUPS
Phase
detector
TROHP
311
8 Mbit/s 8
data
311
8 Mbit/s 8
data
TriFEC
48V d.c. 4 4 4 4
A
311
8 Mbit/s 8
data
TriFEC
TriFEC
SCG
4 4 4 4
4 4 4 4
4 4 4 4
A B
39 MHz
SC
311
8 Mbit/s 8
data
TriFEC
TCS
VCXO

Legend
EML = Electroabsorption modulated laser
OTR = Optical transmit receive
PUPS = Point-of-use power supply
SC = Shelf controller
SCG
TCS
TRDA
TriFEC
TROHP
VCXO

= Triple forward error correction ASIC

Figure 1-36
OC-192 SR T/R interface circuit pack
DX3686p
LOS (Yellow)
Fail (Red)
Active (Green)

OC-192 intermediate reach T/R interface (NTWR06CA)

Note: The OC-192 intermediate reach (IR) T/R interface circuit pack is
only used in OPTera Connect DX network elements running OPTera
Connect DX Release 4.1 or above.
The OC-192 IR T/R interface circuit pack is specifically designed for
intermediate reach (within 40 km) applications.
The OC-192 IR T/R interface circuit pack can be installed in the same slots
supported by the OC-192 SR T/R interface circuit pack. The OC-192 IR T/R
interface circuit pack supports single FEC and no FEC.
Transmit direction
The transmit circuitry of the OC-192 IR T/R interface circuit pack receives 16
STS-12 serial streams from the backplane in switched applications. These
signals are multiplexed together to form a serial NRZ electrical signal that is
then converted to an optical signal (the OC-192 IR T/R interface circuit pack
performs the transmit and receive functions simultaneously).
Receive direction
The receive circuitry of the OC-192 IR T/R interface circuit pack receives an
optical signal and converts it to an electrical NRZ signal. The signal then
demultiplexes to 16 STS-12 serial streams. The backplane interface is
differential CML with clocks for every two data links. Section and line
overhead bytes are also monitored and inserted in both the transmit and receive
paths. Selective path overhead monitoring is also performed. Backplane data
can be active on either one of the two planes (A or B) in switched
applications. The OC-192 IR T/R interface circuit pack also receives two
external clock signals, one from each switch for synchronization. One is
selected to synchronize both the 622MHz and 10GHz phase locked loops
(PLLs).
Figure 1-37 shows a functional block diagram of the OC-192 IR T/R interface.
Figure 1-38 shows an external view of the OC-192 IR T/R interface circuit
pack.
Support circuits
The following four circuits support the OC-192 IR T/R interface circuit pack:
transport control subsystem (TCS)
multiplexer driver, the Receive supermodule, the modulator and the
The TCS controls the operation of the OC-192 IR T/R interface circuit pack
The TCS also generates alarms and activates the LEDs on the circuit pack
faceplate.
The PUPS generates all the voltages required by the OC-192 IR T/R interface
circuit pack.
and clock signals.

Figure 1-37
OC-192 IR T/R interface block diagram
DX0632_SONET
OTR
TCS
Photodiode, STS-192
preamp,
AGC
OC-192
CW
Laser
Control
Control
EOC
1:8
demux
STS-192
8:1
mux
10 GHz
Clock clock (rec)
recovery
PUPS
1.2 Gbit/s data
1.2 GHz clock
1.2 GHz clock
TRDA
Phase
detector
TROHP
8
311 Mbit/s
data
SYDR
48V d.c.
EOC
1.2 Gbit/s data
d.c. supplies
8
311 Mbit/s
data
4
A
4
B
SYDR
OC-192
Modulator
PLL
8
d.c.
supplies
Driver
4 4
8
311 Mbit/s
data
8
311 Mbit/s
data
SYDR
SCG
SYDR
4 4
TCS
4
A
VCXO
4
B
A
B
39 MHz

Legend
CW
EOC
OTR
PLL
PUPS
SC
SCG
SYDR
TCS
TRDA
TROHP
VCXO
= Continuous wave
= Electro-optical controller
= Optical Transmit Receive
= Phase-locked loop
= Point of use power supply
= Shelf Controller
= Sync driver/receiver
SC

Figure 1-38
OC-192 IR T/R interface circuit pack
DX3686p
LOS (Yellow)
Fail (Red)
Active (Green)

OC-192 long reach T/R with APD interface (NTWR06B)

The OC-192 long reach (LR) T/R with avalanche photo diode (APD) interface
circuit pack replaces the functionality of the existing OC-192 DWDM TriFEC
T/R circuit pack in specific applications. The OC-192 LR T/R with APD
interface circuit pack does not function as a DWDM network element, but
operates in the transmission windows of 1533 2.5nm and 1557 2.5nm.
The triple forward error correction (TriFEC) function is implemented in the
SYDR 4 ASIC. This ASIC is capable of performing no FEC, FEC and TriFEC.
The TriFEC encoding is applied in the transmit direction and TriFEC decoding
in the receive direction. In OPTera Connect DX network elements running
OPTera Connect DX Release 1, the OC-192 LR T/R with APD interface
circuit pack provides only single forward error correction (FEC) to correct bit
errors. In OPTera Connect DX network elements running OPTera Connect DX
Release 3 and above, the OC-192 LR T/R with APD interface circuit pack uses
the TriFEC scheme.
Transmit direction
The transmit circuitry of the OC-192 LR T/R with APD interface circuit pack
receives 16 STS-12 serial streams from the backplane in switched
applications. These signals are multiplexed together to form a serial NRZ
electrical signal that is then converted to an optical signal. The OC-192 LR T/R
with APD interface circuit pack performs the transmit and receive functions
simultaneously.
Receive direction
The receive circuitry of the OC-192 LR T/R with APD interface circuit pack
receives an optical signal and converts it to an electrical NRZ signal. This
signal is then demultiplexed to 16 STS-12 serial streams. The backplane
interface is differential CML with clocks for every two data links. Section and
line overhead bytes are also monitored and inserted in both the transmit and
receive paths. Selective path overhead monitoring is also performed.
Backplane data can be active on either one of the two planes (A or B) in
switched applications. The OC-192 LR T/R with APD interface circuit pack
also receives two external clock signals, one from each switch for
synchronization. One is selected to synchronize both the 622MHz and 10GHz
phase-locked loops (PLL).
Figure 1-39 shows a functional block diagram of the OC-192 LR T/R with
APD interface. Figure 1-40 shows an external view of the OC-192 LR T/R
with APD interface circuit pack.
Support circuits
The following four circuits support the OC-192 LR T/R with APD interface:
transport control subsystem (TCSII)
The EOC controls:
the operation of the electro-optical module and multiplexer driver
the Receive supermodule
the modulator
the avalanche photo diode (APD) preamplifier module.
The TCSII controls the operation of the OC-192 LR T/R with APD interface
The TCSII also generates alarms and activates the LEDs on the faceplate of
this circuit pack.
The PUPS generates all the voltages required by the OC-192 LR T/R with
APD interface.
PLLs are used to generate low-jitter, highly stable OC-192 data and clock
signals.

Figure 1-39
OC-192 LR T/R with APD interface block diagram
DX4698p
STS12
4x622M Data differential

2xCKD311M differential
Tx
D9, 11 (A,B)
P1SA
FRMD8N, P
D10, 12
FRM8QN, P
1:4 Clock
From BPR
Distribution
10 ECL
8 Data
9 11 10 12
1 CK differential
Q9, 11
TriFEC
D5, 7
622M 39M
2
D1, 3
P1SB
Q(1, 3)
TIM_CLK
1 2 3 4
Q5, 7
TriFEC
Q10, 12
622M 39M
2
STS12
P1SC
D14, 16
TROHP
8 Data
REF
1 CK differential
ERRSIG
TriFEC
Q14, 16
622M 39M
2
XOR
REF_CLK
Tx
Rx
5 7 6 8
D2, 4
Q2, 4
Q6, 8
To 10G PLL
on module board
2
FRMD8N, P
1.2G
Socket
To modules
13 15 14 16
STS12
TriFEC
622M 39M
2
2
FRMD8N, P
Legend
CML
Q13, 15
D6, 8
P1SD
11
FRMD8N, P
D13, 15
1.2G
Socket
8 Data
From modules
REF
1 CK differential
2
FRMD8N, P
STS12
11
8KHz Framing
Pulse for BPD
4x622M
CK
differential
8
4x39M
CK
differential
8
39M SCG/PLL
622M VCXO
Switch or TDC
PLL
= Phased-locked loop
Rx
= Receive
SCG = System clock generation
TriFEC = Triple forward error correction
TROHP = Transmit receive overhead processor
Tx
= Transmit
VCXO = Voltage control crystal oscillator
Clock Selection
Logic

Figure 1-40
OC-192 LR T/R with APD interface circuit pack (external view)
DX3686p
LOS (Yellow)
Fail (Red)
Active (Green)

OC-192 XR (NTCA04)
Note: The XR circuit pack is used in OC-192 regenerator bays only.
The OC-192 XR is a single regenerator interface that receives an OC-192
optical signal and processes the section overhead. The circuit also inserts the
overheads into the outgoing payload. The XR multiplexes the data to a single
serial STS-192 data stream and then converts this data stream to an optical
OC-192 signal. The XR transmits the signal with enough power to drive 80 km
of stream mode, seamless messaging (SM) optical fiber.
The OC-192 XR performs the following functions:
receive OC-192 optical signals and demultiplex to 1.2 Gbit/s buses to the
transmit receive overhead processor (TROHP)
extract section overhead bytes
transmit overhead bytes through the second generation transport control

subsystem (TCS+) to the regenerator in the opposite direction
insert the section overhead into the outgoing data
support through timing
multiplex 311 MHz, 32-bit wide data to serial STS-192
convert serial STS-192 to optical OC-192 with 1528 nm to 1560 nm
wavelengths, positive or negative chirp
transmit the optical output signal with enough power to drive 80 km of
optical fiber
The XR circuit pack also provides the following features:

support downloadable firmware and software
generate alarm indication signal (AIS) under input failure
conditionsgreen, red and yellow faceplate LEDs
provide unit control and maintenance at the TCS+, that also has a bottom
latch release sensor
provide software provisionable output power and chirp polarity using the
Equipment menu of the NE UI
provide editable circuit pack wavelength using the Equipment menu of the
NE UI
See Figure 1-41 for a functional block diagram of the OC-192 XR. See
Figure 1-42 for an external view of the OC-192 XR.
Support circuits
The following three circuits support the OC-192 XR:
separate electro-optical controllers (EOC) for electro-optical and
high-speed module control
the second generation transport control subsystem (TCS+)
The EOC controls the operation of both the electro-optical module and the
multiplexer driver.
The TCS+ controls the operation of the OC-192 XR. The TCS+ provides
communication between the shelf controller and the XR. The TCS+ also
generates alarms and activates the LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 XR. The TCS+
monitors the supply voltage levels for lower than normal conditions.

Figure 1-41
OC-192 XR block diagram
DX1383_SONET
10 GHz VCO
OC-192
ROA
STS-192
Super 1.2 Gbit/s

1.2 Gbit/s MUXDriver STS-192 ElectroTROHP
Demux
optic
module
8
8
module
module
EOC
Active
(green)
TCS+
Fail
(red)
Legend:
EOC
PUPS
TCS
TROHP
ROA
VCO
To/from
Shelf controller
= Electro-Optic Controller
= Transmit Receive OverHead Processor
= Receive Optical Amplifier
= Voltage Controlled Oscillator
+12 V
-12V
-48 V
+3.3V
PUPS
+5V
-5V
-12V
OC-192

Figure 1-42
OC-192 XR circuit pack (external view)
F5512-192_R60
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)
OC-192 merged XR/WT (NTCF04)

Note: The transponder/regenerator (XR) circuit pack is used in OC-192
regenerator bays only.
The OC-192 merged XR/wavelength translator (WT) is a single regenerator
interface that receives an OC-192 optical signal and processes the section
overhead. The circuit also inserts the overheads into the outgoing payload. The
merged XR/WT multiplexes the data to a single serial STS-192 data stream
and then converts this data stream to an optical OC-192 signal. The merged
XR/WT transmits the signal with enough power to drive 80 km of single mode
optical fiber.
Note: When installed in a OC-192 bay, the NTCF04 circuit pack operates
only as an XR. The NTCF04 circuit pack can be equipped as a WT in an
OPTera Long Haul 1600 Repeater network element. The added
functionality of Traffic Mode provisioning to (3R) is supported. For more
information, refer to the OPTera Long Haul 1600 Release 7 Repeater NE
Network Application Guide, NTY316AG.
The OC-192 merged XR/WT circuit pack performs the following functions:
receive OC-192 optical signals and demultiplex to 1.2 Gbit/s buses to the
transmit receive overhead processor (TROHP)
extract section overhead bytes
transmit overhead bytes through the second generation transport control
subsystem (TCS+) to the regenerator in the opposite direction
insert the section overhead into the outgoing data
support through timing
multiplex 311 MHz, 32-bit wide data to serial STS-192
convert serial STS-192 to optical OC-192 with 1528 nm to 1560 nm
wavelengths, positive or negative chirp
transmit the optical output signal with enough power to drive 80 km of
optical fiber
The merged XR/WT circuit pack also provides the following features:
support for downloadable firmware and software
generation of alarm indication signal (AIS) under input failure conditions
(green, red and yellow faceplate LEDs)
unit control and maintenance at the TCS+
a bottom latch release sensor
software provisionable output power and chirp polarity using the
Equipment menu of the NE UI
See Figure 1-43 for a functional block diagram of the OC-192 merged
XR/WT. See Figure 1-44 for an external view of the OC-192 merged XR/WT.
Support circuits
The following three circuits support the OC-192 merged XR/WT:
separate electro-optical controllers (EOCs) for electro-optical and
high-speed module control
the second generation transport control subsystem (TCS+)
The EOC controls the operation of both the electro-optical module and the
multiplexer driver.
The TCS+ controls the operation of the OC-192 merged XR/WT. The TCS+
provides communication between the shelf controller and the merged XR/WT.
The TCS+ also generates alarms and activates the LEDs on the circuit pack
faceplate.
The PUPS generates all the voltages required by the OC-192 merged XR/WT.
The TCS+ monitors the supply voltage levels for lower than normal
conditions.

Figure 1-43
OC-192 merged XR/WT block diagram
DX1383_SONET
10 GHz VCO
OC-192
ROA
STS-192
Super 1.2 Gbit/s

1.2 Gbit/s MUXDriver STS-192 ElectroTROHP
Demux
optic
module
8
8
module
module
EOC
Active
(green)
TCS+
Fail
(red)
Legend:
EOC
PUPS
TCS
TROHP
ROA
VCO
To/from
Shelf controller
+12 V
-12V
-48 V
+3.3V
PUPS
+5V
-5V
-12V
OC-192

Figure 1-44
OC-192 merged XR/WT circuit pack (external view)
F5512-192_R60
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)

DX1383_SDH
10 GHz VCO
STM-64
ROA
STM-64
Super 1.2 Gbit/s

1.2 Gbit/s MUXDriver STM-64
TROHP
Demux
module
8
module
8
Electrooptic
module
EOC
Active
(green)
TCS+
Fail
(red)
Legend:
EOC
PUPS
TCS
TROHP
ROA
VCO
To/from
Shelf controller
+12 V
-12V
-48 V
+3.3V
PUPS
+5V
-5V
-12V
STM-64
OC-192 DWDM transmit interface (NTCA01)

Note: The OC-192 DWDM transmit interface circuit pack is used in the
OC-192 bays only.
The OC-192 DWDM transmit interface aligns with a 100 GHz optical
frequency grid that is a subset of the complete ITU-T grid. The DWDM
transmit interface receives traffic as sixteen STS-12 serial links from both
switch modules and transmits these as an OC-192 signal.
The OC-192 DWDM transmit interface is available in 32 different
wavelengths.
The OC-192 DWDM transmit interface performs the following functions:
insert section and line overhead bytes
encode the overhead for forward error correction (FEC)

select the data and clock coming from switch module A or B
synchronize the data with the system clock
transmit the OC-192 signal with enough power to drive 80 km of optical
fiber
The OC-192 DWDM transmit interface also provides the following features:
software provisionable output power and chirp polarity using the
Equipment menu of the NE UI.
editable circuit pack wavelength using the Equipment menu of the NE UI
screen
See Figure 1-45 for a functional block diagram of the OC-192 DWDM
transmit interface. See Figure 1-46 for an external view of the OC-192 DWDM
transmit interface circuit pack.
Each backplane receiver (BPR) interface receives four groups of four data
streams of 622 Mbit/s STS-12 data from switch module A or B. The forward
error correction (FEC) circuit receives the sixteen data signals and encodes the
overhead for FEC.
The transmit overhead processor (TOHP) has the following functions:

descramble the incoming data
generate and insert line and section framing bytes
insert overhead bus information
scramble the data
The TOHP then passes the data to the transmit intermediate multiplexer (TIM)
which outputs eight data lines. The multiplexer driver module then converts
the eight data lines to one STS-192 electrical signal. The electro-optical
module then converts the STS-192 electrical signal to an OC-192 optical
signal, and launches the signal through optical fiber.
This circuit pack also features a bottom latch release sensor, which alerts the
system of circuit pack removal.
OC-192 DWDM transmitter wavelengths
For information on the plan of DWDM wavelength allocation, refer to the
Optical Networks Applications Library (NTCA66BA).
Support circuits
The following three circuits support the OC-192 DWDM transmit interface:
multiplexer driver.
The TCS controls the operation of the OC-192 DWDM transmit interface. The
TCS provides communication between the shelf controller and the OC-192
DWDM transmit interface. The TCS also generates alarms and activates the
LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 DWDM transmit
interface.

Figure 1-45
OC-192 DWDM transmit interface block diagram
DX1370_SONET
4
A
10 GHz VCO
BPR
16 x 622 Mbit/s from Switch module A

16 x 622 Mbit/s from Switch module B
4
BPR
B
4
FEC
TIM
TOHP
ElectroMUXDriver STS-192
optic
module
module
OC-192
4
A
BPR
B
4
4
BPR
EOC
Active
(green)
TCS+
Legend:
BPR = BackPlane Receiver
EOC = Electro-Optical Controller
FEC = Forward Error Correction
PUPS = Point-of-Use Power Supply
To/from
TCS = Transport Control Subsystem
Shelf controller
TOHP = Transmit OverHead Processor
TIM = Transmit Intermediate Multiplexer
VCO = Voltage Controlled Oscillator
-48 V
Fail
(red)
+12 V
-12V
PUPS
+3.3V
+5V
-5V
-8V

Figure 1-46
OC-192 DWDM transmit interface circuit pack (external view)
F5514-192_R60
Fail (Red)
Active (Green)
Optical connector
(Output)
OC-192 DWDM regenerator/transmit interface (NTCA03)

Note: The OC-192 regenerator/transmit interface circuit pack is used in
the OC-192 regenerator bays only.
The OC-192 DWDM regenerator/transmit (Rg/Tx) interface receives an
STS-192 electrical signal from the OC-192 receive interface and transmits an
OC-192 optical signal. The OC-192 DWDM Rg/Tx interfaces are available
with the same wavelengths as the OC-192 DWDM transmit interfaces.
The OC-192 DWDM Rg/Tx interface performs the following functions:
process the section overhead
convert the serial STS-192 electrical signal into an optical signal
The OC-192 DWDM Rg/Tx interface also makes available the following
features:
software provisionable output power and chirp polarity from the NE UI
Equipment menu
edit circuit pack wavelengths from the NE UI Equipment menu
Note: The previous two features are only available with Release 3 or
above of the OC-192 software load.
Figure 1-47 shows a functional block diagram of the OC-192 DWDM Rg/Tx
interface. Except for the external label, the OC-192 DWDM Rg/Tx circuit
pack looks identical to the OC-192 DWDM transmit interface circuit pack
shown in Figure 1-46.
The OC-192 DWDM Rg/Tx interface receives a 32-bit wide 311 Mbit/s
electrical signal from the OC-192 receiver through the shelf backplane. The
circuit outputs the data as sixteen STS-12 data streams.
The TOHP performs the following tasks:
descrambles the incoming data
generates and inserts section framing bytes
inserts overhead information
scrambles the data again
passes the data to the TIM, which outputs eight data lines
The multiplexer driver module converts the eight data lines to one STS-192
serial signal. The electro-optical module converts the STS-192 electrical signal
to an optical signal, and launches the optical signal through optical fiber.
This circuit pack also has a bottom latch release sensor, which alerts the system
of circuit pack removal.
Support circuits
The following three support circuits are part of the OC-192 DWDM Rg/Tx
interface:
The EOC controls the operation of the electro-optical module and multiplexer
driver.
The TCS controls the operation of the OC-192 DWDM Rg/Tx interface. The
TCS provides communication between the shelf controller and the OC-192
DWDM Rg/Tx interface. The TCS also generates alarms and activates the
LEDs on the circuit pack faceplate.
The PUPS generates all the voltages required by the OC-192 DWDM Rg/Tx
interface.
Variants
For information on the variants of this circuit pack, refer to SONET Planning

Figure 1-47
OC-192 DWDM regenerator/transmit interface block diagram
DX1371_SONET
10 GHz VCO
311 Mbit/s
ROHP
TOHP
TIM
32
ElectroMUXDriver STS-192 optic

module
module
OC-192
EOC
Active
(green)
TCS+
Fail
(red)
+12 V
To/from
Shelf controller
-12V
-48 V
Legend:
EOC
PUPS
TCS
ROHP
TIM
TOHP
VCO
= Transmit Intermediate Multiplexer
= Transmit OverHead Processor
+3.3V
PUPS
+5V
-5V
-12V
OC-192 short reach receive interface (NTCA02)

Note: The OC-192 short reach (SR) receive interface is used in the
OC-192 bays only.
The OC-192 SR receive circuit pack acts as the interface between the incoming
optical signal and the OC-192 demultiplexer.
The OC-192 SR receive interface performs the following functions:
amplify the incoming optical signal
Note: For the OC-192 SR receive interface, the signal goes into the
convert the OC-192 optical signal into an STS-192 electrical signal

demultiplex the STS-192 into a 32-bit wide signal
provide optical performance information
Figure 1-48 shows a functional block diagram of the OC-192 SR receive

interface. Figure 1-49 shows an external view of the OC-192 SR receive
The incoming OC-192 optical signal first goes to the PIN preamplifier module
where the signal converts to an STS-192 electrical signal. The equalizer and
demultiplexer convert the STS-192 signal into eight data streams and transmit
them to the receiver intermediate demultiplexer (RID). The RID accepts these
signals and demultiplexes them to a 32-bit wide STS-192 output. This signal
then goes to the OC-192 demultiplexer through the shelf backplane.
The OC-192 SR receive interface also has a bottom latch release sensor, which
alerts the system of circuit pack removal. If the circuit pack is active and
protection is available, the circuit pack switches the traffic.
Support circuits
The following circuits support the OC-192 SR receive interfaces:
The main functions of the EOC are as follows:
generate the alarms, optimize the parameters of the received STS-192
signal (overall gain, clock and data timing, and threshold level)
monitor the optical and electrical performances of the receiver modules
The TCS is the on board computer for the supervision of the OC-192 SR
receive interfaces. The TCS provides communication between the shelf
controller and the EOC.
The TCS receives information about the module status, the condition of the
input signal from the EOC and other information. The TCS sends this
information to the shelf controller. The TCS also generates alarms and
The PUPS generates all the voltages required by the OC-192 SR receive
interfaces.

Figure 1-48
OC-192 SR receive interface block diagram
DX1372_SONET
OC-192
SR Rx
STS-192
to OC-192 Demux
PIN/ STS-192
Equalizer
preamp
Super
demux
module
32
RID
Active
(green)
EOC
LOS
(yellow)
Fail
(red)
TCS+
To/from
Shelf controller
Legend
EOC = Electro-optic controller
PUPS = Point-of-use power supply
RID = Receive interface demultiplexer
SR Rx = Short reach receiver
TCS = Transport controlled subsystem
+12 V
-12V
-48 V
PUPS
+5V
-5V
-6.5V

Figure 1-49
OC-192 SR receive interface circuit pack (external view)
F5513-192_R60
LOS (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Input)
OC-192 demultiplexer (NTCA05)

Note: The OC-192 demultiplexer is used in the OC-192 bays only.
The OC-192 demultiplexer processes the STS-192 data sent by the receive
interface and sends it to the switch modules.
The main functions of the OC-192 demultiplexer are as follows:
extract the transport overhead and send it to the shelf backplane
synchronize the incoming signal with the shelf clock
transmit section data communications channel (SDCC) and line data
communications channel (LDCC) to the shelf backplane
Figure 1-50 shows a functional block diagram of the OC-192 demultiplexer.
Figure 1-51 shows an external view of the OC-192 demultiplexer circuit pack.
Incoming STS-192 data from the OC-192 receive interface goes through the
receive overhead processor (ROHP), which reads and processes the overhead.
The STS-192 signal then splits into STS-48 data streams and goes to the FEC,
which performs forward error correction. The synchronization (SYNC)
module receives the data streams and synchronizes them to the shelf clock
before passing them to the BPD. Two identical signals (each equivalent to an
STS-48) from each of the four BPDs, go to the switch modules through the
shelf backplane.
This circuit pack also features a bottom latch release sensor. The sensor alerts
the system of circuit pack removal, and switches the traffic if the circuit pack
is active and protection is available.
Support circuits
The following two circuits support the OC-192 demultiplexer:

The TCS controls the operation of the OC-192 demultiplexer. The TCS
provides communication between the shelf controller and the different
modules on the OC-192 demultiplexer. The TCS also generates alarms and
The PUPS generates all the voltages required by the OC-192 demultiplexer.

Figure 1-50
OC-192 demultiplexer block diagram
DX1260_SONET
4
FEC
SYNC
BPD
4
4
B
A
FEC
Parallel
STS-192 from
Rx Interface
SYNC
BPD
4
4
ROHP
32
FEC
SYNC
BPD
4
16 x 622 Mbit/s to
Switch module A
16 x 622 Mbit/s to
Switch module B
4
A
FEC
SYNC
BPD
4
Active
(green)
TCS+
Legend
BPD
FEC
LDCC
PUPS
ROHP
SCG
SDCC
SYNC
TCS
To/from
Shelf controller
= Backplane driver
= Forward error correction
= Line data communications channel
= Receive overhead processor
= System clock generation
= Section data communications channel
= Synchronization module
= Transport controlled subsystem
Fail
(red)
LDCC/SDCC
to OC-192
+3.3 V
-48 V
PUPS
+5V
-5V
-2V

Figure 1-51
OC-192 demultiplexer circuit pack (external view)
F3183-2-192
Latch
Fail (Red)
Active (Green)
Latch
Switch module (NTCA26, NTCA24)

The switch module supports the OC-192 optical units required in add/drop
multiplexer (ADM) configurations. The switch module performs all the
switching functions required for the OC-192 system. The two switch modules,
A and B, operate as a working and protection pair in a 1+1 configuration.
This section describes the following switch modules:
DX65 (NTCA26AA) - OPTera Connect DX bays only
DX100 (NTCA26BA) - OPTera Connect DX bays only
DX140 (NTCA26CA) - OPTera Connect DX bays only
Data overhead switch (DOS) switch module (NTCA24AA) - OC-192 bays
only
Note 1: The functional architectures of the DX65 and DOS switch
modules are common to each other and throughput is the same.
Note 2: The DX140 switch module is required when the network element
is configured as the hub network element in a dual 4-Fiber Ring
configuration and when the network element is configured as an
unprotected hub. The DX100 switch module is used in the single 4-Fiber
Ring configuration.
The DX65, DX100, and DX140 switch modules are used in OPTera
Connect DX network elements with the following circuit packs:
OC-192 DWDM T/R interface (NTCA06)
OC-192 DWDM TriFEC T/R (NTCF06)
OC-192 short reach (SR) T/R (NTWR06AA)
OC-192 intermediate reach (IR) T/R (NTWR06CA)
OC-192 SR TriFEC T/R (NTWR06AB)
OC-192 long reach (LR) T/R with APD (NTWR06B)
The DOS switch module NTCA24 is used in OC-192 network elements with
the following circuit packs:
OC-192 DWDM transmit interface (NTCA01)
OC-192 DWDM Rg/Tx (NTCA03)
OC-192 SR receive interface (NTCA02)
OC-192 demultiplexer (NTCA05)
OC-192 XR (NTCA04)
OC-192 merged XR/WT (NTCF04)
OC-192 RxVOA merged XR/WT (NTCF14)
MOR (NTCA11AK, NTCA11BK or NTCA11CK)
MOR Plus (NTCA11NK, NTCA11PK, NTCA11JK or NTCA11KK)
The switch modules perform the following functions:

synchronization
traffic handling
protection switching
overhead switching
other control functions
system of circuit pack removal, and switches the traffic if the circuit pack is
active and protection is available.
Figure 1-52 shows a block diagram for the DX65 and standard DOS switch
module. Figure 1-53 shows a block diagram for the DX100 and DX140 switch
modules. Figure 1-54 shows an external view of the switch module.
Data overhead switch
The main switch processing circuit consists of three DOS stages: first, mid and
third stage (see Figure 1-52). All outputs from the first DOS stage
cross-connect to all inputs of the second stage. The connections between the
mid and third stages are a mirror image of those between the first and mid
stages. The first and third DOS stages perform timeslot interchange functions.
The required interchange pattern is programmed into the memory of the stage.
The mid stage performs the main routing and switching function.
Synchronization
The switch module receives three different reference clock signals: two come
from the external synchronization interface (ESI), and one from the other
switch module. From these three clock signals, the switch module selects a
reference and locks its local voltage-controlled crystal oscillator (VCXO) to
that clock signal.
The switch module provides clock and frame signals for the OC-192
demultiplexers and OC-192 transmit interfaces of the main shelf. The switch
module also performs clock and frame handoff at each input port to align the
data before time slot interchange (TSI). The switch module also performs
reference switches while maintaining the least possible phase error between
the VCXOs of the two switch modules.
Traffic handling
The switch module handles the traffic data passing between the OC-192 T/R
circuit pack and the tributaries. The traffic handling capacity of the switch
module is determined by the DOS TSI arrays. All circuit packs in the main
transport shelf operate as working and protection pairs. There are no
unprotected tributaries.
DX65
The DX65 switch module has a maximum bandwidth capacity of 60 Gbit/s of

traffic. The bandwidth is divided as follows:
four OC-192 (total 40 Gbit/s) line traffic
eight OC-48 tributaries (total 20 Gbit/s)
A maximum of eight OC-48 or Quad OC-12 tributaries are used in this
application. The maximum total usage for the switch module is 60 Gbit/s.
The DX65 switch module does not support the extension shelf.
DX100
The DX100 switch module has a maximum bandwidth capacity of 100 Gbit/s
of traffic, the bandwidth is divided as follows:
four OC-192 (total 40 Gbit/s) line traffic
sixteen OC-48 tributaries (total 40 Gbit/s) in the main shelf
eight OC-48 tributaries (total 20 Gbit/s) in the extension shelf
Only a maximum of eight OC-48 or eight Quad OC-12 tributaries (total
20 Gbit/s) are used in the main shelf for this application, so that the maximum
total usage for the switch module is 80 Gbit/s.
DX140
The DX140 switch module has a maximum bandwidth capacity of 140 Gbit/s
of traffic, the bandwidth is divided as follows:
eight OC-192 (total 80 Gbit/s) line traffic
sixteen OC-48 tributaries (total 40 Gbit/s) in the main shelf
eight OC-48 tributaries (total 20 Gbit/s) in the extension shelf
Only a maximum of eight OC-48, eight Quad OC-3 or eight Quad
OC-12tributaries (possible total 20 Gbit/s) are used in the main shelf of this
application, so that the maximum total usage for the switch module is
120 Gbit/s.

Tributaries
The rules that determine the maximum number of working and protection
tributaries for which the switch module handles traffic are summarized in
Table 1-3. The number given in the table is the maximum number of circuit
packs of that type with no other tributary interfaces present:
Table 1-3
Tributary allocation
T/R Interface
(see Note1)
Main shelf
OPTera Connect DX
Extension shelf
(see Note2)
OC-192
Working
Protection
Working
Protection
Working
Protection
Quad OC-3
HD OC-3
Half-height OC-12
Quad OC-12
OC-48
Dual OC-48
(see Note3)
Quad OC-48
Dual GE
Note 1: If the network element protection mode set to protected, all tributary circuit packs operate as
working and protection pairs (there are no unprotected tributaries). If the network element protection
mode is set to unprotected, there can be mixed unprotected and protected tributaries on a port-basis.
Note 2: The extension shelf is not applicable if the switch module is a DX65.
Note 3: The Dual OC-48 tributary circuit packs are not supported in the extension shelf.
The following rules state the maximum number of working and protection
tributaries for which the switch module handles traffic:
a maximum of four working and four protection Quad OC-3 T/R interfaces
with no other tributary interfaces present
a maximum of four working and four protection HD OC-3 T/R interfaces
with no other tributary interfaces present (with either the DX100 or DX140
switch module only)
a maximum of eight working and eight protection half-height OC-12 T/R
interfaces with no other tributary interfaces present (OC-192 network
elements only)
a maximum of four working and four protection Quad OC-12 T/R
interfaces with no other tributary interfaces present
a maximum of four working and four protection OC-48 T/R interfaces with
no other tributary interfaces present
a maximum of four working and four protection Dual OC-48 T/R
interfaces with no other tributary interfaces present (with either the DX100
or DX140 switch module only)
a maximum of four working and four protection Dual GE interfaces with
no other tributary interfaces present
combinations of working and protection circuit packs, adding up to a
maximum bandwidth of 192 STS-1 signals
Quad OC-3 T/R
HD OC-3 T/R
half-height OC-12 T/R (OC-192 only)
Quad OC-12 T/R
OC-48 T/R
Dual OC-48 T/R (SR, IR and LR)
STS-48 T/R electrical
Dual GE (unprotected) (see Note 3)
Note 1: Each working circuit pack of any type must have the same type of
protection circuit pack in the adjacent slot in the shelf.
Note 2: The circuit packs used are dependant on the shelf configuration.
Note 3: The Dual GE circuit pack can only be used as an unprotected
provisioned can be either protected or unprotected.
The data from the tributaries arrives as differential serial STS-12. Each STS-12
data stream demultiplexes to STS-1 data streams and calculates the appropriate
connection map to perform time slot interchange on the data.
The data multiplexes to its original format before transmitting to the
appropriate transmit interface.
Protection switching
The switch module calculates and stores appropriate connection map contents
for each possible line or tributary protection switch scenario, according to the
network element configuration. If a line or tributary equipment protection
switch is necessary, the system writes the appropriate DOS connection
memory locations to perform the required protection switch.
When a network protection switch is necessary, the switch module performs

K-byte processing and insertion. The switch module also calculates
connection map changes, and updates the connection memories within
SONET protection switching time limits.
Overhead switching
The switch module also performs overhead switching. To perform overhead
switching, the DOS array uses an overhead connection map instead of a data
connection map. During the overhead time slots, the circuit routes some
internal overhead bytes in the STS-12 data streams along separate paths
through the DOS. Some overhead bytes then arrive at a different destination to
that of the data with which they arrived.
The overhead connection map forms a pair of internal Rx buffers and a pair of
internal Tx buffers. Each frame transmits the content of the Rx buffers over a
pair of receive overhead (RXOH) links. The frame also receives the content of
the Tx buffers over a pair of transmit overhead (TXOH) links. The switch
module sets up the overhead connection map to switch each set of overhead
bytes of any STS-1 output exiting the DOS.
Other control functions
The switch module provides the following other control functions:
illuminate the front panel green LED when carrying traffic, and extinguish
the LED when traffic fails
communicate with the microcontroller on the second switch module
through a dedicated link to exchange status and control information
communicate with the control shelf through a GraceLAN link
monitor DOS circuits, phase-locked loop (PLL) and PUPS for failure
provide an RS-232 debug port for testing and background debug mode
(BDM) port for initial programming
Support circuits
The following two circuits support the OC-192 switch modules:
TCS
PUPS
The TCS controls the operation of the OC-192 switch module. The TCS
provides communication between the shelf controller and other circuits on the
switch module. The TCS also generates alarms and activates the LEDs on the
The PUPS generates all the voltages required by the OC-192 switch module.

Figure 1-52
DX65 and DOS switch modules functional block diagram
DX1478_SONET
TXOH
RXOH
TSI ARRAY
64 x 622 Mbit/s
from Line interfaces
(= 4 x STS-192)
64
64
FIRST
DOS
STAGE
MID
DOS
STAGE
64 x 622 Mbit/s
to Line interfaces
(= 4 x STS-192)
THIRD
DOS
STAGE
32 x 622 Mbit/s
from tributary interfaces
= 8 x STS-48 (max)
32
= 32 x STS-12 (max)
= 32 x STS-3 (max)
(Max available = 64 x STS-12)
32
32 x 622 Mbit/s
to tributary interfaces
= 8 x STS-48 (max)
= 32 x STS-12 (max)
= 32 x STS-3 (max)
PLL
622 MHz, frame
622 MHz
VCXO
ESI A
622 MHz,
frame
622 MHz, frame
ESI B
From
partner
Switch
39 MHz
Timing
interlock
Primary
SCG
622 MHz,
622 MHz Secondary frame
SCG
39 MHz To main shelf,
extension shelf
shelf (if used)
Legend
DOS
ESI
MX
PLL
PUPS
RXOH
TCS
TSI
TXOH
VCXO
= Data overhead switch

= External Synchronization interface
= Message exchange
= Phase-locked loop
= Receive overhead
-48V
= Time slot interchange
= Transmit overhead
PUPS
monitors
Active (green)
TCS
Optical signal fail
(yellow)
PUPS
+12V
+5V
+3.3V
To/from
-5 V Shelf controller
via MX
-12V
Fail (red)

Figure 1-53
DX100 and DX140 switch modules functional block diagram
DX1479_SONET
TXOH
RXOH
TSI ARRAY
From Line interfaces:

DX100: 64 x 622 Mbit/s
(= 4 x STS-192)
DX140: 128 x 622 Mbit/s
(= 8 x STS-192)
64 or 128
64 or 128
From tributary interfaces

(main + extension shelves):
64 x 622 Mbit/s
= 16 x STS-48 (max)
= 64 x STS-12 (max)
= 64 x STS-3 (max)
FIRST
DOS
STAGE
MID
DOS
STAGE
THIRD
DOS
STAGE
64
64
To Line interfaces:
DX100: 64 x 622 Mbit/s
(= 4 x STS-192)
DX140: 128 x 622 Mbit/s
(= 8 x STS-192)
To tributary interfaces
(main + extension shelves):
64 x 622 Mbit/s
= 16 x STS-48 (max)
= 64 x STS-12 (max)
= 64 x STS-3 (max)
622 MHz, frame
622 MHz
VCXO
PLL
ESI A
622 MHz,
frame
622 MHz, frame
ESI B
From
partner
Switch
39 MHz
Timing
interlock
Primary
SCG
622 MHz,
622 MHz Secondary frame
SCG
39 MHz To main shelf,
extension shelf
shelf (if used)
Legend
DOS
ESI
MX
PLL
PUPS
RXOH
TCS
TSI
TXOH
VCXO
= Data overhead switch

= External Synchronization interface
= Message exchange
= Phase-locked loop
= Receive overhead
-48V
= Time slot interchange
= Transmit overhead
PUPS
monitors
Active (green)
TCS
Optical signal fail
(yellow)
PUPS
+12V
+5V
+3.3V
To/from
-5 V Shelf controller
via MX
-12V
Fail (red)

Figure 1-54
Switch module (external view)
DX2990p
Circuit pack fail (Red)

Active(Green)
MOR (NTCA11)
The multiwavelength optical repeater (MOR) operates in bidirectional
DWDM line amplified systems. Figure 1-57 shows an external view of the
MOR circuit pack.
MOR and optical service channel module options
The following three versions of the MOR amplifier circuit pack are supported
(see Figure 1-55):
MOR with 1510 nm optical service channel (OSC), NTCA11AK
MOR without OSC, NTCA11BK
1625 nm OSC, NTCA11CK
Figure 1-55
MOR and OSC unit options
F3752
NTCA11Bx
NTCA11Ax
1B Ch
1B Ch
4B Ch
4B Ch
OSC
1510
1R Ch
4R Ch
NTCA11Cx
OSC
1625
1R Ch
OSC 1625
4R Ch
OSC 1510
Legend
B
Ch
OSC
R
= Blue
= Channel
= Optical service channel
= Red
Description
The MOR circuit pack contains the following components.
MOR with 1510 nm OSC - NTCA11AK
The MOR with 1510 nm OSC optically amplifies counter-propagating optical

signals which are symmetrically allocated into two wavelength bands: the Red
band and the Blue band. The MOR can amplify a total of sixteen wavelengths
(16 ), with eight wavelengths (8 ) assigned to co-propagate in each
wavelength band.
The MOR unit also supports a unidirectional out-of-band 1510 nm OSC for
supervisory purposes. The 1510 nm supervisory channel co-propagates with
the Red band channel.
Add/drop wavelength division multiplexing (WDM) couplers embedded into
the MOR Red band amplifier path provide optical access to the 1510 nm OSC.
Because the OSC integrates into the MOR amplifier gain block, you do not
require external add/drop couplers and optical fiber patches. Support of
integrated 1510 nm OSC option on MOR does not erode loss budgets between
sites. Figure 1-56 shows the functional block diagram of the MOR with
1510 nm OSC.
MOR without OSC - NTCA11BK
This MOR optically amplifies counter-propagating optical signals that are

symmetrically allocated into two wavelength bands: the Red band and the Blue
band. The MOR can amplify a total of sixteen wavelengths (16 ), with eight
wavelengths (8 ) assigned to co-propagate in each wavelength band.
The MOR does not include the OSC option.
The block diagram is identical to that of the MOR with 1510 nm OSC
amplifier as shown in Figure 1-56, with the exception that it does not include
the OSC module assembly.
1625 nm OSC - NTCA11CK
The 1625 nm OSC supports a unidirectional out-of-band optical service

channel at 1625 nm for supervisory purposes. You must configure the 1625 nm
service channel to co-propagate with the Blue Band channels. The 1625 nm
OSC module uses the same platform as the MOR unit, but does not support the
optical amplifier gain blocks provided on the MOR. This unit version does not
support optical amplification or power monitoring functionality as provided
with the MOR circuit pack.
Use the 1625 nm OSC module in conjunction with the MOR with 1510 nm
OSC on limited fiber, route diverse or ring applications where all channels
need to propagate through a single line amplified path. You require external
1550/1625 nm WDM couplers for optical access to OSC at 1625 nm.
The block diagram is identical to that of the MOR with OSC amplifier
(Figure 1-56), except there is no erbium-doped fiber amplifier (EDFA) gain
block module.
MOR EDFA gain block module
The MOR unit is based on a two pump, bidirectional optical amplifier

architecture.
Connectors located on the MOR circuit pack faceplate provide optical signal
access. The connector assignments are Blue In/Red Out and Red In/Blue Out.
The counter-propagating Red and Blue band channels route between the
EDFA module and optical connectors located on the circuit pack faceplate.
The 1510 nm OSC signal designment is to co-propagate with Red Band
channels. Access to the 1510 nm OSC is internal to the MOR.
The EDFA module is the core of the MOR amplifier. The main functions of the
EDFA module are as follows:
amplify bidirectional optical signals
extract received optical supervisory traffic
insert transmitted optical supervisory traffic
monitor bidirectional input and output signal power
Each direction of a transmission routes through separate amplifier gain
regions. The input optical signals get energy from a dedicated 980 nm pump
source, producing amplification in both directions. Each optical path includes
WDM splitters and combiners for the pump laser and signal, optical isolator,
and optical gain flattening filters. The Red band gain path also includes a
WDM splitter and combiner for OSC access.
Four PIN photodiodes at the input/output ports of the EDFA gain block module
monitor the power.
MOR motherboard
The motherboard includes a transport control subsystem (TCS), point of use

power supplies (PUPS), and different digital processing components. The
motherboard monitors and controls all MOR functions and acts as the
communication bridge with the OC-192 shelf controller installed in the same
bay.
OSC module
The optional OSC module includes a 1510 nm or 1625 nm transmitter,

receiver, and a service channel overhead processor. This module performs
electro-optical conversion of optical supervisory traffic and routes optical
overhead based data.
Support circuits
The following circuits also support MOR circuit packs and the 1625 nm OSC
circuit pack:
TCS
PUPS
The TCS controls the operation of the MOR circuit packs and the 1625 nm
OSC circuit pack. The TCS provides communication between the shelf
processor and other circuits on the MOR circuit packs and the 1625 nm OSC
circuit pack. The TCS also generates alarms and activates the LEDs on the
The PUPS generates all the voltages required by the MOR circuit packs and
the 1625 nm OSC circuit pack.

Figure 1-56
MOR block diagram
F3733
EDFA Module
EDFA
&
components
Blue Band Out/

Red Band In
Red Band Out/

Blue Band In
Red
Blue
OSC
1510
Red
Blue
Out
Red
In
Blue
In
Optical
Service
Channel Tx
Red
Out
Optical
Service
Channel Rx
Blue
OSC
1510
PUPS
LOS (yellow)
LOS (yellow)
Active (green)
Faceplate
LED control
TCS
& DSP
Optical Overhead
Processor
-48 V
OOH Bus
Fail (red)
LAN
Backplane Interface
Legend
EDFA
LED
LOS
OSC
PUPS
Rx
TCS
Tx
= Erbium-doped fiber amplifier

= Light emitting diode
= Loss of signal
= Optical service channel
= Receive
= Transmit

Figure 1-57
MOR circuit pack (external view)
F5275-MOR_R70
LOS blue band (Yellow)

LOS red band (Yellow)
Fail (Red)
Active (Green)
Optical connector
(Output)
Optical connector
(Input)
MOR Plus (NTCA11)

MOR Plus provides access to each signal band directly at the faceplate of the
circuit pack. MOR Plus has three optical connectors: input, output, and
common. MOR Plus also has one less WDM coupler than the normal MOR.
Figure 1-62 shows an external view of the MOR Plus circuit pack.
The MOR Plus, in comparison to the original MOR, has the following
advantages:
improved performance in preamplifier and post amplifier applications
increase in wavelength capacity and reach
per band dispersion compensation
improvement in compatibility with future optical networking devices that
includes wavelength add/drop multiplexers (ADM) at line amplifier sites
you can insert optical components into the link without reducing the
maximum supported system reach
MOR Plus circuit pack options
There are four versions of the MOR Plus amplifier circuit pack supported:
MOR Plus with Blue-Pre/Red-Post amplifier and unidirectional 1510 nm
OSC, NTCA11NK
MOR Plus with Red-Pre/Blue-Post amplifier and unidirectional 1510 nm
OSC, NTCA11PK
MOR Plus with Blue-Pre/Red-Post amplifier without unidirectional OSC,
NTCA11JK
MOR Plus with Red-Pre/Blue-Post amplifier without unidirectional OSC,
NTCA11KK
Description
The MOR Plus amplifier circuit pack includes the following components.
MOR Plus with Blue-Pre/Red-Post amplifier with 1510 nm OSC - NTCA11NK
The MOR Plus circuit pack provides:

one bidirectional port (the common port for Blue Input and Red Output
signals)
two unidirectional ports (Blue Output and Red Input).
The MOR Plus circuit pack also supports a unidirectional out-of-band
1510 nm OSC for supervisory purposes. The 1510 nm supervisory channel
co-propagates with the Red band channel. Add/drop WDM couplers
embedded into the MOR Red band amplifier path provide optical access to the
1510 nm OSC.
As the OSC integrates into the MOR amplifier gain block, you do not require
external add/drop WDM couplers and associated optical fiber patches. Support
of the integrated 1510 nm OSC option on MOR does not erode the inter-site
loss budget. Figure 1-58 shows the block diagram of the MOR Plus.
MOR Plus with Red-Pre/Blue-Post amplifier with 1510 nm OSC - NTCA11PK
This MOR Plus circuit pack provides:

one bidirectional port (common port for Red Input, Blue Output signals)
two unidirectional ports (Red Output and Blue Input).
This version of the MOR Plus circuit pack also supports a unidirectional
out-of-band 1510 nm OSC for supervisory purposes. The 1510 nm
supervisory channel co-propagates with the Red band channel. Add/drop
WDM couplers embedded into the MOR Red band amplifier path provide
optical access to the 1510 nm OSC. As the OSC integrates into the MOR
amplifier gain block, you do not require external add/drop WDM couplers and
associated optical fiber patches. Support of the integrated 1510 nm OSC
option on MOR does not erode the inter-site loss budget. Figure 1-59 shows a
block diagram for this type of MOR Plus.
MOR Plus with Blue-Pre/Red-Post amplifier without OSC - NTCA11JK

one bidirectional port (common port for Blue Input, Red Output signals)
two unidirectional ports (Blue Output and Red Input).
This version of the MOR Plus does not include the OSC option. The block
diagram is identical to that of the MOR Plus with Blue-Pre/Red-Post and OSC,
except that there is no OSC module assembly. Figure 1-60 shows a block
diagram for this type of MOR Plus.
MOR Plus with Red-Pre/Blue-Post amplifier without OSC - NTCA11KK

one bidirectional port (common port used for Red Input and Blue Output
signals)
two unidirectional ports (Red Output and Blue Input).
This version of the MOR Plus does not include the OSC option. The block
diagram is identical to the MOR Plus with Red-Pre/Blue-Post and OSC, except
that there is no OSC module assembly. Figure 1-61 shows a block diagram for
this type of MOR Plus.
EDFA gain block module, OSC module, motherboard, and support circuits
MOR Plus internal circuits such as the motherboard, OSC module, and support
circuit packs are like the normal MOR circuit pack. The main difference is that
MOR Plus has one less WDM coupler than the normal MOR.

Figure 1-58
MOR Plus with Blue-Pre/Red-Post amplifier and 1510 nm OSC
DX1379
OSC
1510 nm Tx
Red band
input
Red band
post amplifier
Red band and
1510 nm OSC
output
Red
Blue
Blue band
output
Blue band
input
Blue band
pre amplifier
Legend
= MOR Plus faceplate connector
= WDM optical coupler
Figure 1-59
MOR Plus with Red-Pre/Blue-Post amplifier and 1510 nm OSC
DX1380
OSC
1510 nm Rx
Red band
pre amplifier
Red band
output
Red band and

1510 nm OSC
input
Red
Blue
Blue band
output
Blue band
input
Blue band
post amplifier
Legend

Figure 1-60
MOR Plus with Blue-Pre/Red-Post amplifier and no OSC
DX1378
Red band
input
Red band
post amplifier
Red band
output
Red
Blue
Blue band
output
Blue band
input
Blue band
pre amplifier
Legend
Figure 1-61
MOR Plus with Red-Pre/Blue-Post amplifier and no OSC
DX1377
Red band
pre amplifier
Red band
input
Blue band
output
Red band
output
Red
Blue
Blue band
post amplifier
Blue band
input
Legend

Figure 1-62
MOR Plus circuit pack (external view)
F5142-MOR_R70
LOS blue band (Yellow)

LOS red band (Yellow)
Fail or mismatch (Red)
Active (Green)
Optical connector (Blue output)

Optical connector (Red input)
Optical connector (Common)
Partitioned OPC
The partitioned operations controller (OPC) has three separate circuit packs:
OPC controller (NTCA50)
OPC interface (NTCA52)
OPC storage (NTCA51AA and NTCA51AB)
If you install a partitioned OPC, the network element control shelf must
contain all three of these circuit packs.
Together, these three circuit packs perform the following tasks:
provide storage and software load upgrades
communicate with the shelf controller circuit pack and maintenance
interface circuit pack
provide operations, administration, maintenance, and provisioning

(OAM&P) functionality
allow the control shelf to communicate with the outside world
The OPC storage circuit pack provides one interface for the OPC removable
media (NTCA53).
Figure 1-63 shows the functional block diagram of the OPC.

Figure 1-63
Partitioned OPC block diagram
F3746-192_R21
SCSI bus
LED driver
OPC storage
card presence
OPC
storage
circuit
pack
Serial Signals
NM Ethernet
LED driver
To/from
back-plane
OPC
controller
circuit
pack
OPC
I/F
circuit
pack
To/from
OPC removable
media
9-pin
RS-232 I/F
9-pin
10 Base T Ethernet I/F
25-pin
RS-232
Ethernet
card presence
Maintenance
I/F
Legend:
card presence
GraceLan
OPC controller
card presence
SC
A and B
MX A
and
MX B
I/F = Interface
LED = Light emitting
diode
MX = Maintenance
exchange
circuit pack
NM = Network
Manager
OPC = Operations
controller
SC = Shelf controller
circuit pack
SCSI = Small Computer
System Interface
OPC controller (NTCA50)

The OPC controller circuit pack provides OAM&P functionality. The OPC
controller communicates with the OPC interface circuit pack, the OPC storage
circuit pack, the shelf controller circuit pack, and the maintenance interface
circuit pack.
Figure 1-64 shows a functional block diagram of the OPC controller.
Figure 1-65 shows an external view of the OPC controller circuit pack.
The OPC controller contains the following components.
External communications
The OPC controller circuit pack has one 10BaseT Ethernet connection (using
the backplane) for external communications through the OPC interface circuit
pack.
Internal communications
The OPC controller circuit pack has one 10BaseT Ethernet connection (using
the backplane) for internal shelf controller communications through the
maintenance interface circuit pack. The OPC controller circuit pack also has
buses to communicate with the OPC storage circuit pack and the OPC interface
circuit pack.
LED control
The OPC controller circuit pack drives the LEDs for all three OPC circuit
packs: the OPC controller, the OPC interface, and the OPC storage circuit
pack. The OPC storage circuit pack controls the hard drive activity LED on the
OPC storage circuit pack only.
Point-of-use power supply (PUPS)
The OPC controller circuit pack comes with a point-of-use power supply
(PUPS) that generates all the voltages required for the correct operation of the
unit.

Figure 1-64
OPC controller circuit pack block diagram
F3750-192_R21
Flash
memory
NM
DRAM
SC
CPU
Port A & B
Green
(active)
Red
(fail)
+3.3V
-48V
PUPS
+5V
Legend:
CPU = Central Processor Unit
DRAM = Dynamic Random Access Memory
NM = Network Manager
PUPS = Point of Use Power Supply
SC = Shelf Controller

Figure 1-65
OPC controller circuit pack (external view)
F3757_R21
Fail (Red)
Active(Green)
OPC interface (NTCA52)

The OPC interface circuit pack provides the external customer interfaces for
the control shelf. The OPC also communicates with the maintenance interface
circuit pack, and with the OPC controller circuit pack. Figure 1-66 shows a
functional block diagram. Figure 1-67 shows an external view of the OPC
The OPC interface contains the following components.
External communications
The OPC interface circuit pack has three ports on its faceplate:
one 9-pin RS-232 interface for X.25 communication
one 25-pin RS-232 interface for printer, terminal, and modem support
one 10BaseT Ethernet port
The OPC controller has an Ethernet bus and a serial processor extension bus to
communicate through the backplane with the OPC controller circuit pack.
LED control
The OPC controller circuit pack controls the faceplate LEDs of the OPC
The OPC interface circuit pack is equipped with a point-of-use power supply
(PUPS) that generates all the voltages required for the correct operation of the
unit.

Figure 1-66
OPC interface block diagram
F3748-192_R21
Tx/Rx
Transformer
To/from
backplane
9-pin
RS-232
25-pin
RS-232
9-pin
10BaseT Ethernet
Tx/Rx
control
From
OPC
controller
LED
input
To/from
OPC controller
Green
(active)
Red
(fail)
-48V
FPGA
PUPS
To/from
MI
+5V
Legend:
FPGA = Field Programmable Gate Array
LED = Light Emitting Diode
MI = Maintenance Interface
OPC = Operations Controller
Rx = Receive
Tx = Transmit

Figure 1-67
OPC interface circuit pack (external view)
F3760_R21
9-Pin X.25 RS-232

connector
25-Pin RS-232
connector
9-Pin 10 Base T
Ethernet connector
Fail (Red)
Active (Green)
OPC storage (NTCA51AA and NTCA51AB)

The OPC storage circuit pack includes a small computer system interface
(SCSI) drive, electrically erasable programmable read-only memory
(EEPROM), and a removable media interface. There are two types of OPC
storage circuit pack:
hard disk drive (NTCA51AA)
solid state disk drive (NTCA51AB)
Both types of circuit pack support the OPC removable media NTCA53.
Figure 1-68 shows a functional block diagram of the OPC storage. Figure 1-69
shows an external view of the OPC storage circuit pack.
The OPC storage contains the following components.
Removable media interface
The OPC storage circuit pack provides one interface for the removable media.
The removable media interface provides software download, save, and restore
capabilities for the network element.
The OPC storage circuit pack has a processor bus and a SCSI bus to
communicate through the backplane with the OPC controller circuit pack.
Hard disk drive
The SCSI hard disk drive comes as part of the OPC storage circuit pack for
UNIX applications.
EEPROM
The EEPROM contains information about the OPC storage circuit pack, such
as flash memory size, circuit pack serial number, hardware or software
interface vintage. The EEPROM also contains the product engineering code
(PEC) and Common Language Equipment Identifier (CLEI) code bytes.
LED control
The OPC controller circuit pack controls the faceplate LEDs of the OPC
storage circuit pack. The OPC storage circuit pack controls the hard drive
activity LED on the OPC storage circuit pack only.
Point of use power supply (PUPS)
The OPC storage circuit pack comes with a PUPS that generates all the
voltages required for the correct operation of the unit.

Figure 1-68
OPC storage block diagram
DX1561
OPC storage circuit pack
NVS
To/from
removable
media
Removable
media
I/F
Hard drive
or solid-state
drive
OPC
controller
circuit
pack
Green
(Hard drive
activity)
Green
(active)
LED
input
Yellow
(card shutdown
in progress)
Red
(card fail)
+5V
-48V
PUPS
+12V
-12V
Legend:
I/F = InterFace
LED = Light Emitting Diode
NVS = Non Volatile Storage
OPC = OPerations Controller

Figure 1-69
OPC storage circuit pack (external view)
F3759-192_R60
IO
UT
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CT
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PA R CT
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be oth
as or epla
r h ped be r
o
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tec op st
de en dr d mu
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If t as be a
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SE
Removable media
interface
CA
UT
Re
m
sh ovin
u
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Do e o ownOPC
no per wil pr
Ha t re atin l coior to
Sh rd Dmov g sy rrup
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n
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lit. gres
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Sh
utd
ow
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Ha
Pro
rd
gre
Dis
ss
kA
cti
vit
y
Card shutdown in
progress (Yellow)
Card fail (Red)
Active (Green)
OPC removable media (NTCA53)

The 122 M/byte OPC removable media provides software download, save, and
restore capabilities for network elements under the OPC span of control.
You insert the OPC removable media in the slot on the faceplate of the OPC
storage circuit pack.
Figure 1-70 shows a view of the OPC removable media.
Figure 1-70
OPC removable media
F3758_R21
Orderwire (NTCA47)
The orderwire circuit pack is supported in OPTera Connect DX and OC-192
network elements. For information on the orderwire facility, please refer to the
Orderwire User Guide, NTCA66CA.
Shelf controller (NTCA41)

The shelf controller (SC) is the central processor for the system.
The main functions of the shelf controller are as follows:
report alarms
support the network element user interface (NE UI)
provide RS-232 and Ethernet communication ports
handle data communications channel (DCC) routing
collect performance monitoring data
coordinate network element software download and upgrade
See Figure 1-71 for a functional block diagram of the shelf controller.
Figure 1-72 shows an external view of the shelf controller circuit pack.
The 32 MBytes RAM SC is used in add-drop multiplexer (ADM)
configurations only. The 16 Mbytes RAM is used in regenerators only.
RS-232 and Ethernet ports
The shelf controller supports two RS-232 ports and one Ethernet port. One
RS-232 port is available through a 25-pin D-subminiature connector located
on the local craft access panel (LCAP). The second RS-232 port, and the
Ethernet port, are available through 9-pin D-subminiature connectors located
on the faceplate of the maintenance interface circuit pack.
The shelf controller communicates with all the circuit packs in the OPTera
Connect DX bay and OC-192 bay. The shelf controller controls alarm
reporting, fault detection, protection, performance monitoring data collection,
and software management.
The shelf controller communicates with the following transport control
subsystem (TCS) based circuit packs supported in the OPTera Connect DX
and OC-192 bays through the message exchange circuit pack:
Quad T/R interfaces (NTCA33, NTCA36)
HD OC-3 T/R interfaces (NTCA35AA, NTCA35AB) (OPTera Connect
DX network elements only)
OC-12 half-height T/R interface (NTCA31B) (OC-192 network elements
only)
OC-48 short reach T/R interface (NTCA30AL/CK)

OC-48 long reach T/R interface (NTCA30AN)
Quad OC-48 T/R interfaces (NTWR31) (OPTera Connect DX network
elements only)
Dual OC-48 short reach T/R interface (NTWR30AA) (OPTera Connect
Dual OC-48 intermediate reach T/R interface (NTWR30BA) (OPTera
Connect DX network elements only)
Dual OC-48 long reach T/R interface (NTWR30CA) (OPTera Connect DX
network elements only)
STS-48 T/R electrical interface (NTCA34)
Dual Gigabit Ethernet extended reach interface (NTCA90GA)
Dual Gigabit Ethernet long reach interface (NTCA90CA)
Dual Gigabit Ethernet short reach interface (NTCA90EA)
OC-192 T/R interface (NTCA06) (OPTera Connect DX network elements
only)
OC-192 DWDM TriFEC T/R interface (NTCF06) (OPTera Connect DX
OC-192 short reach T/R interface (NTWR06AB) (OPTera Connect DX
OC-192 intermediate reach T/R interface (NTWR06CA) (OPTera Connect
OC-192 long reach T/R with APD interface (NTWR06B) (OPTera
Connect DX network elements only)
OC-192 XR (NTCA04) (OC-192 network elements only)
OC-192 merged XR/WT (NTCF04) (OC-192 network elements only)
OC-192 DWDM transmit interface (NTCA01) (OC-192 network elements
only)
OC-192 DWDM regenerator/transmit interface (NTCA03) (OC-192
OC-192 short reach receive interface (NTCA02) (OC-192 network
elements only)
OC-192 demultiplexer (NTCA05) (OC-192 network elements only)
Switch module (NTCA26, NTCA24) (NTCA24 is used in OC-192
Orderwire (NTCA47) (OC-192 network elements only)
MOR (NTCA11) (OC-192 network elements only)

MOR Plus (NTCA11) (OC-192 network elements only)
The shelf controller also communicates with the OPC circuit packs (through
the maintenance interface circuit pack), the message exchange circuit pack,
and the parallel telemetry circuit pack.
Flash memory
The shelf controller flash memory contains one copy of its software, one copy
of the system provisioning data, and a software library.
You use the software library when you replace a circuit pack. The software
library makes sure that the circuit pack you are inserting runs the appropriate
software version, according to the systems provisioning data.
Support circuits
The PUPS generates all the voltages required by the shelf controller.

Figure 1-71
Shelf controller block diagram
F3236-192_R21
Filters and
Transformers
Ethernet
DRAM
Buffer
CPU
Buffer
Flash
memory
GraceLan
interface
RS-232 (MI)
RS-232 (LCAP)
RS-530 (MI)
(future)
MI LEDs control
output bit ports
input bit ports
to/from MX A
and MX B
Legend:
CPU =
DRAM =
LCAP =
MI =
MX =
LED =
Central Processing Unit

Dynamic Random Access Memory
Local Craft Access Panel
Maintenance Interface
Message eXchange
Light Emitting Diode

Figure 1-72
Shelf controller circuit pack (external view)
F3192-192
Fail (Red)
Active(Green)
Maintenance interface (NTCA42)

The maintenance interface (MI) works with the shelf processor. The MI circuit
pack contains the RS-232 and the Ethernet interfaces.
Two MI versions are available: the 32 MByte (NTCA42AA) and the
128 MByte (NTCA42BA). The OPTera Connect DX bay supports only the
128 Mbyte MI. The OC-192 bay supports both MI types.
The MI performs the following functions:
provide access to RS-232 and Ethernet interfaces
support circuit pack inventory
collect status signals
monitor processor sanity
provide interface between the LCAP and the shelf controller
provide flash memory storage

drive bay level alarm indicators
support a software library
communicate with the OPC
Figure 1-73 shows a functional block diagram of the MI. Figure 1-74 shows an
external view of the MI circuit pack.
RS-232 and Ethernet
The maintenance interface supports two RS-232 interfaces (A and B) from the
shelf controller. Interface A connects to a male 9-pin D-subminiature
connector located on the faceplate of the maintenance interface. Interface B
connects to the LCAP through the control shelf backplane.
The maintenance interface provides three Ethernet connections for the
Ethernet port provided by the shelf controller circuit pack. You can access this
Ethernet interface through three 9-pin D-subminiature connectors located on
the faceplate of the maintenance interface.
Circuit pack inventory
The MI circuit pack reads circuit pack inventory from the circuit packs that are
not connected to the shelf controller. These circuit packs include the
breaker/filter modules, the LCAP, and the synchronization, alarm, and
telemetry terminations (SATT).
Status signals
Status signals go to the MI by the fan modules and the breaker/filter modules.
The MI reports these signals to the shelf controller.
Processor sanity
The MI monitors the status of the shelf controller. The shelf controller uses a
sanity timer. The shelf controller refreshes the timer every 30 seconds. The MI
activates major visual and audible alarms if the shelf processor does not refresh
the timer.
LCAP interface
The MI acts as an interface between the shelf controller and the LCAP. The MI
detects the alarm cutoff (ACO) and lamp test signals originated by the LCAP
and notifies the shelf controller. The MI controls and monitors the state of the
relays (located on the LCAP) that control the ACO circuit.
Flash memory
The flash memory located on the MI stores a second copy of the network
element shelf controller software and provisioning data. The flash memory
also stores the software library. The first copy in the shelf controller flash
memory is only for shelf controller software and provisioning data.
Data backup and software storage between the shelf controller and MI allows
replacement of both circuit packs while the system is in service. Do not replace
both circuit packs at the same time.
Use the software library when you replace a circuit pack that contains transport
control subsystems (TCS). The software library makes sure that the circuit
packs you are inserting run the appropriate software version, according to the
system software. The software library also updates with a software upgrade.
Bay alarms
The shelf controller controls the critical, major, and minor alarm relays. Both
critical and minor alarm relays appear on the MI. The major alarm relay is on
the SATT. The relay raises a major alarm if the MI fails or if you remove the
MI.
The shelf controller controls the LEDs on the MI.
The MI also comes with a PUPS that generates all the voltages required for the
correct operation of the unit.

Figure 1-73
MI block diagram
F3237-192_R21
RS-232
Interface
RS-232 to SC
Ethernet to SC
Ethernet
Interfaces
Ethernet to
OPC controller
circuit pack
RS-232
Interface
RS-232 to SC
To/from SC
DB9 connector on faceplate
3 DB9 connectors on faceplate
DB25 connector on LCAP
Flash
memory
to SATT
Alarm status
ACO to SC
ACO/Lamp test
from LCAP
Sanity timer
Status
Fans
From SC
Bay I/F
alarms
MI
LEDs
+5 V
-48 V
To/from SC
PUPS
Inventory
-5 V
Legend:
ACO =
I/F =
LCAP =
LED =
MI =
PUPS =
SATT =
SC =
Alarm Cut Off

Interface
Local Craft Access Panel
Light Emitting Diode
Maintenance Interface
Point of Use Power Supply
Synchronization, Alarms and Telemetry Terminations
Shelf Controller

Figure 1-74
MI circuit pack (external view)
DX1562
RS-232
port
Port 1
10BaseT
Ethernet ports
Port 2
Port 3
FW-3187

There are three types of ESI circuit packs:
NTCA44AA, which provides external inputs and outputs at the DS1 line
rate of 1.544 Mbit/s
NTCE44AA, which provides external inputs and outputs at the E1 line rate
of 2 Mbit/s or the 2 MHz line rate
NTCE44BA, which provides external inputs and outputs at the 2 MHz line
rate
The external synchronization interface (ESI) circuit pack provides a 38 MHz
reference output for shelf timing. The ESI circuit pack adjusts the clock rate
according to the specifications for external timing (to either 1.544 Mbit/s,
2 Mbit/s or 2 MHz).
The control shelf is fitted with two ESI circuit packs that operate as a working
and protection pair.
If the synchronization references are being supplied to the bay, ESI circuit
pack NTCE44AA must be fitted into the control shelf of a network element
with a universal synchronization, alarms, and telemetry terminations
(uniSATT) connector block so that both the E1 (2 Mbit/s) and 2 MHz line rates
are supported. This circuit pack can operate at the 2 MHz line rate in a network
element with a 2 MHz SATT. This circuit pack cannot operate in a network
element with a 1.544 Mbit/s SATT, unless the network element is using line
timing (instead of external synchronization references).
The main functions of the ESI are as follows:
provide a stable reference timing source for the system
provide one reference output at the DS1 line rate of 1.544 Mbit/s, the E1
line rate of 2 Mbit/s, or the 2 MHz line rate
Figure 1-75 shows a functional block diagram of the 1.544 Mbit/s ESI circuit
pack. Figure 1-76 shows a functional block diagram of the 2 Mbit/s ESI circuit
pack. Figure 1-77 shows a functional block diagram of the 2 MHz ESI circuit
pack. The ESI circuit packs look identical to the circuit pack shown in
Figure 1-72.
For the 1.544 Mbit/s and 2 MHz ESI circuit packs, the building-integrated
timing supply (BITS) and OC-192 interfaces are used for timing generation,
while only OC-192 interfaces are used for timing distribution. These ESI
circuit packs reduce these input signals to the rate of 8 kHz. The system
monitors the input signals for frequency and forms one timing reference pool
for timing generation and another for timing distribution. These ESI circuit
packs select one reference for timing generation and another for timing
distribution from these timing reference pools.
For the 2 Mbit/s ESI circuit pack, the building-integrated timing supply (BITS)
and OC-192 interfaces are used for both timing generation and timing
distribution. This ESI circuit pack reduces these input signals to the rate of
8 kHz. The system monitors the input signals for frequency and forms a timing
reference pool. This ESI circuit pack selects one reference from this timing
reference pool to provide both timing generation and timing distribution.
In the event of a failure of all timing distribution sources:
for the 1.544 Mbit/s ESI circuit pack, the external timing output sends an
alarm indication signal (AIS) and a Tx AIS alarm becomes active
for the 2 MHz ESI circuit pack, the external timing output signal is
squelched and a Tx AIS alarm becomes active
for the 2 Mbit/s ESI circuit pack, either the external timing output sends an
AIS and a Tx AIS alarm becomes active (with the E1 line rate), or the
external timing output is squelched and a Tx AIS alarm becomes active
(with the 2 MHz line rate)
Note: There is only one timing reference pool for the 2 Mbit/s ESI circuit
pack. A failure of all timing generation sources implies a failure of all
timing distribution sources.
In the event of a failure of all timing generation sources, the ESI circuit pack
operates in freerun or holdover mode. When the ESI circuit pack operates in
freerun or holdover mode, the internal oscillator of the ESI circuit pack
generates the timing. If the ESI circuit pack does not generate the timing, it
selects the same reference and both ESI circuit packs follow in parallel. The
selection of the timing generation reference does not depend on the selection
of the timing distribution reference.
In freerun or holdover mode, the ESI circuit pack provides a slave equipment
clock (SEC) output of accuracy 4.6 ppm. The shelf clock located on the switch
module derives its timing output from the ESI circuit pack. In the event of
failure or removal of both ESI circuit packs, the shelf clock will run in freerun
mode with an accuracy of 20 ppm.
The shelf controller controls the LEDs on the ESI circuit pack through the
transport control subsystem (TCS).
The ESI circuit pack comes with a PUPS that generates all the voltages
required for the correct operation of the unit.

Figure 1-75
1.544 Mbit/s ESI block diagram
DX4867p
External
input I/F
Input from
a BITS
Timing
distribution
Output
I/F
Timing
generation
Timing
filter
DS1 outputs
to SATT
Timing
reference
pool
Input from
OC-192 or
STM-64 I/F
Backplane
I/F
Timing output to
switch modules A & B
Timing output to
mate ESI
Active
(green)
To/from
mate ESI
TCS+
Fail
(red)
+12 V
PUPS
-48 V
-12 V
+5 V
-5 V
To/from
shelf controller
Legend
BITS = Building-Integrated Timing Supply
ESI = External Synchronization Interface
I/F = Interface
SATT = Synchronization, Alarms and Telemetry Terminations
TCS = Transport Controlled Subsystem

Figure 1-76
2 Mbit/s ESI block diagram
DX4868p
Input from
a BITS
External
input I/F
Timing
distribution
Output
I/F
Timing
generation
Timing
filter
E1 or 2 MHz
outputs to SATT
Timing
reference
pool
Input from
OC-192 or
STM-64 I/F
Backplane
I/F
Timing output to
Timing output to
mate ESI
Active
(green)
To/from
mate ESI
TCS+
+12 V
PUPS
-48 V
-12 V
+5 V
-5 V
To/from
shelf controller
Legend
I/F = Interface
Fail
(red)

Figure 1-77
2 MHz ESI block diagram
DX4869p
Input from
a BITS
External
input I/F
Timing
distribution
Output
I/F
Timing
generation
Timing
filter
2 MHz outputs
to SATT
Timing
reference
pool
Input from
OC-192 or
STM-64 I/F
Backplane
I/F
Timing output to
Timing output to
mate ESI
Active
(green)
To/from
mate ESI
TCS+
Fail
(red)
+12 V
PUPS
-48 V
-12 V
+5 V
-5 V
To/from
shelf controller
Legend
I/F = Interface
Message exchange (NTCA48)

The message exchange (MX) circuit pack routes the data communications
channel (DCC) and enables communications between circuit packs supplied
with a processor. The MX circuit pack also enables communication between
the shelf controller and circuit packs supplied with a processor or transport
control subsystem (TCS). See Figure 1-78.
Note: You must install at least one MX circuit pack in the control shelf. If
you install two MX circuit packs, one can act as the working circuit pack,
and one can act as the protection circuit pack. Installing two MX circuit
packs is optional, but highly recommended.
The MX circuit pack performs the following functions:
support circuit pack presence detection with the shelf controller
support DCC messaging
support operations, administration, and maintenance (OAM) messages
between circuit packs supplied with a processor
See Figure 1-79 for a functional block diagram of the MX circuit pack. The
MX circuit pack is identical to the circuit pack shown in Figure 1-72.
Circuit pack presence
The MX circuit pack stores a circuit pack presence bit for every circuit pack
that has a processor (TCS). The shelf controller reads these bits through the
maintenance interface (MI). If you remove a circuit pack, the shelf controller
detects a change in circuit pack presence and passes this information to the
shelf controller.
The shelf controller controls the LEDs on the MX circuit pack.
The MX circuit pack also comes with a PUPS that generates all the voltages
required for the correct operation of the unit.
GraceLan/MMSB
GraceLan is the protocol used by the system for both DCC routing and internal
system control messages. System control functions include:
fault reporting
performance monitoring
data collection
software upgrade
circuit pack configuration
The GraceLan messaging system connects the SC and the GraceLan nodes
together at the two MX circuit packs.
The following circuit packs form GraceLan nodes:

shelf controller
ESI
all circuit packs in the main shelf
Each GraceLan node has a separate connection to each of the MX circuit
packs identified by a slot ID number, which identifies its position in the
network element.
Figure 1-78
Communications between the MX circuit pack and other circuit packs in the system
F3239-192_R40
MI
OPC-C
OPC-S
SC
OPC-I
Circuit
pack 1
MX G1
Circuit
pack x
MX G2
Circuit
pack y
Circuit packs equipped with a processor (TCS)

Legend:
MI = Maintenance Interface module
MX = Message eXchange module
OPC-C = Operations Controller Control module
OPC-I = Operations Controller Input/Output module
OPC-S = Operations Controller Storage module
SC = Shelf Controller module

Figure 1-79
MX circuit pack block diagram
F3240
To MI
Active
(green)
S_PEZ
interface
Fail
(red)
Card 1
Card x
GraceLan
interface
Selector
System card
presence to SC
To/from SC
MMSB
interface
To SC
Legend:
Control/
Timing
Timing
distribution
+5 V
-48 V
PUPS
MI = Maintenance Interface
MMSB = Multi-Master Serial Bus
S_PEZ = Serial Processor Extension bus
SC = Shelf Controller
-5 V
Parallel telemetry (NTCA45AA)

The parallel telemetry circuit packs provide the interface to the customers
central alarm reporting equipment. Relay contact outputs and digital detection
inputs provide access.
The main functions of the parallel telemetry circuit pack are as follows:
provide 32 dry contact compatible inputs
provide eight Form C (break before make) relay outputs
Figure 1-80 shows a functional block diagram of the parallel telemetry circuit
pack. Figure 1-81 shows an external view of the parallel telemetry circuit pack.
Telemetry input interface
The 32 parallel telemetry inputs connect through a 44-pin D-subminiature
connector located on the circuit pack faceplate. They connect a network
element to the external triggers for events (such as an open door or a high shelf
temperature). The parallel telemetry inputs are active when connected to 0V.
When an open input changes to closed, a trigger trips and the network element
software raises an environmental alarm.
The parallel telemetry circuit pack maps the state of all 32 parallel telemetry
inputs into the shelf controller addressing space.
Telemetry output interface
The parallel telemetry circuit packs access the eight telemetry outputs through
a 25-pin D-subminiature connector located on the circuit pack faceplate. Each
output includes a three wire set: a common connection (COM), normally
opened (NO) signal, and a normally closed (NC) signal.
There are two possible states for each output, they are as follows:
NC connected to COM and NO floating
NO connected to COM and NC floating
The parallel telemetry circuit pack maps each of the eight parallel telemetry
outputs into the shelf controller addressing space.
The field programmable gate array (FPGA) controls the circuit pack LEDs.
The parallel telemetry circuit pack also comes with a PUPS that generates all
the voltages required for the correct operation of the unit.

Figure 1-80
Parallel telemetry circuit pack block diagram
F3241
All inputs are

Active Low
S_PEZ to/from
shelf controller
input
NO
Input
I/F
1
Output
I/F
1
COM
ground
NC
FPGA
NO
input
Output
I/F
8
Input
I/F
32
COM
NC
ground
Active
(green)
Fail
(red)
Legend:
COM = COMmon
FPGA = Field Programmable Gate Array
I/F = InterFace
NC = Normally Closed
NO = Normally Opened
PUPS = Point-of-Use Power Supply
S_PEZ = Serial Processor Extension bus
-48 V
PUPS
Note: The parallel telemetry cable has only eight ground pins.
Each input can be grounded to any of the ground pins.
+5 V

Figure 1-81
Parallel telemetry circuit pack (external view)
F3195-192
25-Pin telemetry
output connector
44-Pin telemetry
input connector
Fail (Red)
Active(Green)
Breaker/filter module (NTCA40AA)

Located in the control shelf, the breaker/filter module accepts three 30 Amp
feeds from the customer power plant. The module provides current limited
power outputs required by the system.
The main functions of the breaker/filter module are as follows:
provide low frequency filtering
balance load for input feeds
provide seven current limited outputs
provide a 60 W cooling unit output
Figure 1-82 shows a functional block diagram of the breaker/filter module.
Figure 1-83 shows an external view of the breaker/filter module.
Each of the three input feeds has a dedicated filter to prevent battery
oscillation. A low voltage monitor generates an alarm if the voltage of a feed
drops below 41.5 V 1.5 V. The three input feeds are current limited by
circuit breakers.
The breaker/filter module can generate filter failures, power losses, trip alarms,
and low voltage warnings. The power on and alarm detection circuits control
the circuit pack LEDs, and communicate with the shelf controller.

Figure 1-82
Breaker module functional block diagram
F3242-192_R40
48 V to
cooling unit
Feed from
power plant
Feed from
power plant
Feed from
power plant
Low
voltage
monitor
Filter
Low
voltage
monitor
Filter
Low
voltage
monitor
Filter
Circuit
Breaker 2
48 V to
transport shelf
Circuit
Breaker 3
48 V to
transport shelf
Circuit
Breaker 4
48 V to
transport shelf
Circuit
Breaker 5
48 V to
transport shelf
Circuit
Breaker 1
48 V to
control shelf
Circuit
Breaker 6
Circuit
Breaker 7
Active
(green)
Alarm
and
Pwr On
detection
48 V to
tributary, or dense
regenerator, or line
extension shelf
48 V to
tributary, or dense
regenerator, or line
extension shelf
Fail
(red)
To shelf controller

Figure 1-83
Breaker/filter module (external view)
F3191-192
Input feeds
Circuit breaker
switches (7)
Fail (Red)
Active (Green)
Fan module (NTCA85BA, NTCA85EA)

Note: Fan module NTCA85BA is used in OC-192 bays only. Fan module
NTCA85EA is used in OPTera Connect DX bays only.
The environmental control panel (ECP) has three fan modules that operate at
approximately 80% of maximum speed under normal conditions. The
temperature threshold set at the factory increases or decreases the speed of the
fan module.
The fan controller monitors all operations of the fan including: speed, state of
the remote temperature sensors, and the reporting of alarms to the shelf
controller. In the event of a failure, the fan controller sends an alarm signal to
the shelf controller and to the other fans.
During normal operation of the unit, a green LED illuminates on the front
panel of the fan. In the event of a failure, a red LED on the front panel of the
fan illuminates.
At low temperatures (below 0C), the fan is off. At high temperatures (above
55C) the fan operates at a higher speed and signals other fans to increase their
speed. When the sensor temperature exceeds 70C, the fan controller sends a
high shelf temperature alarm to the shelf controller.
Figure 1-84 shows a functional block diagram of the fan module. Figure 1-85
shows an external view of a fan module used in OPTera Connect DX bays
(NTCA85EA). Figure 1-86 shows an external view of a fan module used in
OC-192 bays (NTCA85BA).

Figure 1-84
Fan module functional block diagram
F3243
LED control
Fan failed
Fan OK out
LED control
Green/Red
Operations
monitor
RED
Control
Fan OK in
High temp (+70C)
Sensor
GREEN
Fan speed
Sensor OK
Temperature
interface
+50oC
0oC
Speed
control
All fans OK
Fan position L
Fan position R
Fan present
Ulog
Supply (-35V -75Vl)
Supply return (GND)

Figure 1-85
OPTera Connect DX fan module - NTCA85EA (external view)
DX0468p
Unlock position
Lock position
Figure 1-86
OC-192 fan module - NTCA85BA (external view)
DX2647p
Fail (Red)
Active (Green)
Lock
Filler card (NTCA49/59)

The filler cards are available in the following four formats:
transport shelf, tributary extension shelf, and line extension shelf filler card
(single slot, NTCA49AA)
transport shelf filler card (double slot, slots 14 and 15 only, NTCA49AB)
control shelf filler card (single slot, 1 inch, NTCA59AA)
transport shelf and tributary extension shelf half-height filler card (single
slot, NTCA49AC)
Note: If there is one half-height OC-12 circuit pack in a slot, use a
half-height filler card NTCA49AC for the other half slot. In other cases,
you must use a single slot full-height filler card (NTCA49AA).
All unused or empty slots in the control shelf, transport shelf, tributary
extension shelf, and line extension shelf must contain the appropriate filler
card. The filler cards have two distinct purposes. The main transport shelf and
the tributary extension shelf require filler cards for correct cooling. The control
shelf requires filler cards to protect against electromagnetic interference (EMI)
emissions.
Filler cards have no LEDs on their faceplate, nor do they contain any internal
circuits. Figure 1-87 shows the four available filler cards.

Figure 1-87
Filler cards
F3526-192_R40
Transport shelf,
tributary extension
shelf, dense regenerator
extension shelf, and line extension
shelf filler card, single slot
Control shelf
filler card,
single slot
Transport shelf
filler card, double
slot, slots 14 and 15
Transport and
tributary extension
shelf half-height filler
card, single slot
Nortel Networks
OPTera Connect DX
optical switch
Circuit Pack Descriptions
Copyright 20002004 Nortel Networks, All Rights Reserved
The information contained herein is the property of Nortel
Networks and is strictly confidential. Except as expressly
authorized in writing by Nortel Networks, the holder shall keep all
information contained herein confidential, shall disclose the
information only to its employees with a need to know, and shall
protect the information, in whole or in part, from disclosure and
dissemination to third parties with the same degree of care it uses
to protect its own confidential information, but with no less than
reasonable care. Except as expressly authorized in writing by
Nortel Networks, the holder is granted no rights to use the
information contained herein.
Nortel Networks, the Nortel Networks logo, the Globemark,
OPTera, and Preside are trademarks of Nortel Networks.
323-1521-102
Standard Rel 6
April 2004
Printed in Canada and in the United Kingdom

323-1521-102.r06 Circuit Pack Descriptions

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Printed in Canada and in the United Kingdom

About this document

Circuit pack LEDs 1-4

About this document

Circuit Pack Descriptions 323-1521-102 Rel 6 Iss 1 Standard Apr 2004

vi About this document

OPTera Connect DX SONET NTP Library

About the OPTera

OC-48 NTP Library

OPTera Long Haul

About this document vii

Circuit Pack Descriptions 323-1521-102 Rel 6 Iss 1 Standard Apr 2004

viii About this document

Circuit pack descriptions

Circuit Pack Descriptions 323-1521-102 Rel 6 Iss 1 Standard Apr 2004

1-2 Circuit pack descriptions

Quad OC-3 T/R interface with four SDCC

Quad OC-12 T/R interface with one SDCC

Quad OC-12 T/R interface with four SDCC

Hexadeca (HD) OC-3 T/R interface with 0 SDCC NTCA35AA

OPTera OC-192 Regen Page

HD OC-3 T/R interface with 16 SDCC

OC-12 half-height T/R interface

OC-48 short reach T/R interface

OC-48 long reach T/R interface

OC-48 DWDM T/R interface

Quad OC-48 short reach T/R interface

Quad OC-48 intermediate reach T/R interface

Dual OC-48 short reach T/R interface

Dual OC-48 intermediate reach T/R interface

Dual OC-48 long reach T/R interface

STS-48 electrical T/R interface

Dual Gigabit Ethernet (GE) long reach (ZX)

Dual Gigabit Ethernet (GE) long reach (LX)

Dual GE short reach (SX) interface

OC-192 DWDM triple forward error correction

OC-192 short reach T/R interface

OC-192 intermediate reach T/R interface

OC-192 long reach T/R with Avalanche Photo

OC-192 merged XR/WT interface

Circuit pack descriptions 1-3

OC-192 DWDM transmit interface

OC-192 DWDM Rg/Tx interface

OC-192 short reach receive interface

DX100 switch module

DX140 switch module

DOS switch module

OPTera OC-192 Regen Page

MOR and MOR Plus circuit packs

OPC removable media

Maintenance interface (MI)

1.544 Mbit/s External synchronization interface

2 Mbit/s/2 MHz External synchronization interface NTCE44AA

Message exchange (MX)

Circuit Pack Descriptions 323-1521-102 Rel 6 Iss 1 Standard Apr 2004

1-4 Circuit pack descriptions

OPTera OC-192 Regen Page

Filler card (transport shelf - tributary or line)

Filler card (double-width switch module slot)

Filler card (single, half-height)

Filler card (Control shelf)

Circuit pack LEDs