VLSI

Email: vlsi@pantechmail.com

[ Xilinx ISE & Spartan FPGA's]

PSVLSI602
PSVLSI603
PSVLSI604
PSVLSI605

PSVLSI606

Multiplier-less pipeline architecture for lifting-based twodimensional discrete wavelet transform

A Low-Power Architecture for the Design of a OneDimensional Median Filter
Fully Reused VLSI Architecture of FM0/Manchester Encoding
Using SOLS Technique for DSRC Applications
Analysis of ternary multiplier using booth encoding
technique
High speed 16-bit digital Vedic multiplier using FPGA
Low-Power VLSI Architectures for DCT/DWT: Precision vs
Approximation for HD Video, Biomedical, and Smart Antenna
Applications

PSVLSI610

A multi rate CPFSK transmitter

Implementation of AES Algorithm on FPGA for Low Area
Consumption
Low Power Multiplier Architectures Using Vedic
Mathematics in 45nm Technology for High Speed Computing
Circuit-level design technique to mitigate impact of process,
voltage and temperature variations in complementary metaloxide semiconductor full adder cells

PSVLSI611

Design & Optimization of FinFET based Schmitt Trigger using

Leakage Reduction Techniques

PSVLSI607
PSVLSI608
PSVLSI609

APPLICATION

TECHNOLOGY
| CORE

Radar
Edge Preserving
Telecommunicati
on
Signal Processing
Signal Processing

Biomedical
RadioTransmitter
NSA Products
Digital
Multipliers
Digital Signal
Processing
Memory cells

PSVLSI614

Implementation of Low Power Flip Flop Design in Nanometer

Regime
Low power Memristor Based 7T SRAM Using MTCMOS
Technique
Reduction of Leakage Power & Noise for DRAM Design
Using Sleep Transistor Technique

Memory circuits

PSVLSI615

Design of Low Leakage Current Average Power CMOS

Current Comparator Using SVL Technique

Analog to Digital
Converter

PSVLSI612
PSVLSI613

PSVLSI616
PSVLSI617

Implementation of High Performance SRAM Cell Using

Transmission Gate
Implementation of Sub threshold Adiabatic Logic for
Ultralow-Power Application

Photovoltaic
system
Router Buffers

Router
Sensor Networks

www.pantechforum.com |www.pantechsolutions.net|www.pantechproed.com
2015 Pantech ProEd Private Limited

2015
XILINX ISE | MODELSIM
REGISTER TRANSFER LOGIC | ARCHITECTURE
DESIGN

PSVLSI601

PROJECT THEME

2015
CADENCE
MEMORY |ANALOG | DIGITAL CIRCUITS

PROJECT
CODE

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VLSI

Email: vlsi@pantechmail.com

[ Xilinx ISE & Spartan FPGA's]

PSVLSI619
PSVLSI620

PSVLSI621
PSVLSI622
PSVLSI623
PSVLSI624
PSVLSI625
PSVLSI626
PSVLSI627
PSVLSI628
PSVLSI629
PSVLSI630
PSVLSI631
PSVLSI632
PSVLSI633
PSVLSI634
PSVLSI635
PSVLSI636

Design of Full Adder circuit using Double Gate MOSFET

Design of Low Power and High Speed Carry Select Adder
Using Brent Kung Adder
Design of a Compact Reversible Carry Look-Ahead Adder
Using Dynamic Programming
Low-power, high-speed dual modulus prescalers based on
branch-merged true single-phase clocked scheme
Energy and Area Efficient Three-Input XOR/XNORs With
Systematic Cell Design Methodology
Power Optimization of Communication System Using Clock
Gating Technique
Low-Power Clock Distribution Using a Current-Pulsed
Clocked Flip-Flop
AN EFFICIENT ALGORITHM FOR BOUNDARY DETECTION
Hardware Implementation of Digital Watermarking System
for Real Time Captured Image Transmitting
Reconfigurable Architecture of Adaptive Median Filter An
FPGA Based Approach for Impulse Noise Suppression

Biomedical
System
Signal Processing
Radar Detection

ALU Design
DSP
ARCHITECTURE
DSP
Photovoltaic
System
Photovoltaic
System
Consumer
Electronics
DSP
ARCHITECTURES
DSP
ARCHITECTURES
Nanotechnology
Frequency
Counters
Avionics
Photovoltaic
Standalone
systems
Computer Vision
Broadcast
Monitoring
Computer Vision

www.pantechforum.com |www.pantechsolutions.net|www.pantechproed.com
2015 Pantech ProEd Private Limited

2015 CMOS
COMBINATIONAL |SEQUENTIAL ARITHMETIC CIRCUITS

PSVLSI618

Dynamic Threshold Source Coupled Logic with Push pull

topology for Ultra Low Power Applications
Aging-Aware Reliable Multiplier Design With Adaptive Hold
Logic
Estimation of Static and Dynamic Characteristics for 4-Bit
Flash ADC
Design of a Low Power 4x4 Multiplier Based on Five
Transistor (5-T) Half Adder, Eight Transistor (8-T) Full Adder
& Two Transistor (2-T) AND Gate
Design and Analysis of ApproximateCompressors for
Multiplication
Design of Area and Power Aware Reduced Complexity
Wallace Tree Multiplier
Single-ended structure sense-amplifier-based flip-flop for
low-power systems
Variations in Nanometer CMOS Flip-Flops: Part IIEnergy
Variability and Impact of Other Sources of Variations
Design and Realization of CMOS Circuits Using Dual
Integrated Technique to Reduce Power Dissipation

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VLSI

Email: vlsi@pantechmail.com

PSVLSI639
PSVLSI640
PSVLSI641
PSVLSI642
PSVLSI643
PSVLSI644
PSVLSI645
PSVLSI646
PSVLSI647

PSVLSI648
PSVLSI649
PSVLSI650
PSVLSI651

Design and Estimation of delay, power and area for Parallel

prefix adders
Design of an Energy Efficient, High Speed, Low Power Full
Subtractor Using GDI Technique
Design of a low Power Arithmetic and logic unit using GDI
Technique
Low-Power Pulse-Triggered Flip-Flop Design Based on a
Signal Feed-Through Scheme
AreaDelayPower Efficient CarrySelect Adder

PSVLSI652
Logical Effort for CMOSBased Dual Mode Logic Gates
PSVLSI653
PSVLSI654
PSVLSI655
PSVLSI656

Design of sequential circuits using single-clocked Energy

efficient adiabatic Logic for ultra-low power application
A New Design of Low Power High Speed Hybrid CMOS Full
Adder
A Fully Static Topologically-Compressed 21-Transistor FlipFlop With 75% Power Saving
An Arithmetic and Logic Unit Optimized for Area and Power

PSVLSI657
PSVLSI658

Analysis and Design of a Low-Voltage Low-Power Double-Tail

Comparator

Computer Vision
Optical Character
Image Tampering
Machine Vision
Defense
Computer Vision
Access Control
Satellite imagery
Remote Sensing
Defense
Computer Vision
Avionics

Avionics
Power
Management
Avionics
Power
Management
Power
Management
Power
Management
Avionics
Power
Management
Power
Management
Avionics

www.pantechforum.com |www.pantechsolutions.net|www.pantechproed.com
2015 Pantech ProEd Private Limited

2014
LOW POWER DESIGN
COMBINATIONAL | SEQUENTIAL |DIGITAL CIRCUITS | TESTING

PSVLSI637
PSVLSI638

Image segmentation framework based on multiple feature

spaces
Leaf Shape Extraction For Plant Classification
Median Filtered Image Quality Enhancement and AntiForensics via Variation DE convolution
Comparisons of Robert, Prewitt, Sobel operator based edge
detection methods for real time uses on FPGA
Reversible Image Data Hiding with Contrast Enhancement
Shape analysis of decisive objects from an image Using
Mathematical Morphology
PCA and DWT Based Multimodal Biometric Recognition
System
Iris Image Compression using Wavelets Transform Coding
Multifocus Image Fusion Based on NSCT and Focused Area
Detection
Semantic image compression based on data hiding
Rapid Heterogeneous Prototyping from Simulink

2015
IMAGE PROCESSING
FEATURE EXTRACTION | BIOMETRIC RECOGNITION

[ Xilinx ISE & Spartan FPGA's]

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VLSI

Email: vlsi@pantechmail.com

[ Xilinx ISE & Spartan FPGA's]

PSVLSI661

Photovoltaic
Avionics
BIST
BIST
Defense

PSVLSI670

Implementation of a video streaming security system for

smart device
Background Subtraction with Dirichlet Process Mixture
Models
Fast hardware architecture for greylevel image morphology
with flat structuring elements
A RealTime MotionFeatureExtraction VLSI Employing
DigitalPixelSensorBased Parallel Architecture
Portable CameraBased Assistive Text and Product Label
Reading From HandHeld Objects for Blind Persons
Runway Extraction in Low Visibility Conditions based on
Fusion method
Multispectral images segmentation based on DWT and
decisions fusion

Encryption

PSVLSI671

An Efficient parallel algorithm for secured data

communication using RSA public key Cryptography
method
Hardware Efficient VLSI Architecture for 3-D Discrete
Wavelet Transform
Segmentation of Blood Vessels and Optic Disc in Retinal
Images
Multiprocessing on FPGA using Light Weight Processor

Signal
Processing

PSVLSI664
PSVLSI665
PSVLSI666
PSVLSI667
PSVLSI668
PSVLSI669

PSVLSI672
PSVLSI673
PSVLSI674
PSVLSI675
PSVLSI676
PSVLSI677

A low power hardware implementation of S-Box for

Advanced Encryption Standard.
An Optimized Modified Booth Recoder for Efficient
Design of the Add-Multiply Operator
Binary division algorithm and high speed DE
convolution algorithm

Computer Vision
Computer Vision
Computer Vision
Machine Vision
Machine Vision
Computer Vision

BioMedical
Machine Vision

Encryption
ALU Design
Processor
design

www.pantechforum.com |www.pantechsolutions.net|www.pantechproed.com
2015 Pantech ProEd Private Limited

2014
MICROBLAZEPROCESSOR DESIGN

PSVLSI663

Built-in-self-test technique for diagnosis of delay faults in

cluster-based field programmable gate arrays

PSVLSI659
PSVLSI660

Photovoltaic

2014
PROCESSOR
ARCHITECTURE

PSVLSI662

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop

Featuring Efficient Embedded Logic
Design Flow for Flip-Flop Grouping in Data-Driven Clock
Reverse Converter Design via ParallelPrefix Adders: Novel
Components, Methodology, and Implementations
A novel approach to realize Built-in-self-test enabled UART
using VHDL

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