RRB Junior Computer Engineer Model Question Paper Solved 2 - 2

File hosted by educationobserver.
com/forum
1)
a.
Who is the brain of computer:

ALU
b.
CPU
d.
None of these
c.
2)
a.
MU
Which technology using the microprocessor is fabricated on a single chip:

POS
b.
MOS
d.
ABM
c.
3)
a.
b.
c.
d.
4)
a.
ALU
MOS stands for:
Metal oxide semiconductor
Memory oxide semiconductor

Metal oxide select
None of these
In which form CPU provide output:
Computer signals
b.
Digital signals
d.
None of these
c.
5)
a.
b.
c.
d.
6)
a.
Metal signals
How many types of microprocessor comprises:
3
6
9
4
Which is the microprocessor comprises:

Register section
b.
One or more ALU
d.
All of these
c.
7)
a.
Control unit
The register section is related to______ of the computer:

Processing
b.
ALU
d.
None of these
c.
8)
a.
b.
Main memory
What is the store by register:

data
operands
File hosted by educationobserver.com/forum
c.
d.
9)
a.
memory
None of these
How many types of classification of processor based on register section:

1
b.
d.
a.
Calculator
c.
10) In Microprocessor one of the operands holds a special register called:

b.
Dedicated
d.
None of these
a.
Intel 8085
c.
Accumulator
11) Accumulator based microprocessor example are:

b.
Motorola 6809
d.
None of these
a.
data
c.
A and B
12) A set of register which contain are:

b.
memory addresses
d.
all of these
a.
c.
result
13) How many types are primarily register:

b.
d.
a.
general purpose register
c.
14) There are primarily two types of register:

b.
dedicated register
d.
none of these
a.
general purpose register
c.
A and B
15) Which register is a temporary storage location:

b.
dedicated register
d.
none of these
a.
c.
A and B
16) How many parts of dedicated register:
b.
d.
a.
PC
c.
17) Name of typical dedicated register is:

b.
IR
d.
All of these
a.
Program counter
c.
Paragraph counter
c.
SP
18) PC stands for:

b.
Points counter
d.
Paint counter
a.
Intel register
19) IR stands for:

b.
In counter register
d.
Instruction register
a.
Status pointer
c.
Index register
20) SP stands for:

b.
Stack pointer
d.
None of these
c.
a and b
21) The act of acquiring an instruction is referred as the____ the instruction:

a.
Fetching
c.
Both a and b
b.
Fetch cycle
d.
None of these
a.
2-bit
22) How many bit of instruction on our simple computer consist of one____:
b.
6-bit
d.
None of these
a.
c.
12-bit
23) How many parts of single address computer instruction :

b.
d.
c.
24) Single address computer instruction has two parts:
a.
The operation code
b.
The operand
d.
None of these
c.
A and B
25) LA stands for:

a.
b.
c.
Load accumulator
Least accumulator
Last accumulator
d.
None of these
a.
Enable MRD
26) ED stands for:

b.
Enable MDR
d.
None of these
a.
Least MAR
c.
Both a and b
27) LM stands for:

b.
Load MAR
d.
Load MRA
a.
Clearing a flag
c.
Both a and b
c.
Least MRA
28) Causing a flag to became 0 is called:

b.
d.
Case a flag
None of these
29) Which are the flags of status register:

a.
Over flow flag
b.
Carry flag
d.
Zero flag
f.
Negative flag
c.
e.
Half carry flag

Interrupt flag
g.
All of these
a.
a.
a.
30) The carry is operand by:

31) The sign is operand by:
32) The zero is operand by:
33) The overflow is operand by:
a.
a.
CD
c.
Both a and b
34) _____ is the condition:

b.
IR
d.
None of these
a.
CRJA
35) ____ causes the address of the next microprocessor to be obtained from the memory:
b.
ROM
d.
HLT
a.
c.
Both a and b
c.
MAP
36) _________ Stores the instruction currently being executed:

b.
Current register
d.
None of these
a.
37) In which register instruction is decoded prepared and ultimately executed:

b.
Current register
d.
None of these
a.
Condition code register
c.
Both a and b
38) The status register is also called the____:

b.
c.
Flag register
A and B
d.
None of these
a.
Binary coded decimal
c.
Both a & b
39) BCD stands for:

b.
Binary coded decoded
d.
none of these
a.
Stack
c.
Accumulator
40) Which is used to store critical pieces of data during subroutines and interrupts:
b.
Queue
d.
Data register
a.
High memory
41) The area of memory with addresses near zero are called:
b.
Mid memory
c.
d.
Memory
Low memory
42) The point where control returns after a subprogram is completed is known as the :
a.
Return address
c.
Program Address
b.
Main Address
d.
Current Address
a.
Queue
43) The subprogram finish the return instruction recovers the return address from the:
b.
Stack
d.
Pointer
c.
Program counter
44) The processor uses the stack to keep track of where the items are stored on it this by using
the:
a.
Stack pointer register
c.
Both a & b
b.
Queue pointer register
d.
None of these
a.
TOP
c.
MID
45) Which point to the ___ of the stack:

b.
START
d.
None of these
a.
LILO
46) Stack words on:

b.
c.
LIFO
FIFO
d.
None of these
a.
PUSH
47) Which is the basic stack operation:

b.
POP
d.
None of these
a.
Stack pointer
c.
Stack push
c.
BOTH A and B
48) SP stand for:

b.
Stack pop
d.
None of these
a.
1 bit
49) How many bit stored by status register:

b.
4 bit
c.
6 bit
d.
8 bit
a.
Index register
50) Which is the important part of a combinational logic block:

b.
Barrel shifter
d.
None of these
c.
Both a & b
51) The structure of the stack is _______ type structure:

a.
First in last out
c.
Both a & b
b.
Last in last out
d.
None of these
a.
Pushing data
52) The data in the stack is called:

b.
Pushed
d.
None of these
a.
HARDWIRED CONTROLS
c.
Pulling
53) The CU is designed by using which techniques:

b.
MICROPROGRAMING
d.
ALL OF THESE
a.
BCD
c.
NANOPROGRAMING
54) The 16 bit register is separated into groups of 4 bit where each groups is called:
b.
Nibble
d.
None of these
a.
Octal digit
c.
Half byte
55) A nibble can be represented in the from of:

b.
Decimal
d.
None of these
a.
Least significant digit
c.
Hexadecimal
56) The left side of any binary number is called:

b.
Most significant digit
d.
low significant digit
c.
Medium significant digit
57) MSD stands for:

a.
Least significant digit
b.
Most significant digit
d.
low significant digit
c.
Medium significant digit
58) _____ a subsystem that transfer data between computer components inside a computer or
between computer:
a.
Chip
b.
Register
d.
Bus
a.
Processor
c.
Processor
59) Which is called superhighway:

b.
Multiplexer
d.
None of these
a.
Pascal
c.
Backbone bus
60) The external system bus architecture is created using from ______ architecture:
b.
Dennis Ritchie
d.
Von Neumann
a.
PCB
c.
Charles Babbage
61) The network of wires or electronic path ways on mother board back side:
b.
c.
BUS
BOTH A and B
d.
None of these
a.
Rear side bus
62) Which Bus connects CPU & level 2 cache:

b.
Front side bus
d.
None of these
a.
System bus
c.
Memory side bus
63) Which bus carry addresses:

b.
Address bus
d.
Data bus
a.
32767
c.
Control bus
64) A 16 bit address bus can generate___ addresses:

b.
25652
c.
65536
d.
none of these
a.
16
65) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
b.
32
d.
64
a.
Control bus
c.
36
66) CPU can read & write data by using :

b.
Data bus
d.
None of these
c.
Address bus
67) Which bus transfer singles from the CPU to external device and others that carry singles
from external device to the CPU:
a.
Control bus
c.
Address bus
b.
Data bus
d.
None of these
a.
READ
68) Which is not the control bus signal:

b.
WRITE
d.
None of these
a.
Input
c.
RESET
69) When memory read or I/O read are active data is to the processor :
b.
c.
Output
Processor
d.
None of these
a.
Input
70) When memory write or I/O read are active data is from the processor:
b.
Output
d.
None of these
a.
28=256
b.
2 =4096
c.
Processor
71) Using 12 binary digits how many unique house addresses would be possible:
c.
d.
12
216=65536
None of these
72) PROM stands for:
a.
Programmable read-only memory
a.
Erasable Programmable read-only memory
a.
Address
73) EPROM stands for:
74) Each memory location has:

b.
Contents
d.
None of these
a.
Processor memory
c.
Both A and B
75) Which is the type of microcomputer memory:

b.
Primary memory
d.
All of these
a.
Program store code
c.
Secondary memory
76) Secondary memory can store____:

b.
Compiler
d.
All of these
a.
Auxiliary
c.
Operating system
77) Secondary memory is also called____:

b.
Backup store
d.
None of these
a.
Mask ROM
c.
Both A and B
78) Customized ROMS are called:

b.
c.
Flash ROM
EPROM
d.
None of these
a.
Dynamic RAM
79) The ram which is created using bipolar transistors is called:

b.
Static RAM
d.
DDR RAM
a.
Dynamic RAM
c.
Permanent RAM
c.
Permanent RAM
80) Which type of RAM needs regular referred:

b.
d.
Static RAM
SD RAM
81) Which RAM is created using MOS transistors:
a.
Dynamic RAM
c.
Permanent RAM
b.
Static RAM
d.
SD RAM
a.
SR-Latch
82) Which latch is mostly used creating memory register:

b.
JK-Latch
d.
T-Latch
a.
WR signal controls the input buffer
c.
D-Latch
83) Which statement is false about WR signal:

b.
The bar over WR means that this is an active low signal
d.
If WR is 0 then the input data reaches the latch input
a.
Linear decoding
c.
The bar over WR means that this is an active high signal
84) Which technique is used for main memory array design:

b.
Fully decoding
d.
None of these
a.
Cable select
c.
Both A and B
85) CS stands for:

b.
c.
Chip select
Control select
d.
Cable system
a.
Write enable
c.
Write envy
86) WE stands for:

b.
d.
Wrote enable
None of these
87) When CS _____ the chip is not selected at all hence D7 to D0 are driven to high impedance
state:
a.
High
c.
Medium
b.
d.
Low
Stand by
88) The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit
word The what is the site of address bus:
a.
b.
8 bit
10 bit
c.
12 bit
d.
16 bit
a.
Linear decoding
c.
Partially
89) Which storage technique dose not decoding circuit:

b.
Fully decoding
d.
None of these
a.
16 KB
90) In linear decoding address bus of 16-bit wide can connect only ____ of RAM.
b.
6KB
d.
64KB
a.
Address map is not contiguous.
c.
12KB
91) Which statement is wrong according to linear decoding :

b.
c.
Confects occur if two of the select lines become active at the same time
If all unused address lines are not used as chip selectors then these unused lines
become dont cares

d.
None of these
92) The problem of bus confect and sparse address distribution are eliminated by the use of
______ address technique:
a.
Fully decoding
c.
Both a & b
b.
Half decoding
d.
None of these
a.
Control memory
93) A microprocessor retries instructions from :

b.
Cache memory
d.
Virtual memory
a.
MAR
c.
Main memory
94) Which register is used to communicate with memory:

b.
MDR
d.
None of these
a.
Simple architecture machine
c.
Both a & b
c.
Both A and B
95) SAM stands for:

b.
d.
Solved architecture machine

None of these
96) MAR stands for:

a.
Memory address register
c.
Micro address register
b.
Memory address recode
d.
None of these
a.
Memory data register
c.
Micro data register
97) MDR stands for:

b.
Memory data recode
d.
None of these
a.
Valid memory address
c.
Variable memory address
98) VAM stands for:

b.
Virtual memory address
d.
None of these
a.
VAM
99) Which microprocessor to read an item from memory:

b.
SAM
d.
None of these
c.
100)
a.
b.
c.
d.
101)
a.
b.
c.
d.
102)
a.
MOC
Which bus plays a crucial role in I/O:
System bus
Control bus
Address bus
Both A and B
Which register is connected to the memory by way of the address bus:
MAR
MDR
SAM
None of these
How many bit of MAR register:

8-bit
b.
16-bit
d.
64-bit
c.
103)
a.
b.
c.
32-bit
MOC stands for:
Memory operation complex
Micro operation complex
Memory operation complete
d.
104)
a.
None of these
Which are the READ operation can in simple steps:

Address
b.
Data
d.
All of these
c.
105)
Control
The upper red arrow show that CPU sends out the control signals____ and _____
indicate the data is read from the memory:

a.
Memory request
b.
Read
d.
None of these
c.
106)
a.
Both A and B
The information is transferred from the_____ and ____ specified register:

MDR
b.
CPU
d.
None of these
c.
107)
a.
Both A and B
The information on the data bus is transferred to the ______register:
MOC
b.
MDR
d.
CPU
c.
108)
VAM
The lower red curvy arrow show that CPU places the address extracted from the
memory location on the_____:

a.
Address bus
c.
Control bus
b.
d.
109)
a.
b.
c.
d.
110)
a.
System bus
Data bus
DMA stands for:
Direct memory access

Direct memory allocation
Data memory access
Data memory allocation
DMA stands for:
Dynamic memory access
b.
Data memory access
d.
Both B and C
c.
111)
CRT stands for:
a.
Cathode ray tube
c.
Command ray tube
b.
d.
112)
a.
Compared ray tube

None of these
The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
Read
b.
Write
d.
None of these
c.
113)
a.
b.
c.
d.
114)
a.
b.
c.
d.
115)
a.
Both A and B
The ____ place the data from a register onto the data bus:
CPU
ALU
Both A and B
None of these
The CPU removes the ___ signal to complete the memory write operation:
Read
Write
Both A and B
None of these
The value memvar must be transferred to the ___:
Computer
b.
CPU
d.
None of these
c.
116)
a.
Both A and B
The microcomputer system by using the ____device interface:
Input
b.
Output
d.
None of these
c.
117)
a.
Both A and B
How bit microprocessor inexpensive a separate interface is provided with I/O device:
2 bit
b.
4 bit
d.
32 bit
c.
118)
device:
a.
b.
c.
8 bit
How many ways of transferring data between the microprocessor and a physical I/O
2
d.
119)
a.
b.
c.
d.
The standard I/O is also called:

Isolated I/O
Parallel I/O
both a and b
none of these
120)
standard I/O uses which control pin on the micro processor:
121)
A___ on this pin indicates a memory operation:
a.
a.
b.
c.
d.
122)
a.
b.
c.
d.
123)
IO/M
Low
High
Medium
None of these
The external device is connected to a pin called the ______ pin on the processor chip.
Interrupt
Transfer
Both
None of these
The DMA controllers are special hardware embedded into the chip in modern integrate
processor that ____and_____ to the system;

a.
b.
c.
d.
124)
a.
b.
c.
d.
125)
a.
Data transfer
arbitrate access
Both A and B
None of these
The CPU completes yields control of the bus to the DMA controller via:
DMA acknowledge signal
DMA integrated signal
DMA implicitly signal
None of these
The mode of DMA are:

Single transfer
b.
Block transfer
d.
Repeated single transfer
f.
Repeated Burst block transfer
c.
e.
g.
1.
Burst block transfer
Repeatedblock transfer
All of these
EOC stands for:
a.
End of conversion
c.
End of controller
b.
2.
d.
None of these
a.
Interrupt request register
c.
Interrupt resolver register
IRR stands for:

b.
3.
Input resolver register
a.
Interrupt service register
b.
c.
a.
Priority register
b.
Priority resolver
d.
None of these
a.
Input mask register
IMR stands for:
Input
Input mask resolver
d.
Interrupt mask register
b.
Interrupt
d.
None of these
a.
Interrupt acknowledge
c.
Interrupt address
INT stands for:
c.
7.
INTA stands for:

b.
8.
Priority request
b.
c.
a.
In-service register
All of these
c.
6.
Input service register
d.
PR stands for:
5.
Input request register
d.
ISR stands for:
4.
Emphasize of conversion
Interrupt mask resolver
Both a and b
Interrupt access
d.
None of these
a.
Command select
CS stands for:
b.
Chip select
d.
Command series
c.
Chip series
9.
RD stands for:
a.
Read
c.
Request
b.
10.
d.
a.
b.
c.
11.
d.
a.
Register
ICW stands for:
Initialization command words
OCW stands for:
a.
DMA stands for:
d.
Direct memory acknowledgment
a.
Direct memory application

HLD stands for:
High
b.
Hour
d.
None of these
a.
Hold
HLDA stands for:
High acknowledgment
b.
Hold acknowledgment
d.
Hold access
a.
High access
HRQ stands for:
b.
d.
a.
b.
c.
Hold request
Hold read
c.
16.
Direct memory allocation

c.
15.
Operational cost words
b.
c.
14.
Operational command words

Operational control words
c.
13.
Initialization command write
Operational conjunction words
c.
12.
Interrupt command words
Interrupt command write
b.
d.
Real
Hold register
AEN stands for:
Hold resolver
Address enable
Address equivalent
Acknowledgment enable
17.
d.
Acknowledgment equivalent
ADSTB stands for:
a.
Access strobe
b.
Access strobe
c.
d.
18.
a.
Address store
Address strobe
MEMER and MEMW means:
Memory read
b.
Memory write
d.
None of these
c.
19.
a.
HRQ and HLDA means:

Hold request
b.
Hold acknowledgment
d.
None of these
a.
Analogue to analogue converters
c.
20.
Both a and b
Both a and b
ADC stands for:

b.
Analogue to digital converters
d.
Digital to analogue converters
a.
Analogue to analogue converters
c.
21.
Digital to digital converters
DAC stands for:

b.
Analogue to digital converters
d.
Digital to analogue converters
c.
22.
Digital to digital converters
Which is the commonly used programmable interface and particular used to
provide handshaking:
a.
8251
b.
8254
d.
8255
a.
8255
c.
23.
8259
b.
8254
d.
8259
a.
8255
c.
24.
Which is a programmable communication interface:
8251
Which programmable timer is used to generate timing signal :
b.
8254
d.
8259
a.
8251
c.
25.
8251
b.
8254
d.
8259
a.
8237
c.
26.
Which is widely used in interrupt controller with a number of microprocessor:
8255
Which are used DMA controllers with 8085/8086 microprocessor:
b.
8257
d.
None of these
c.
27.
Both a and b
and i/o device:

a.
Which provide a mechanism to establish a link between the microprocessor
Input interface
b.
Output interface
d.
None of these
c.
28.
I/O ports:
Both a and b
In which the processor uses a protection of the memory address to represent
a.
Memory mapped I/O
c.
Both a and b
b.
I/O memory mapped
d.
None of these
a.
I/O mapped I/O
29.
The standard I /O is also called:
b.
Isolated I/O
d.
None of these
c.
30.
Both a and b
The processor of knowing the status of device and transferring the data with
matching speeds is called:

a.
Handshaking
c.
Ports
b.
Peripheral
d.
None of these
a.
8251
31.
b.
8254
Which is designed to automatically manage the handshake operation:
c.
8255
d.
8259
a.
Mode 0
32.
Which mode is used for single handshake in 8255:
b.
Mode 1
d.
None of these
a.
Mode 0
c.
33.
Mode 2
Which mode is used for double handshake in 8255:
b.
Mode 1
d.
None of these
a.
Mode 0
c.
Mode 2
c.
34.
b.
Mode 2
Which mode is used for simple input or output without handshaking:
Mode 1
d.
None of these
a.
PC0-PC2
35.
b.
c.
Which are used for port B in 8255:

PC3-PC7
PC6-PC7
d.
PC3-PC5
a.
PC0-PC2
36.
Which are used for port A in 8255 mode 1:
b.
PC3-PC7
d.
PC3-PC5
a.
PC0-PC2
c.
37.
PC6-PC7
Which are used for handshake lines for port A in 8255 mode 2:
b.
PC3-PC7
d.
PC3-PC5
a.
Input
c.
Both a & b
c.
38.
b.
PC6-PC7
AL&99H which operation is performed here:
Output
d.
None of these
a.
Input
39.
34H&AX which operation is performed here:
b.
Output
d.
None of these
a.
8251
c.
40.
Progress
b.
8255
d.
8259
c.
41.
Which chip used for AD&DA converters in 8086 processor:
8254
The time taken by the ADC from the active edge of SOC pulse till the active
edge of EOC signal is called:

a.
Conversion over
b.
Conversion delay
d.
None of these
c.
42.
Conversion signal
Arrange the flowing step of the general algorithm for ADC interfacing:
i.
ii.
iii.
digital output.
the ADC.
a.
iv.
4,1,2,3
d.
4,3,2,1
a.
0809
43.
d.
None of these
a.
2:4
Both a & b
Which multiplexer by ADC 0808/0809:
b.
3:8
d.
None of these
a.
AD7521
c.
45.
b.
c.
Ensuring the stability of analogue input applied to
Which chip is used for analogue to digital converter:

0808
44.
Read digital data output of the ADC as equivalent
1,2,3,4
b.
c.
Marking the end of the conversion processes by the.
2,1,3,4
b.
c.
Issuing start of conversion pulse to ADC.
4:16
Which chip is used for DAC:
AD7522
AD7523
d.
46.
AD7524
Which converters convert binary number into their equivalent voltages:

a.
b.
Analogue to digital
d.
Digital to analogue
c.
47.
a.
Gain
c.
Loss
b.
d.
48.
Analogue to analogue
Digital to digital
An external feedback resistor acts to control the:
Gate
Profit
Which used to generate accurate time delays and can be used for other timing
application such as a real time clock an event counter a digital one shot a square wave generator
and a complex wave form generator:
a.
8251 programmable timer
b.
d.
a.
CLK
b.
Gate
d.
None of these
a.
1output signal
c.
3output signal
c.
49.
c.
50.
b.

8254 programmable timer counter has two inputs signals:
Both a & b
8254 programmable timer counter has:
2output signal
d.
4output signal
a.
51.
8254 can operate how many operating modes:
b.
d.
a.
Enable counting
c.
52.
6
8254 gate of a counter is to either:
b.
Disable counting
d.
None of these
c.
53.
Both
8254 counters can count in the:
a.
Binary
b.
Decimal
d.
A&B
a.
c.
Hexadecimal
54.
b.
d.
a.
Low
c.
How many modes in 8254:
55.
Which is the state of gate signal for normal contains:
b.
High
d.
None of these
c.
Undefined
56.
Which generate an interrupt to the microprocessor after a certain interval of
time:
a.
8251
b.
8254
c.
d.
8255
8259
1.
A central processing unit, fabricated on a single chip of semiconductor is called:
a.
Microprocessor
c.
ROM
b.
RAM
d.
None of these
2.
Which is the architecture of microprocessor:
a.
CISC
b.
RISC
d.
None of these
3.
CISC stands for:
b.
Complex Instruction Set Car
c.
a.
All of these
Complex Instruction System Computer
c.
Complex Instruction Set Computer
d.
None of these
a.
Reduced Instruction Set Computer
c.
Resource Instruction Set Computer
4.
b.
RISC stands for:
Reduced Intergraded Set Computer
d.
Resource Instruction System Computer
a.
System Bus
5.
Which is the components of computer:
b.
CPU
d.
All of these
6.
System Bus Contains:
a.
Address Bus
c.
Memory Unit
b.
Data Bus
d.
All of these
7.
Microprocessor is the _____ of computer:
a.
Hand
c.
Control Bus
b.
Heart
d.
Leg
8.
Microprocessor is fabricated on single chip using:
a.
MOS
c.
CPU
c.
b.
Brain
ALU
d.
All of these
9.
Which is the components of microprocessor:
a.
Register unit
b.
Arithmetic and logical unit
c.
d.
Timing and control unit
All of these
10. Which is an integral part of any microcomputer system and its primary purpose is to hold
program and data:
a.
Memory unit
c.
A and B
b.
d.
Register unit
None of these
11. How many group of memory unit:

a.
Four
b.
Three
d.
One
c.
Two
12. Which is the parts of memory unit:

a.
Processor memory
b.
Main memory
d.
All of these
c.
Secondary memory
13. MOS stand for:

a.
Metal oxide semiconductor
c.
A and B
b.
d.
Memory oxide semiconductor

None of these
14. Which system communicates with the outside word via the I/O devices interfaced to it:
a.
Microprocessor
b.
Microcomputer
d.
All of these
c.
Digital computer
15. A computer which has the microprocessor as______ is called as a microcomputer:

a.
CPU
c.
RU
b.
d.
ALU
None of these
16. The organization of I/O devices create a difference between _____:

a.
Digital computer
b.
Micro computer
d.
None of these
c.
A and B
17. How many generation of microprocessor:

a.
Four
b.
Five
d.
Three
c.
Six
18. The___ was very successful in the calculator market at that time:
a.
Motorola 6800 and 6809
b.
Microprocessor 4004
d.
None of these
c.
Intel 8085
19. How are the successful microprocessor:

a.
8004
b.
5006
d.
All of these
c.
4004
20. How many microprocessor in the market during the same period:
a.
b.
d.
c.
21. PMOS stands for:

a.
P-channel metal-oxide-semiconductor
c.
Both A and B
b.
P-channel memory oxide-semiconductor
d.
None of these
a.
Low-cost
22. Which provided the current:
b.
Slow-cost
d.
All the above
c.
Low-Output
23. Second Generation_____?

a.
1974-1976
b.
1974-1978
d.
None of these
c.
1974-1972
24. The beginning of very efficient____ microprocessor in second generation:

a.
4-bit
b.
8-bit
d.
64-bit
c.
16-bit
25. Which are some of popular processor:

a.
Motorola 6800 and 6809
b.
Intel 8085
d.
All the above
c.
Zilog Z80
26. NMOS stands for:

a.
N-channel metal-oxide-semiconductor
b.
P-channel metal-oxide-semiconductor
d.
All the above
a.
CRT
c.
N-channel memory-oxide-semiconductor
27. _____ Was more common year:
b.
TTL
d.
None of these
c.
Both A and B
28. Which technology speed faster and higher density:

a.
PMOS
c.
HMOS
b.
d.
NMOS
All the above
29. What is the period of 3 generation:

a.
1979-1981
b.
1979-1980
d.
1978-1980
c.
1978-1979
30. Third generation microprocessor is dominated by____ microprocessor:

a.
8 bit
b.
4 bit
d.
64 bit
c.
16 bit
31. Intel used HMOS technology to recreate_____:

a.
8084 A
b.
8086 A
d.
8088 A
c.
8085 A
32. HMOS stands for:
a.
High performance metal oxide semiconductor
c.
Both A and b
b.
High processor metal oxide semiconductor
d.
None of these
a.
1979-1980
33. What is the period of fourth generation:
b.
1981-1995
d.
1974-1980
c.
1995-2000
34. The fourth generation of microprocessor came really as a soon boon to the_____:
a.
Computing environment
c.
Hot environment
b.
d.
Processing environment
All of these
35. How many bit microprocessor in the era marked beginning of fourth generation:
a.
4 bit
b.
8 bit
d.
32 bit
c.
16 bit
36. They were fabricated using a low power version of the HMOS technology called____:
a.
HSMOS
b.
HCMOS
d.
None of these
c.
HSSOM
37. Motorola introduced _____ processor:

a.
2 bit-RISC
b.
4 bit-RISC
d.
32 bit-RISC
c.
8 bit-RISC
38. Motorola introduced 32 bit RISC processor called______:

a.
MC 88100
c.
MC 80100
b.
d.
MC 81100
MC 81000
39. Period of fifth generation?

a.
1974-1978
b.
1979-1980
d.
1995-till date
c.
1981-1985
40. The growth of vacuum tube technology has been listed as follow:
a.
1946-1957
c.
1985-1999
b.
d.
1958-1964
None of these
41. The growth of transistor technology in_____:

a.
1946-1957
b.
1958-1964
d.
None of these
c.
1985-1999
42. How are the growth of SSI technology in_____:

a.
1956 on words
b.
1965 on words
d.
1978 on words
c.
1978 on words
43. The growth of medium scale integration in______:

a.
b.
Till 1971
Till 1970
c.
d.
Till 1972
Till 1969
44. The growth of SSI up to____:

a.
100 device on a chip
c.
b.
d.
45. The growth of LSI technology on_____:

a.
1994-1995
b.
1971-1977
d.
None of these
c.
1972-1978
46. Which is most commonly measured in terms of MIPS previously million instruction per
second:
a.
Microprocessor
b.
Performance of a microprocessor
d.
None of these
c.
Assembly line
47. The range of this rating for which microprocessor of_____:

a.
VLSI
b.
Motorola
d.
Zilog
c.
Intel
48. How can we make computers work faster?

a.
The fetch-execute cycle and pipelining
c.
Both A and B
b.
d.
The assembly
None of these
49. Who is the represents the fundamental process in the operation of the CPU:
a.
The fetch-execute cycle and pipelining
c.
Both A and B
b.
d.
The assembly
None of these
50. Which process information at a much faster rate than it can retrieve it from memory:
a.
ALU
b.
Processor
d.
CPU
c.
Microprocessor
51. _____ memory system which is discussed later can improve matters in this respect:
a.
Data memory
b.
Cache memory
d.
None of these
c.
Memory
52. The fetch-execute cycle is to use a system know as:

a.
Assembly line
b.
Pipelining
d.
None of these
c.
Cache
53. The time taken for all stages of the assembly line to become active is called the:
a.
Flow through time
c.
Throughput
b.
d.
Clock period
All of these
54. The clock period is denoted by:

a.
Tp
b.
T1+T2+T3-------+T n
c.
Pt
d.
None of these
55. Ti is the time taken for the ith stage and there are n stages in the:
a.
Throughput
b.
Assembly line
d.
None of these
c.
Both A and B
56. Who is the determined by the time taken by the stages the requires the most processing time:
a.
Clock period
c.
Throughput
b.
d.
Flow through
None of these
57. The ____ of can assembly line to be I/t p:

a.
Clock period
b.
Pipelining
d.
Flow through
c.
Throughput
58. Which is the microprocessor launched by Motorola corporation introduced:

a.
Mc6800
c.
IMP-8
b.
d.
8080
RPS-8
59. How many bit MC6800 microprocessor:

a.
4-bit
b.
8-bit
d.
32-bit
c.
16-bit
60. Motorola has declined from having nearly __________ share of the microprocessor market to
much smaller share:

a.
30%
b.
40%
d.
60%
c.
50%
61. Which is the microprocessor launch by Fairchild company:

a.
F-6
b.
F-8
d.
None of these
c.
Both A and B
62. How many stages has fetch execute cycle:

a.
b.
d.
c.
63. Which is the worlds first microprocessor?

a.
Intel 4004
b.
Motorola 68020
d.
None of these
c.
Intel8008
64. MOSFET stands for?

a.
Metal-oxide-semiconductor field effect transistor
c.
Both A and B
b.
Metal-oxide-semiconductor fan effort transistor
d.
None of these
a.
Speed
65. What is the main problem of Intel 4004 microprocessor:
b.
Memory size
c.
d.
World width
All of these
66. The evolution of the 4 bit microprocessor ended when Intel released in:
a.
4004
b.
8008
d.
4040
c.
40964
67. How many bit microprocessor still survives in low-end application such as microwave ovens
and small control system:
a.
4 bit
c.
32 bit
b.
d.
16 bit
64 bit
68. Calculator are based on______ microprocessor:

a.
4 bit
c.
32 bit
b.
d.
16 bit
64 bit
69. BCD stands for:

a.
Binary coded decimal
c.
Both A and B
b.
d.
Based coded decimal

None of these
70. Intel 8008 microprocessor realizing in:

a.
1971
c.
1999
b.
d.
1973
1988
71. Intel 8008 microprocessors upgraded version is:

a.
8080
c.
Both A and B
b.
d.
4004
None of these
72. Intel 8008 microprocessor was introduced in:

a.
1971
b.
1973
d.
1988
c.
1999
73. MC6800 microprocessor was introduced by:

a.
Motorola corporation
c.
Both A and B
b.
d.
Fairchild
None of these
74. Which Microprocessor producer continue successfully to create newer and improved version
of the microprocessor:
a.
Intel
b.
Motorola
d.
None of these
c.
Both A and B
75. Motorola has declined how many % share of the microprocessor market to a much smaller
share:
a.
50%
c.
48%
b.
d.
55%
51%
76. Which year Intel corporation introduced an updated version of the 8080- the 8085:
a.
1965
b.
1976
d.
1985
c.
1977
77. In 1977 which corporation introduced an updated version of the 8080- the 8085:
a.
Motorola
b.
Intel
d.
National
c.
Rockwell
78. How many bit microprocessor developed by Intel:

a.
4 bit
b.
8 bit
d.
64 bit
c.
32 bit
79. Which is the main feature of 8085:

a.
Internal clock generator
b.
Internal system controller
d.
All of these
c.
Higher clock frequency
80. Which is 16 Bit microprocessor:

a.
8088
b.
8086
d.
All of these
c.
8085
81. How many speed of 8088,8085,8086 microprocessor:

a.
2.5 Million instruction per second
c.
b.
d.
82. Which year Intel family ensured:

a.
1965
b.
1978
d.
1999
c.
1981
83. Which corporation decided to use 8088 microprocessor in personal computer:

a.
IBM
c.
PMN
b.
d.
CRT
SPS
84. Which processor provided 1 MB memory:

a.
16-bit 8086 and 8088
c.
64-bit 8086 and 8088
b.
d.
32-bit 8086 and 8088

8-bit 8086 and 8088
85. Who was introduce the 80286 microprocessor updated on 8086,in 1983:
a.
Intel
c.
Fairchild
b.
d.
Motorola
None of these
86. Which is the microprocessor launched by Intel:

a.
Z-8
b.
8080
d.
None of these
c.
8000
87. Which is the microprocessor launched by national semiconductor:

a.
b.
IMP-4
IMP-8
c.
d.
IMP-6
IMP-7
88. Which is the microprocessor launched by Rockwell international:

a.
RPS-4
b.
RPS-6
d.
All of these
c.
RPS-8
89. Which is the microprocessor launched by Zilog:

a.
Z-2
b.
Z-4
d.
Z-8
c.
Z-6
90. CAD stands for:

a.
Computer aided drafting
c.
Both A and B
b.
d.
Compare aided drafting

None of these
91. GUI stands for:

a.
Graphical user interface
c.
Graphical use inter
b.
d.
Graph used Intel

None of these
92. VGA stands for:

a.
Visual graph area
b.
Visual graphics array
d.
All of these
c.
Visual graph accept
93. Pentium Pro Processor contains:
a.
L1 Cache
b.
L2 Cache
d.
None of these
c.
Both L1 & L2
94. L1 cache memory is places at ______

a.
On Processor
c.
On Memory
b.
d.
On Mother Board
All of these
95. L2 cache memory is places at ______

a.
On Processor
b.
On Mother Board
d.
All of these
c.
On Memory
96. Pentium Pro can address _____ of memory:

a.
4 GB
c.
256 GB
b.
d.
128 GB
512 GB
97. Which is the professional or Business version of Intel Processors:

a.
Pentium II
b.
Pentium Pro
d.
Pentium Xeon
c.
Pentium MMX
98. Pentium III processor is released in the form of:

a.
b.
c.
Socket 370 Version
Slot 1 Version in Plastic Cartridge

Both a and b
d.
None of these
a.
1.0 GHz
99. What is the maximum clock speed of P III processors
b.
1.1 GHz
d.
1.3 GHz
c.
1.2 GHz
100.
a.
Power PC microprocessor architecture is developed by:

Apple
b.
IBM
d.
All of these
c.
101.
Motorola
Which is not the main architectural feature of Power PC:
a.
It is not based on RISC
c.
Both 32 & 64 Bit
b.
Superscalar implementation
d.
Paged Memory management architecture
a.
DEC
c.
Motorola
102.
b.
d.
103.
a.
Alpha AXP is developed by:
IBM
Intel
Which is not the main feature of DEC Alpha:
64 Bit RISC processor
b.
Designed to replace 32 VAX(CISC)
d.
Variable Instruction length
a.
Debian
c.
104.
Seven stage split integer/floating point pipeline

Which is not the open-source OS:
b.
BSD Unix
d.
Windows
c.
Gentoo & Red Hat Linux
105.
a.
ISA stands for:

Instruct set area
b.
Instruction set architecture
d.
None of these
c.
106.
Both a and b
RISC stands for:
a.
Reduced Instruction set computer
c.
Reduced instruction stands computer
b.
Reduced Instruct set compare
d.
All of these
a.
Digital electronic computer
b.
Digital electronic corporation
d.
None of these
107.
c.
DEC stands for:
Digital equipment corporation
108.
How many architectural paradigms in microprocessor:
a.
c.
b.
d.
3
6
109.
a.
Which are the architectural paradigms in microprocessor:

RISC
b.
CISC
d.
A and B
c.
110.
PISC
CISC stands for:
a.
Complex instruction set computer
c.
Compared instruction set computer
b.
Camper instruct set of computer
d.
None of these
a.
CPU
c.
MU
111.
b.
PCs use____ based on this architecture:
ALU
d.
None of these
1.
BIU STAND FOR:

a.
Bus interface unit
c.
A and B
b.
2.
d.
None of these
a.
Execution unit
c.
Exchange unit
EU STAND FOR:
b.
3.
None of these
a.
The register can be divided are:

b.
d.
a.
The bus interface unit
b.
The execution unit
d.
None of these
a.
General- purpose register
Both A and B
Which are the four categories of registers:

b.
Pointer or index registers
d.
Other register
c.
6.
Which are the part of architecture of 8086:
c.
5.
Execute unit
d.
c.
4.
Bess interface unit
Segment registers
e.
All of these
a.
General- purpose register
c.
Segment registers
Eight of the register are known as:

b.
d.
Pointer or index registers

Other register
7.
The four index register can be used for:

a.
Arithmetic operation
c.
Subtraction operation
b.
8.
d.
All of these
a.
Instruction pointer
c.
Instruction paints
IP Stand for:
b.
9.
Multipulation operation
Instruction purpose
d.
None of these
a.
Code segment
c.
Cost segment
CS Stand for:
b.
Coot segment
d.
Counter segment
a.
Data segment
c.
Declare segment
10. DS Stand for:

b.
Direct segment
d.
Divide segment
a.
CS: Code segment
11. Which are the segment:

b.
DS: data segment
d.
ES:extra segment
c.
SS: Stack segment
e.
All of these
a.
AX
c.
AL
12. The acculatator is 16 bit wide and is called:

b.
AH
d.
DL
a.
BH
13. The upper 8 bit are called______:

b.
BL
d.
CH
a.
AL
c.
AH
14. The lower 8 bit are called_______:

b.
CL
c.
BL
d.
DL
a.
Industry pointer
15. IP stand for:

b.
Instruction pointer
d.
None of these
a.
Stack segment
c.
Array segment
c.
Index pointer
16. Which has great important in modular programming:

b.
Queue segment
d.
All of these
a.
Status register
c.
Flag register
17. Which register containing the 8086/8088 flag:

b.
Stack register
d.
Stand register
a.
The stack
18. Which flag are used to record specific characteristics of arithmetic and logical instructions:
b.
The stand
d.
The queue
a.
16 bit
c.
64 bit
c.
The status
19. How many bits the instruction pointer is wide:

b.
32 bit
d.
128 bit
a.
Logical address
20. How many type of addressing in memory:

b.
Physical address
d.
None of these
a.
64 kb
c.
50 kb
c.
Both A and B
21. The size of each segment in 8086 is:

b.
24 kb
d.
16kb
a.
20 bit
22. The physical address of memory is :
b.
16 bit
d.
64 bit
a.
Physical
c.
Both
c.
32 bit
23. The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
b.
d.
Logical
None of these
24. To provide clarity in case of the status register_______ and __________ placeholders are
displayed:
a.
Binary
b.
Hexadecimal
d.
None of these
a.
40 pin
c.
30 pin
c.
Both
25. The pin configuration of 8086 is available in the________:

b.
50 pin
d.
20 pin
a.
Deal inline package
26. DIP stand for:

b.
Dual inline package
d.
Digital inline package
a.
Project address
c.
Direct inline package
27. PA stand for:

b.
Physical address
d.
Pointer address
a.
Segment bus address
c.
Pin address
28. SBA stand for:

b.
Segment bit address
d.
Segment byte address
a.
Effective address
c.
Effect address
c.
Segment base address
29. EA stand for:

b.
d.
Electrical address
None of these
30. BP stand for:

a.
Bit pointer
b.
Base pointer
d.
Byte pointer
a.
Destination index
c.
Definition index
c.
Bus pointer
31. DI stand for:

b.
Defect index
d.
Delete index
a.
Stand index
32. SI stand for:

b.
Source index
d.
Simple index
a.
Default segment
c.
Delete segment
c.
Segment index
33. DS stand for:

b.
Defect segment
d.
Definition segment
a.
Address latch enable
c.
Address lower enable
34. ALE stand for:

b.
Address light enable
d.
Address last enable
a.
Address data
c.
Address date
35. AD stand for:

b.
Address delete
d.
Address deal
a.
Non mask able interrupt
c.
Both
36. NMI stand for:

b.
Non mistake interrupt
d.
None of these
a.
program counter
c.
protect counter
37. PC stand for:

b.
project counter
d.
planning counter
a.
Accumulator high
c.
Appropriate high
38. AH stand for:

b.
Address high
d.
Application high
a.
Accumulator low
c.
Appropriate low
39. AL stand for:

b.
Address low
d.
Application low
a.
Conditional flag
40. Which are the categorized of flag:

b.
Control flag
d.
None of these
a.
AX: Accumulator
c.
Both a and b
41. Which are the general register:

b.
BX: Base
d.
DX: Data
c.
e.
CX: Count
All of these
42. ________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
a.
Data segment
b.
Code segment
d.
Extra segment
a.
000H to FFFH
c.
Stack segment
43. The offset of a particular segment varies from _________:

b.
0000H to FFFFH
d.
00000H to FFFFFH
a.
Architecture of the microprocessor
c.
00H to FFH
44. Which are the factor of cache memory:

b.
Properties of the programs being executed
d.
All of these
c.
Size organization of the cache
45. ________ is usually the first level of memory access by the microprocessor:
a.
Cache memory
c.
Main memory
b.
d.
Data memory
All of these
46. which is the small amount of high- speed memory used to work directly with the
microprocessor:
a.
Cache
c.
Cost
b.
d.
Case
Coos
47. The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
a.
Main memory
c.
Cache memory
b.
d.
Case memory
All of these
48. The amount of information which can be placed at one time in the cache memory is
called_________:
a.
Circle size
b.
Line size
d.
None of these
a.
c.
Wide line size
49. How many type of cache memory:

b.
d.
a.
Fully associative cache
c.
50. Which is the type of cache memory:

b.
Direct-mapped cache
d.
All of these
a.
Associative memory
c.
Ordinary memory
c.
Set-associative cache
51. Which memory is used to holds the address of the data stored in the cache :
b.
Case memory
d.
None of these
a.
Cheaper way
52. Direct mapping is a _________ to implement cache memory :
b.
Case way
d.
None of these
a.
Direct bit
c.
Cache way
53. A fourth bit called the _________:

b.
Cache bit
d.
All of these
a.
First in first other
c.
Valid bit
54. FIFO stand for:

b.
First in first out
d.
None of these
a.
Cache hits
c.
Cache memory
c.
First in first over
55. Microprocessor reference that are available in the cache are called______:
b.
Cache line
d.
All of these
a.
Cache hits
56. Microprocessor reference that are not available in the cache are called_________:
b.
Cache line
d.
Cache memory
a.
L211 controller
c.
Cache misses
57. __________ is the most commonly used cache controller with a number of processor sets:
b.
L210 controller
d.
None of these
a.
Line full buffers
c.
L214 controller
58. LFB stand for:

b.
Line fill buffers
d.
None of these
a.
Line read buffers
c.
Line root buffers
c.
Line fan buffers
59. LRB stand for:

b.
d.
Line ready buffers

Line right buffers
60. EB stand for:
a.
Effect buffers
b.
Effecting buffers
d.
None of these
a.
Effect buffers
c.
Effection buffers
61. EB stand for:

b.
Effecting buffers
d.
Eviction buffers
a.
Write buffers
c.
Wrote buffers
c.
Effection buffers
62. WB stand for:

b.
Written buffers
d.
None of these
a.
Write allocate
c.
Way allocate
63. WA stand for:

b.
d.
Wrote allocate
Word allocate
64. In case of direct- mapped cache lower order line address bits are used the access the
___________:
a.
RAM
c.
Directory
b.
ROM
d.
HDD
a.
tags
c.
point
65. The index high order bits in the address known as_________:
b.
d.
e.
label
location
66. The parity bits are used to check that a__________:

a.
Two bit error
b.
Single bit error
d.
None of these
a.
Register
c.
Multi bit error
67. Who works as cache on the variable:

b.
Memory
c.
Pointer
d.
Segment
a.
Main memory
68. Second level is a cache on the ________:

b.
RAM
d.
None of these
c.
Both
69. The memory system is said to be effective if the access time of the cache is close to the
effective access time of the_____:
a.
ROM
b.
RAM
d.
Processor
a.
First level
c.
Third level
c.
HDD
70. Cache is usually the____________ of memory access by the microprocessor:

b.
Second level
d.
Fourth level
a.
Spatial locality
71. The principal of working of the cache memory largely depends on which locality:
b.
Temporal locality
d.
All of these
a.
TLB
c.
LEB
c.
Sequentially
72. Who work as a cache for the page table:

b.
TLP
d.
WAB
a.
Reads* Read miss rate * Read miss penalty
73. Which formula is used to calculate the number of read stall cycles:
b.
c.
Write* (Write miss rate * Write miss penalty)+write buffer stalls

Memory access * Cache miss rate * Cache miss penalty
d.
None of these
a.
74. Which formula is used to calculate the number of write stall cycles:
b.
d.
None of these
c.
75. Which formula is used to calculate the number of memory stall cycles:
a.
b.
d.
None of these
a.
RESET signal
c.
Both
c.
76. Which causes the microprocessor to immediately terminate its present activity:
b.
INTERUPT signal
d.
None of these
a.
64-bit AHB-Lite slave ports
77. Which are the cache controller ports:

b.
64-bit AHB-Lite master ports
d.
None of these
a.
16KB-2MB
c.
18 KB-2MB
c.
Both
78. Cache can be controlled __________:

b.
17 KB-2MB
d.
19 KB-2MB
a.
BIU
c.
TIU
79. Which is responsible for all the outside world communication by the microprocessor:
b.
d.
e.
PIU
LIU
80. INTR: it implies the__________ signal:

a.
INTRRUPT REQUEST
c.
INTRRUPT RONGH
b.
d.
INTRRUPT RIGHT
INTRRUPT RESET

RRB Junior Computer Engineer Model Question Paper Solved 2 - 2

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

RRB Junior Computer Engineer Model Question Paper Solved 2 - 2

Diunggah oleh

Hak Cipta:

Format Tersedia

File hosted by educationobserver.

Who is the brain of computer:

Which technology using the microprocessor is fabricated on a single chip:

MOS stands for:

Metal oxide semiconductor

Memory oxide semiconductor

Which is the microprocessor comprises:

One or more ALU

The register section is related to______ of the computer:

What is the store by register:

File hosted by educationobserver.com/forum

How many types of classification of processor based on register section:

10) In Microprocessor one of the operands holds a special register called:

11) Accumulator based microprocessor example are:

12) A set of register which contain are:

13) How many types are primarily register:

general purpose register

14) There are primarily two types of register:

general purpose register

15) Which register is a temporary storage location:

16) How many parts of dedicated register:

File hosted by educationobserver.com/forum

17) Name of typical dedicated register is:

18) PC stands for:

19) IR stands for:

20) SP stands for:

21) The act of acquiring an instruction is referred as the____ the instruction:

23) How many parts of single address computer instruction :

24) Single address computer instruction has two parts:

File hosted by educationobserver.com/forum

The operation code

25) LA stands for:

26) ED stands for:

27) LM stands for:

28) Causing a flag to became 0 is called:

29) Which are the flags of status register:

Over flow flag

Half carry flag

30) The carry is operand by:

File hosted by educationobserver.com/forum

34) _____ is the condition:

36) _________ Stores the instruction currently being executed:

37) In which register instruction is decoded prepared and ultimately executed:

Condition code register

38) The status register is also called the____:

Binary coded decimal

39) BCD stands for:

Binary coded decoded

File hosted by educationobserver.com/forum

File hosted by educationobserver.com/forum

Stack pointer register

Queue pointer register

45) Which point to the ___ of the stack:

46) Stack words on:

47) Which is the basic stack operation:

48) SP stand for:

49) How many bit stored by status register:

File hosted by educationobserver.com/forum

50) Which is the important part of a combinational logic block:

51) The structure of the stack is _______ type structure:

First in last out

Last in last out

52) The data in the stack is called: