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BASIC STRUCTURE OF COMPUTER

HARDWARE AND SOFTWARE


INTRODUCTION

A digital computer is a fast electronic calculating


machine that accepts digitized input information,
processes it according to a list of internally stored
instructions, and produces the resulting output
information.

The list of instructions is called a computer program,


and the internal storage is called computer memory.

Types of Computers
1.

Personal Computers. This is the most common


computer which has found wide use in homes,
schools, and business offices.

2.

Workstations.
Although still of desktop
dimensions, these machines have a computational
power which is significantly higher than that of
personal computers. Workstations are often used
in engineering applications, especially for
interactive design work (CAD/CAM).

3.

Mainframes. A large and powerful computer


used for business data processing in medium to
large corporations that require much more
computing
and
storage
capacity
than
workstations can handle.

4.

Supercomputers. These are used for large-scale


numerical calculations found in applications such
as weather forecasting and aircraft design and
simulation. In mainframes and supercomputers,
the main functional units may comprise a number
of separate and often large parts.

In its simplest form, a computer consists of five


functionally independent main parts: input, memory,
arithmetic and logic, output, and control units.

Arithmetic
and
Logic

Input

Memory
Output

Control

I/O

Basic Structure of Computer Hardware and Software

Processor

BASIC FUNCTIONAL UNITS OF A COMPUTER

The Input Unit accepts coded information from


human operators or from other computers.
Examples:
keyboard, joystick, mouse,
scanner, bar code readers

trackball,

Memory Unit
1.

Primary Storage or Main Memory. This is


where programs are stored during their execution.
The MM is a fast memory capable of operating at
electronic speeds.

The information in MM is often processed in


groups of fixed size called words. The number of
bits in a word is the word length of the computer.
Typical word lengths range from 16 to 64 bits.
The MM is organized so that the contents of one
word, containing n bits, can be stored or retrieved
in one basic operation.

Since programs must reside in MM during


execution, MM is often referred to as the
bottleneck in most computer operations.

Basic Structure of Computer Hardware and Software

To provide easy access to any word in MM, a


distinct address is associated with each word
location. Addresses are numbers that identify
successive locations.
Memory
Location

Address of 1st
Memory Location

1
2

.
.
.

4,194,302
4,194,303

MM is also known as random-access memory


(RAM). RAM is memory in which any location
can be reached in a short, fixed amount of time.
The time required to access one word is the
memory access time. For RAMs, this time is
fixed, independent of the location of the word
being accesses. It typically ranges from 10 to
100 nanoseconds for most modern computers.

Basic Structure of Computer Hardware and Software

2.

Secondary Storage. This is used when large


amounts of data have to be stored, particularly if
some of the data need not be accessed very
frequently.
Examples:

magnetic disks, drums, tapes

Arithmetic and Logic Unit (ALU). This is where the


execution of most operations takes place. It contains a
number of high-speed storage elements called
registers.
used for temporary storage of frequently
used operands.
Each register can store one word of data.
access times are 5 to 10 times faster than
memory access times.

Control Unit (CU). This is the nerve center of a


computer. It sends control signals to other units and
senses their state.
The ALU together with CU is the Central Processing
Unit (CPU) of a computer.

Basic Structure of Computer Hardware and Software

The control and arithmetic and logic units are usually


many times faster than other devices connected to a
computer system. This enables a single processor to
control a number of external devices such as video
terminals, magnetic tape and disk memories, sensors,
displays, and mechanical controllers. This is possible
because the vast difference in speed enables the fast
processor to organize and control the activity of many
slower devices

Output Unit. It sends processed results to the outside


world.
Examples:

CRT/monitor, printers, plotters,


modems

The operation of a computer can be summarized as


follows:
1.

2.

3.
4.

The computer accepts information in the form of


programs and data through an input unit and
stores it in memory.
Information stored in the memory is fetched,
under program control, into an arithmetic and
logic unit, where it is processed.
Processed information leaves the computer
through an output unit.
All activities inside the machine are directed by
the control unit.

Basic Structure of Computer Hardware and Software

BASIC CONCEPTS OF COMPUTER ARCHITECTURE

Computer Architecture is the design of computers,


including their instruction sets, hardware components,
and system organization.

Most computers
Architecture.

follow

the

Von

Neumann

also known as the Stored Program


Architecture or the Fetch-DecodeExecute Architecture.

A Von Neumann architecture simply means that


programs (together with data) are stored in main
memory during execution.

Not all computers follow the Von Neumann


architecture. Some examples are processor array
architecture, multiprocessor architecture, dataflow
architecture, and neural network architecture.

Basic Structure of Computer Hardware and Software

ASSEMBLY LANGUAGE

Types of Programming Language

1.

Machine Language. The natural or primitive


language that the computer actually understands.
This programming language consists of 0s and
1s which makes programming very difficult.

Sample machine language program to add 5 and


3 (using the Intel microprocessor instruction set):

10111000
00000101
00000000
10111011
00000011
00000000
00010001
11011000

Basic Structure of Computer Hardware and Software

2.

Assembly Language

A
programming
language
that
uses
abbreviations or mnemonics in place of binary
patterns in order to make the task of
programming easier. Mnemonics are designed to
be easy to remember and are a significant
improvement over binary digits.

An assembly language program has to be


converted to machine language before a computer
can execute it. An assembler is a special
program that translates assembly language
mnemonics into machine language.

Sample assembly language program to add 5 and


3 (using the Intel microprocessor instruction set):

MOV AX, 05
MOV BX, 03
ADC AX, BX

NOTE:

Both machine and assembly languages


are low-level programming languages.

Basic Structure of Computer Hardware and Software

3.

High-Level Language

A programming language that uses English-like


commands or instructions. High-level languages
are the easiest to use and contains many
complicated or advanced instructions.
A high-level language has to be converted to
machine language before a computer can execute
it. A compiler is a special program that translates
high-level language instructions into machine
language.
Examples of High-level Languages:
1.
2.
3.
4.

FORTRAN (FORmula TRANslation)


COBOL (COmmon Business-Oriented
Language)
BASIC (Beginners All-purpose Symbolic
Instruction Code)
Pascal

Sample BASIC program to add 5 and 3:


LET A = 5
LET B = 3
LET C = A + B

Basic Structure of Computer Hardware and Software

Advantages of using high-level languages over lowlevel languages:

1.

Easy to Learn. Low-level languages are


more cryptic than high-level language.

2.

Predefined Functions. Most high-level


languages provide many pre-defined
functions
and
subroutines,
thereby
simplifying programming tasks.

3.

Portability.
Low-level languages are
specific towards a certain processor. The
instruction set of the Intel processors (IBM
PCs and compatibles) is very much
different from the instruction set of the
Motorola processors (Apple Macintosh).

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10

Advantages of using low-level languages over highlevel languages:

1.

Compact Code. Programs are executed in


their machine language format. Programs
written in a high-level language should still
be compiled and translated to machine
language. Most compilers are not optimized
to generate compact code.

2.

Speed. This is directly related to compact


code. The shorter the code, the shorter the
execution time of the program.

3.

Flexible. Low-level language does not


constrain the programmer to follow a certain
programming convention (i.e. modularity)
nor a rigid coding constraint (i.e. the called
routine should be placed before the calling
routine).

Application programs are now more and more


complex and test the high-level language to its limit.
High-level programmers now use assembly languagebased subroutines to augment the capabilities of highlevel languages.

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11

BASIC OPERATIONAL CONCEPTS

Example of a typical assembly language instruction:

ADD R0, LOCA

Add the operand at memory


location LOCA to the operand in a
register in the processor, R0 and
place the result into register R0.

The given instruction requires the performance of


several steps:

1.

The instruction must be transferred or


fetched from the MM into the CPU.

2.

The operand at LOCA must be fetched and


added to the contents of R0.

3.

The resultant sum is stored in register R0.

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12

In order to fetch/read an instruction or data from main


memory:

1.

The CPU first sends the address of the memory


location to be read.

2.

The CPU then issues or sends the read signal to


the memory.

3.

The word is then read out of memory and is


loaded into a CPU internal register.

In order to store/write data into main memory:

1.

The CPU first sends the address of the memory


location to be written.

2.

The CPU then sends the write signal together


with the data or word to be written to memory.

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13

Connections between the processor and the main


memory:
Main Memory

MAR
PC
IR

CPU

MDR

Control

R0
R1
.
.
.
Rn-1

ALU

n General Purpose
Registers

The PC (Program Counter) contains the memory


address of the instruction to be executed. During
execution, the contents of the PC are updated to point
to the next instruction.
The MAR (Memory Address Register) holds the
address of the location to or from which data are to be
transferred.
The MDR (Memory Data Register) contains the data
to be written or read out of the addressed location.
The IR (Instruction Register) contains the instruction
that is being executed.

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14

Operating Steps:

1.

2.

3.
4.

5.

PC is set to point to the first instruction of the


program (the operating system loads the memory
address of the first instruction).
The contents of the PC are transferred to the
MAR (which are automatically transmitted to the
MM) and a Read signal is sent to the MM.
The addressed word is read out of MM and
loaded into the MDR.
The contents of MDR are transferred to the IR.
The instruction is ready to be decoded and
executed.
During execution, the contents of the PC are
incremented or updated to point to the next
instruction.
If operand or data needed by the instruction
resides in MM:
1. It will have to be fetched by sending its
address to the MAR and initiating a
read cycle.
2. When the operand has been read from
MM into the MDR, it may be
transferred from the MDR to the ALU
If result is to be stored in MM:
1. The result is sent to the MDR.
2. The address of the location where the
result is to be stored is sent to the MAR
and a write cycle is initiated.

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15

BUS STRUCTURES

A bus is a collection of wires that connect several


devices within a computer system.

When a word of data is transferred between units, all


its bits are transferred in parallel.

A computer must have some lines for addressing and


control purposes.

Three main groupings of lines:

1.

Data Bus. This is for the transmission of data.

2.

Address Bus. This specifies the location of data


in MM.

3.

Control Bus. This indicates the direction of data


transfer and coordinates the timing of events
during the transfer.

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16

Single-Bus Structure

Input

Output

Memory

Processor

All units are connected to a single bus, so it provides


the sole means of interconnection.

Only two units can actively use the bus at any given
time.

Bus control lines are used to arbitrate multiple


requests for the use of the bus.

Buffer Registers are used to hold information during


transfers. These prevent a high-speed processor from
being locked to a slow I/O device during a sequence
of data transfers.

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17

Two-Bus Structure
Configuration 1

Input
Processor
Output

Memory
Memory
Bus

I/O Bus

Configuration 2

Input
Memory
Output

Processor
Memory
Bus

I/O Bus

In the second configuration, I/O transfers are made


directly to or from the memory. A special purpose
processor called peripheral processor or I/O channel
is needed as part of the I/O equipment to control and
facilitate such transfers.

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18

MEMORY LOCATIONS AND ADDRESSES

MM is organized so that a group of n bits can be


stored or retrieved in a single basic operation.
n bits

Addresses
0

word 0

word 1
.
.
.

bn-1

b1 b0

word i

.
.
.
M-1

word M - 1

The M addresses constitute the address space of the


computer system.
Example: For the Intel 8088/86 Microprocessor
Address Space = 1,048,576 addresses or memory
locations
using
binary
encoding
of
addresses, 20 bits are needed to
represent all addresses,
220 = 1,048,576

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19

The contents of memory locations can represent


either:
1.
2.

instructions
operands or data
numbers
characters

An instruction usually contains two parts:


1.
2.

the part that specifies the operation to be


performed (op-code field).
the part that may be used to specify operand
addresses.

Examples:
1.

2.

32-bit instruction
8 bits

24 bits

Operation
Field

Addressing Information

16-bit instruction (8088/86)


10001011 11101100
MOV

Basic Structure of Computer Hardware and Software

SP TO BP

20

MAIN MEMORY OPERATIONS

Fetch or Read. This transfers the contents of a


specific MM location to the CPU. The word in the
MM remains unchanged.
Read/Fetch Cycle:

1.

CPU sends address of the desired


location.

2.

MM reads the data stored at that


address and sends it to the CPU.

Store or Write. This transfers a word of information


from the CPU to a specific MM location. This
destroys the former contents of that location.
Write/Store Cycle:
1.

CPU sends address of the desired


location to the MM, together with the
data to be stored into that location.

2.

Data is written at desired location.

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21

INSTRUCTIONS AND INSTRUCTION SEQUENCING

Types of Instructions:
1.

Data transfers between MM and CPU


registers.

2.

Arithmetic and logic operations on data.

3.

Program sequencing and control.

4.

I/O operations or transfers.

Notations
R1

[LOC]
The contents of memory location LOC
are transferred into register R1.

[A] + [B]
The operands in memory locations A
and B are fetched from MM and
transferred into the CPU, where they
will be added in the ALU. Then the
resulting sum is to be stored into
memory location C in MM.

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22

Three-Address Instructions
ADD A, B, C

[B] + [C]

B and C = source operands


A
= destination operands

Two-Address Instructions
ADD A, B

[A] + [B]

MOVE B, C

[C]

A common convention used is to write twooperand instructions in the form:


operation destination, source

One-Address Instructions
Since addition is a two-operand operation, an
implicit assumption must be made regarding the
location of one of the operands as well as the
result.
A general purpose CPU register,
usually called the accumulator, may be
used for this purpose.

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23

Examples:
ADD A

ACC

[A] + [ACC]

Add the contents of memory


location A to the contents of the
accumulator and place the sum
into the accumulator.
LOAD A

ACC

[A]

Move the contents of memory


location A into the accumulator.
STORE A

[ACC]

Move the contents of memory


location A into the accumulator.
Sample Program:
LOAD A
ADD B
STORE C

ACC
ACC
C

[A]
[B] + [ACC]
[ACC]

Zero-Address Instructions
Instructions where the locations of all operands
are defined implicitly.

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24

Two-Phase Procedure in Instruction Execution:

1.

Instruction Fetch.

Instruction is fetched from MM


location whose address is in the
program counter. The instruction
is then placed in the instruction
register in the CPU.

2.

Instruction Execute.

The instruction in the instruction


register is examined to determine
which operation is to be
performed.
The CPU then
performs the specified operation.

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25

Instruction Execution and Straight-Line Sequencing.


Example 1:

Contents

Addresses
i

MOVE R0, A

i+1

ADD R0, B

i+2

MOVE C, R0
.
.
.

3-Instruction
Program
S egment

A
.
.
.
B

Data for the


program

.
.
.
C

To begin the execution of this program, the


address of its first instruction (i) must be placed
into the PC.
The CPU control circuits automatically proceed
to fetch and execute instructions, one at a time, in
the order of increasing addresses. This is
straight-line sequencing.

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26

Example 2:

Addresses

Contents

MOVE R0, NUM1

i+1

ADD R0, NUM2

i+2

ADD R0, NUM3


.
.
.
ADD R0, NUMn

i+n-1
i+n

MOVE S UM, R0
.
.
.

S UM
NUM1
NUM2
.
.
.
NUMn

This program will add a list of n numbers. The


addresses of the memory locations containing the
n numbers are symbolically given as NUM1,
NUM2, . . ., NUMn, and the resulting sum is
placed in memory location SUM.

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27

Branching
The fundamental idea in program loops
is to cause a straight-line sequence of
instructions to be executed repeatedly.

CLEAR R0
MOVE R1, N
LOOPS TART

Determine address of
"Next" number and
add "Next" number to
R0
DEC R1

Program
Loop

Branch > 0
LOOPS TART
MOVE S UM, R0
.
.
.
S UM
N
NUM1
NUM2
.
.
.
NUMn

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28

8086/8088 ARCHITECTURE
HISTORY OF THE INTEL MICROPROCESSORS

The 4-bit Microprocessors


Intel released the worlds first p in 1971. The
4004 is a 4-bit p with maximum memory of
only up to 4,096 4-bit memory locations (2,048
bytes). It only has 45 instructions and was used
in very limited applications such as early video
games and small p-based controllers.

The 8-bit Microprocessors


1.

In 1972, Intel released the 8008 which is an


8-bit p capable of addressing 16,384 bytes
and has 48 instructions. It can execute an
ADD instruction in 20 s.

2.

In 1973, Intel released the 8080. The 8080


can address a total of 65,536 bytes and can
execute an ADD instruction in 2 s only.

3.

In 1977, the 8085 was released. It addresses


the same amount of memory as the 8080 but
it can execute an ADD instruction in 1.3 s.
It also has a built-in clock generator and
system controller.

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29

The 16-bit Microprocessors


In 1978, Intel released the 8086 p and a year
later the 8088. Both are 16-bit ps and can
execute instructions in as little as 400 ns. Both
can address a total of 1,048,576 bytes or
524,288 16-bit words.

These 16-bit microprocessors have multiplication


and division instructions. These functions were
not available in most 8-bit ps.

The main difference between the 8086 and the


8088 is the size of their external data bus. The
external data bus of the 8088 is only 8-bits wide
while that of the 8086 is 16-bits wide (take note
the internal data bus of the 8088 is 16-bits wide).
The reason for this is that many designers still
wanted to use the cheaper 8-bit support and
peripheral chips in their 16-bit systems.
The 8088 was the p used by IBM in their
Personal Computer (PC), the PC XT, and the
Portable Computer.

Basic Structure of Computer Hardware and Software

30

BASIC 8086/8088 ARCHITECTURE


EU

BIU

Register
Array

S egment
Register and
IP

Bus
Controller

ALU & CU
IR

Prefetch
Queue

Execution Unit (EU).


This is responsible for
executing the instructions.

Bus Interface Unit (BIU). This is responsible for


fetching an instruction, the operand of an instruction
or data from the MM.

Instruction Pointer (IP). This is the program counter.

Prefetch Queue. The 8086/8088 prefetches the


succeeding instructions while executing the current
one.

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31

8086/8088 BUS STRUCTURE

Basic 8086 and 8088 Systems

Address Bus

8086
S ystem

8088
S ystem

Data Bus

D0 to D15

Control Bus

RD, WR, M/IO

Address Bus

A0 to A19

Data Bus

Control Bus

A0 to A19

D0 to D7

To
Memory
and I/O

To
Memory
and I/O

RD, WR, IO/M

The M/IO (or IO/M) signal is for selecting the


memory or I/O of the system. If it is a logic 0, then
memory is selected; if it is logic 1, I/O is selected.

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32

MEMORY AND THE 8086/8088

Logical memory is the name given to the memory


viewed by the programmer.
FFFFFH
FFFFEH
FFFFDH
1M
Bytes

8086/8088
Logical
Memory Map

00002H
00001H
00000H

The logical memory space is the same for both the


8086 and the 8088. It starts at memory location
00000H and extends to location FFFFFH. The logical
memory is 8 bits wide.

A 16-bit word of memory begins at any byte address


and extends for two consecutive bytes. For example,
the word at location 00122H is stored at byte 00122H
and 00123H with the least significant byte stored in
location 00122H.

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33

The physical memory is the actual organization of the


memory that the hardware designers see. The physical
memory map of the 8088 is identical to its logical
memory map.

Odd Bank

Even Bank

FFFFFH

FFFFEH

FFFFDH

FFFFCH
FFFFAH

FFFFBH
512 K
Bytes

512 K
Bytes

00005H

00004H

00003H
00001H

00002H
00000H

16 bits

The physical memory of the 8086 contains two banks


of memory.

The advantage of this organization is that the 8086 can


read or write a 16-bit word in one operation (provided
the addresses of the data are even). The 8088 requires
two reads or writes to transfer 16 bits of data.

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34

DEDICATED AND GENERAL USE OF MEMORY

Addresses 00000H to 00013H (20 memory locations)


are dedicated while addresses 00014H to 0007FH
(108 memory locations) are reserved.

These 128 bytes or memory locations


are used for storage or pointers to
interrupt service routines.

Addresses FFFF0H to FFFFBH (12 memory


locations) are dedicated for functions such as storage
of the hardware reset jump instruction.

Addresses FFFFCH to FFFFFH (4 memory locations)


are reserved for use with future products.

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35

THE PROGRAMMING MODEL

All forms of programming depend upon a clear


understanding of the internal register structure of the
p.

Register Structure of the 8086/8088


8 Bits

8 Bits

AH

AL

BH

BL

CH

CL

DH

DL

AX
BX

Accumulator
Base

CX
DX

Count
Data

SP

S tack Pointer

BP

Base Pointer

SI

S ource Index

DI

Destination Index

IP

Instruction Pointer

CS

Code S egment

DS

Data S egment

SS

S tack S egment

ES

Extra S egment

General
Purpose
Register

Pointer and
Index
Registers

S egment
Registers

Flags
16 Bits

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36

General Purpose Registers. These are used in any


manner that the programmer wishes.
Each is
addressable as a 16-bit register (AX, BX, CX, DX) or
as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH,
and DL).

1.

AX (Accumulator). This is often used to


hold temporary result after an arithmetic and
logic operation.

2.

BX (Base). This is often used to hold the


base address of data located in the memory.

3.

CX (Count). This holds the count for


certain instructions such as shift count (CL)
for shifts and rotates, the number of bytes
(CX) operated upon by the repeated string
instructions, and a counter (CX) with the
LOOP instruction.

4.

DX (Data). This holds the most significant


part of the product after a 16-bit
multiplication and the most significant part
of the dividend before a division.

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37

Pointer and Index Registers. Although the pointer


and index registers are also general purpose in nature,
they are more often used to index or point to the
memory location holding the operand data for many
instructions.

1.

SP (Stack Pointer). This is used to address


data in a LIFO (last-in first-out) stack
memory. This occurs most often when the
PUSH and POP instructions are executed.

2.

BP (Base Pointer). This is often used to


address an array of data in memory.

3.

SI (Source Index). This is used to address


source data indirectly for use with string
instructions.

4.

DI (Destination Index). This is normally


used to address destination data indirectly
for use with the string instructions.

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38

Status Register or Processor Status Word. This


contains 16 bits, but 7 of them are not used. Each bit
in the PSW is a flag. These flags are divided into the
conditional flags (they reflect the result of the
previous operation involving the ALU) and the
control flags (they control the execution of special
functions).

The conditional flags are:


1.

Sign Flag (SF) - b7


This is equal to the MSB of the result
of the previous operation. 0 if positive,
1 if negative.

2.

Zero Flag (ZF) - b6


This is set to 1 if the result of the
previous operation is zero and 0 if the
result is nonzero.

3.

Parity Flag (PF) - b2


This is set to 1 if the low-order 8 bits of
the result of the previous operation
contain an even number of 1s.
Otherwise, it is reset to 0.

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39

4.

Carry Flag (CF) - b0


An addition causes this flag to be set to
1 if there is a carry out of the MSB, and
a subtraction causes it to be set to 1 if
a borrow is needed.

5.

Overflow Flag (OF) - b11


This is set to 1 if an overflow occurs, i.e., a result
is out of range. More specifically, for addition
this flag is set to 1 when there is a carry into the
MSB and no carry out of the MSB or vice-versa.
For subtraction, it is set to 1, when the MSB
needs a borrow and there is no borrow from the
MSB, or vice-versa.

6.

Auxiliary Carry Flag (AF) - b4


This flag is used exclusively for BCD
arithmetic. It is set to 1 if there is a
carry out of bit 3 (b3) during an
addition or a borrow by bit 3 during a
subtraction.

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Examples:

SF = 0

ZF = 0

SF = 1

ZF = 0

SF = 0

ZF = 1

SF = 1

ZF = 0

0010 0011 0100 0101


0011 0010 0001 1001
0101 0101 0101 1110
PF = 0

CF = 0

AF = 0

OF = 0

0101 0100 0011 1001


0100 0101 0110 1010
1001 1001 1010 0011
PF = 1

CF = 0

AF = 1

OF = 1

0110 0010 1010 0000


1001 1101 0110 0000
0000 0000 0000 0000
PF = 1

CF = 1

AF = 0

OF = 0

0001 0010 0011 0100


0100 1010 1110 0000
1100 0111 0101 0100
PF = 0

Basic Structure of Computer Hardware and Software

CF = 1

AF = 0

OF = 0

41

The control flags are:

1.

Direction Flag (DF) - b10

This flag is used by string manipulation instructions. If clear, the string is processed from its beginning
with the first element having the lowest address. Otherwise, the string is processed from the high address
towards the low address.

2.

Interrupt Enable Flag (IF) - b9


If set, a certain type of interrupt (a
maskable interrupt) can be recognized
by the CPU; otherwise, these interrupts
are ignored.

3.

Trap Flag (TF) - b8


If set, the 8086/8088 will enter into a
single-step mode. In this mode, the
CPU executes one instruction at a time.

Basic Structure of Computer Hardware and Software

42

SEGMENT REGISTERS AND MEMORY SEGMENTATION

Even though the 8086/8088 has a 1 MB memory


address space, not all this memory can be active at any
one time.

The MM can be partitioned into 64 K (65,536) byte


segments where each segment represents an
independently addressable unit of memory consisting
of 64 K consecutive byte-wide storage locations.

Each segment is assigned a base address that


identifies its starting point, that is, its lowestaddressed byte storage location.

64 KB
S egment

Base Address

Basic Structure of Computer Hardware and Software

43

GENERATING A MEMORY ADDRESS

A logical address in the 8086/8088 is identified by a


segment (its base address) and an offset. The offset
identifies the distance in bytes that the storage location
of interest resides from this starting address.

.
.
.
Data
Offset

64 KB
S egment

.
.
.

Base Address

Both segment base address and offset are 16 bits long.


Therefore, the lowest-addressed byte in a segment has
an offset of 0000H and the highest-addressed byte has
an offset of FFFFH.

However, the physical addresses that are used to


access memory are 20 bits long. The generation of the
physical address involves combining a 16-bit offset
value and a 16-bit segment base address value that is
shifted-left by 4 bits with its LSBs being filled with
0s.

Basic Structure of Computer Hardware and Software

44

Examples:
1.

Segment Base Address = 1234H


Offset Address
= 0022H
Computing for the physical address:

2.

Physical Segment Base Address = 12340H


Offset Address
= 0022H
Physical Address
= 12362H

Segment Base Address = 123AH


Offset Address
= 341BH
Computing for the physical address:

Physical Segment Base Address = 123A0H


Offset Address
= 341BH
Physical Address
= 157BBH

Take note that the offset address is sometimes called


the effective address.

Logical addresses are often written following the


segment base address:offset format.
Example: 1234H:0022H

Basic Structure of Computer Hardware and Software

45

Only four of these segments can be active at any one


time. They are the code segment, stack segment, data
segment, and extra segment.

The locations of the segments of memory that are


active are identified by the value of the address held in
the 8086/8088s four internal segment registers; CS,
SS, DS, and ES.

Code
S egment

S tack
S egment

CS
SS
DS
ES
S egment
Registers

Data
S egment

Extra
S egment

Basic Structure of Computer Hardware and Software

46

The segments are:

1.

Code Segment. This contains the program or


code. The address of the next instruction
executed by the 8086/8088 is generated by
adding the contents of IP (offset address) to the
contents of CS x 10H.

2.

Data Segment. This contains data referenced by


almost all instructions and many addressing
modes. Data are almost always moved into or
out of MM via the data segment. The physical
address of the data is generated by adding the
contents of one of the index or pointer registers
(BX, DI, or SI) to the contents of DS x 10H.

3.

Stack Segment. This is for the LIFO stack. The


physical address is a combination of the contents
stack pointer (SP) plus SS x 10H.

4.

Extra Segment. This is normally for string


instructions.
When a string instruction is
executed, the destination location is addressed by
the destination index register (DI) plus ES x 10H.

Basic Structure of Computer Hardware and Software

47

THE STACK

The stack is implemented in MM of the 8086/8088. It


is 64 KB long and is organized from a software point
of view as 32 K words.

The lowest-addressed byte in the current stack is


pointed to by the base address in the SS register.

Any number of stacks may exist in the 8086/8088. A


new stack can be brought in by simply changing the
value in the SS register. However, only one may be
active at any one time.

The SP contains an offset from the value in SS. The


address obtained in the SS and SP is the physical
address of the top of the stack or TOS (the last storage
location in the stack to which data were pushed).

The value of SP is initialized to FFFFH upon start-up


of the microcomputer. Combining the value with the
current value in SS gives the highest-addressed
location in the stack (bottom of the stack). The stack
grows down in memory from offset FFFFH to 0000H.

Basic Structure of Computer Hardware and Software

48

Whenever a word of data is pushed onto the stack, the


high-order 8 bits are placed in the location addressed
by SP - 1, and the low-order 8 bits are placed in the
location addressed by SP - 2.
SP is then decremented by 2 so that the next
word of data is stored in the next available
memory location.
Example:
PUSH BX
Assume: BX = 1234H
SS = 1800H SP = 3A74H
Bottom of the Stack = SS x 10H + FFFFH
= 18000H + FFFFH
= 27FFFH
Stack Segment = 18000H up to 27FFFH
Top of the Stack

PUSH BX;

= SS x 10H + SP
= 18000H + 3A74H
= 1BA74H

1BA73H
1BA72H

New Top of Stack =

Basic Structure of Computer Hardware and Software

(BH) = 12H
(BL) = 34H
1BA72H (SP = 3A72H)

49

Whenever a word of data is popped from the stack, the


low-order 8 bits are removed from the location
addressed by SP, and the high-order 8 bits are
removed from the location addressed by SP + 1.
SP is then incremented by 2.

Example:
POP CX
Assume: SS = 1234H SP = 281AH
Bottom of the Stack = SS x 10H + FFFFH
= 12340H + FFFFH
= 2233FH
Stack Segment = 12340H up to 2233FH
Top of the Stack

POP CX;

= SS x 10H + SP
= 12340H + 281AH
= 14B5AH

CL
CH

New Top of Stack =

Basic Structure of Computer Hardware and Software

(14B5AH)
(14B5BH)
14B5CH (SP = 281CH)

50

ADDRESSING MODES

Addressing modes refer to the way in which an


operand is specified.

Data Addressing Modes:


Case Study: MOV destination, source
1.

Register Addressing.
The operand to be
accessed is specified as residing in an internal
register of the 8086/8088.
Examples:
MOV AX, CX;
MOV BX, DX;

AX
BX

[CX]
[DX]

In both examples, AX and BX are the destination


operands while CX and DX are the source
operands.

2.

Immediate Addressing. The source operand is


part of the instruction instead of the contents of a
register.
Typically, immediate operands
represent constant data.
Examples:
MOV AL, 15H;
MOV AX, 1A3F;

Basic Structure of Computer Hardware and Software

AL
AX

15H
1A3FH

51

3.

Direct Addressing. The location following the


instruction opcode holds an effective memory
address (EA) instead of data. This EA is the 16bit offset of the storage location specified by the
current value of the DS register.

Examples:
MOV AX, BETA
AX

[DS x 10H + BETA]

If BETA = 1234H and DS = 0200H, then:

PA = DS x 10H + BETA
= 02000H + 1234H = 03234H

MOV AX, BETA;

AL
AH

Basic Structure of Computer Hardware and Software

AX

[03234H]

[03234H]
[03235H]

52

MOV AX, LIST


AX

[DS x 10H + LIST]

If LIST = 000AH and DS = BAAFH, then:


PA = DS x 10H + LIST
= BAAF0H + 000AH = BAAFAH
MOV AX, LIST;
AL
AH

AX

[BAAFAH]

[BAAFAH]
[BAAFBH]

MOV CL, [2000H]


CL

[DS x 10H + 2000H]

If DS = 1000H, then:
PA = DS x 10H + 2000H
= 10000H + 2000H = 12000H
MOV CL, [2000H];

Basic Structure of Computer Hardware and Software

CL

[12000H]

53

4.

Register Indirect Addressing. Similar to direct


addressing but this time, the EA resides in either
a base register (BX, BP) or index register (SI, DI)
within the 8086/8088.
Examples:
MOV AX, [BX];

AX

[DS x 10H + BX]

If BX = C15EH and DS = 1829H, then:


PA = DS x 10H + BX
= 18290H + C15EH = 243EEH
MOV AX, [BX];
AL
AH

MOV AX, [SI];

AX

[243EEH]

[243EEH]
[243EFH]

AX

[DS x 10H + SI]

If SI = 00BEH and DS = 58A2H, then:


PA = DS x 10H + SI
= 58A20H + 00BEH = 58ADEH
MOV AX, [SI];
AL
AH

Basic Structure of Computer Hardware and Software

AX

[58ADEH]

[58ADEH]
[58ADFH]

54

If BP is used, then the stack segment is addressed


instead of the data segment

Example:

MOV CX, [BP];

AX

[SS x 10H + BP]

If BP = 1800H and SS = 8050H, then:


PA = SS x 10H + BP
= 80500H + 1800H = 81D00H

MOV CX, [BP];

CL
CH

Basic Structure of Computer Hardware and Software

CX

[81D00H]

[81D00H]
[81D01H]

55

5.

Register Relative Addressing or Base


Addressing. The physical address of the operand
is obtained by adding a direct or indirect
displacement to the contents of either BX or BP
and the current value in DS or SS, respectively.

Examples:
MOV AX, [BX + 1000H]
AX

[DS x 10H + BX + 1000H]

If BX = 0100H and DS = 0200H, then:


PA = DS x 10H + BX + 1000H
= 02000H + 0100H + 1000H
= 03100H

MOV AX, [BX + 1000H];

AL
AH

Basic Structure of Computer Hardware and Software

AX

[03100H]

[03100H]
[03101H]

56

MOV AL, [BX] + BETA


AX

[DS x 10H + BX + BETA]

If BX = 1000H, BETA = 1234H and DS =


0200H, then:
PA = DS x 10H + BX + BETA
= 02000H + 1000H + 1234H
= 04234H
MOV AL, [BX] + BETA;
AL
[04234H]

MOV DI, SET[BX]


DI

[DS x 10H + SET + BX]

If BX = FB04H, SET = 001AH, and DS =


0210H, then:
PA = DS x 10H + SET + BX
= 02100H + 001AH + FB04H
= 11C1EH
MOV DI, SET[BX];
DIlow
DIhigh

Basic Structure of Computer Hardware and Software

DI

[11C1EH]

[11C1EH]
[11C1FH]

57

6.

Base-Plus-Index Addressing. This is used to


transfer a byte or word between a register and the
memory location indicated by the sum of a base
register and an index register.

Examples:
MOV AX, [BX + SI]
AX

[DS x 10H + BX + SI]

If SI = 2000H, BX = 1234H, and DS = 0200H,


then:
PA = DS x 10H + BX + SI
= 02000H + 1234H + 2000H
= 05234H

MOV AX, [BX + SI];

AL
AH

Basic Structure of Computer Hardware and Software

AX

[05234H]

[05234H]
[05235H]

58

MOV [BX + DI], SP


[DS x 10H + BX + DI]

SP

If DI = 175CH, BX = 1256H, and DS = 0205H,


then:

PA = DS x 10H + BX + DI
= 02050H + 1256H + 175CH
= 04A02H

MOV [BX + SI], SP;

04A02H
04A03H

Basic Structure of Computer Hardware and Software

04A02H

[SP]

[SPlow]
[SPhigh]

59

7.

Base-Relative-Plus-Index Addressing. This is


used to transfer a byte or word between a register
and the memory location addressed by a base
register and an index register plus a
displacement.

Examples:
MOV AX, [BX + SI + 0100H];
AX

[DS x 10H + BX + SI + 1000H]

If DS = 1000H, BX = 0020H, and SI = 0010H,


then:
PA = DS x 10H + BX + SI + 1000H
= 10000H + 0020H + 0010H + 1000H
= 11030H

MOV AX, [BX + SI + 1000H];


AX

AL
AH

Basic Structure of Computer Hardware and Software

[11030H]

[11030H]
[11031H]

60

MOV AX, FILE[BX + DI];


AX

[DS x 10H + BX + DI + FILE]

If DS = 1F00H, BX = 3000H, DI = 0015H, AND


FILE = 1234H, then:

PA = DS x 10H + BX + DI + FILE
= 1F000H + 3000H + 0015H + 1234H
= 23249H

MOV AX, FILE[BX + DI];


AX

AL
AH

Basic Structure of Computer Hardware and Software

[23249H]

[23249H]
[2324AH]

61

BASIC 8086/8088 INSTRUCTIONS


INTRODUCTION

The instruction set of a microcomputer defines the


basic operations that a programmer can make the
device perform.

There are 117 basic instructions for the 8086/88 chip.

Classification of Instructions:
1.

Data Transfer Instructions

2.

Arithmetic Instructions

3.

Logic Instructions

4.

Shift Instructions

5.

Rotate Instructions

6.

Flag Control Instructions

7.

Jump Instructions

8.

String Instructions

Basic Structure of Computer Hardware and Software

62

DATA TRANSFER INSTRUCTIONS

Data transfer instructions facilitate the movement of


data either between registers or between a register and
main memory. They do not affect the flags.

The MOV Instruction


Format:

MOV D, S

Action:

Destination
register
register
MM
register
MM
seg reg
register
seg reg
MM

Source
register
MM
register
immediate
immediate
register
seg reg
MM
seg reg

Basic Structure of Computer Hardware and Software

[S]

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

Example
CX, BX
CX, [BP+SI]
[BX], DX
CX, 80FEH
word ptr [BX], 1834H
DS, BX
AX, CS
SS, [1AFFH]
[BP+SI+1000H], DS

63

Pointers:
1.

The MOV instruction does not allow both source


and destination operands to be memory locations
(no memory to memory transfers).
The
instruction MOV [BX], FILE is invalid.

2.

Both source and destination operands should be


of the same data size. Therefore, the instruction
MOV AH, BX is invalid.

3.

Immediate data cannot be moved to a segment


register. MOV DS, 1800H is therefore invalid.
Instead, use:
MOV AX, 1800H
MOV DS, AX

4.

The destination operand cannot be immediate


data. MOV 1800H, AX is therefore invalid.

5.

More often than not, register CS cannot be the


destination operand.

6.

If the destination operand is a memory location


and the source operand is immediate data, the
prefix byte ptr or word ptr should appear after the
MOV instruction to denote the data size of the
immediate operand.

Basic Structure of Computer Hardware and Software

64

The XCHG Instruction


The XCHG (Exchange) instruction swaps the
contents of the source and destination operands.
Format:

XCHG D, S

Action:

[D]

Destination
MM
register

Source
register
register

[S]

Example
XCHG [BX], CX
XCHG AH, BL

Pointers:
1.

The XCHG instruction does not allow both


source and destination operands to be memory
locations (no memory to memory transfers). The
instruction XCHG [BX], FILE is therefore
invalid.

2.

Both source and destination operands should be


of the same data size. Therefore, the instruction
XCHG AH, BX is invalid.

Basic Structure of Computer Hardware and Software

65

3.

Immediate addressing cannot be used with this


instruction. The instruction XCHG AX, 1800H
is invalid.

4.

A data exchange can also be done using several


MOV instructions:
MOV
MOV
MOV
MOV

CX, AX
DX, BX
AX, DX
BX, CX

However, four registers are needed in order to


implement an exchange between two registers.

5.

Segment registers cannot be used as operands in


the XCHG instruction. XCHG ES, BX is
therefore invalid. Instead use:

MOV CX, ES
XCHG BX, CX
MOV ES, CX

Basic Structure of Computer Hardware and Software

66

The PUSH Instruction

The PUSH instruction decrements SP by 2 and then


moves a word data from the source operand to the top
of the stack pointed to by SP.

Format:

PUSH S

Action:

SP
[SP+ 1]
[SP]

SP - 2
[SH]
[SL]

Source
Example
register PUSH AX
seg reg PUSH DS
MM PUSH BETA

Pointers:
1.

The PUSH instruction pushes word-sized data


only.

Basic Structure of Computer Hardware and Software

67

The POP Instruction


POP transfers a word data pointed to by SP to the
destination operand. Afterwards, the value of SP is
incremented by 2.
Format:

POP D

Action:

DL
DH
SP

[SP]
[SP + 1]
SP + 2

Destination
Example
register
POP AX
seg reg
POP DS
MM
POP BETA

Pointers:
1.

The POP instruction pops word-sized data only.

2.

POP CS is not allowed.


instruction PUSH CS is valid.

Basic Structure of Computer Hardware and Software

However, the

68

The LEA Instruction

The LEA (Load Effective Address) instruction is for


transferring the effective address (not data) of the
source operand to the destination operand.
Format:

LEA D, S

Action:

EA of S

Pointers:

1.

The source operand should always be one of the


memory addressing modes, while the destination
operand should always be a 16-bit register.

2.

In the LEA instruction, the effective address is


moved to the destination operand. Therefore, the
destination operand is like a pointer.

3.

Usually, registers BX, BP, DI, or SI are used as


the destination operand since these registers
could be used as offset registers.

Basic Structure of Computer Hardware and Software

69

Examples:
Assume the following:
DS = 5000H
LIST = 1800H

51802H

44H

51801H

33H

51800H

22H

517FFH

11H

If the MOV DI, LIST instruction is


executed, the contents of memory location
51800H and 51801H are transferred to
register DI. DI will therefore contain the
word 3322H.

However, if the LEA DI, LIST instruction


is executed, this will transfer the effective
address of the source operand to register DI.
Therefore, DI will now contain 1800H.

Basic Structure of Computer Hardware and Software

70

ARITHMETIC INSTRUCTIONS

Review of Some Concepts Regarding the Binary


Number System

1.

Unsigned Integer. Unsigned integers may either


be 8 bits or 16 bits in length. Unsigned integers
are viewed as positive numbers only. This means
that all bits are considered in determining the
magnitude of a number.
The value range of an unsigned integer is from 0
to 2n - 1. For 8 bits, the range is from 0 to 255,
while for 16 bits, the range is from 0 to 65,535.

2.

Signed Integer. Signed integers are viewed as


either positive or negative numbers. Because of
this, the most significant bit is viewed as a sign
bit (0 for positive and 1 for negative).
The value range of a signed integer is -2n-1 to 2n-1
- 1. For 8 bits, the range is from -128 to +127
while for 16 bits, the range is from -32,768 to
+32,767. Negative numbers are represented in
twos complement.

Basic Structure of Computer Hardware and Software

71

3.

Binary-Coded Decimal (BCD). In BCD, each


decimal digit is represented in one nibble.
Examples:
99 = 1001 1001
103 = 0001 0000 0011

BCD uses only 10 out of 16 possible


combinations. The following 6 combinations are
never used: 1010, 1011, 1100, 1101, 1110, and
1111.

There are some situations in which arithmetic


operations on BCD numbers require some
adjustments. This happens if the result of the
operation falls into one of the six unused
combinations.
Examples:
12 =
+ 45 =
57

0001 0010
0100 0101
0101 0111

In this example, there is no need to


adjust result.

Basic Structure of Computer Hardware and Software

72

12 =
+ 49 =
61

0001 0010
0100 1001
0101 1011

Since 1011 is an invalid BCD code,


there is a need to adjust result. This
can be done by adding 6 (0110) to the
result:

0101 1011
0110
0110 0001 = 61

The 8086/8088 provides adjustment instructions


for BCD-based arithmetic operations.

4.

Packed BCD. In packed BCD, two BCD digits


could be packed into one byte.

5.

Unpacked BCD. In unpacked BCD, one BCD


digit is represented in one byte. The BCD digit is
represented in the least significant nibble, while
the most significant nibble may be 0 or any value.

Basic Structure of Computer Hardware and Software

73

Arithmetic instructions cover the four basic arithmetic


operations: addition, subtraction, multiplication, and
division. Arithmetic instructions affect the status
flags.

The ADD Instruction


The ADD instruction adds the source operand to the
destination operand and then places the result in the
destination operand.
Format:

ADD D, S

Action:

Destination
register
register
MM
register
MM

Source
register
MM
register
immediate
immediate

[D] + [S]
Example
ADD BX, CX
ADD DX, [BP + SI]
ADD [BX + DI], CX
ADD BX, 0015H
ADD byte ptr BETA, 12H

Pointers:
1.

The ADD instruction does not allow both


source and destination operands to be
memory locations (no memory to memory
addition). Therefore, the instruction ADD
[BX], BETA is invalid.

Basic Structure of Computer Hardware and Software

74

2.

Both source and destination operands


should be of the same data size. The
instruction ADD AH, BX is therefore
invalid.

3.

The destination operand cannot be


immediate data. Therefore, the instruction
ADD 1800H, CX is invalid.

4.

All status flags are affected after execution.

5.

As with the MOV instruction, if the


destination operand is a memory location
and the source operand is immediate data,
the prefix byte ptr or word ptr should appear
after the ADD instruction to denote the data
size of the immediate operand.

The ADC Instruction


The ADC (Add with Carry) instruction adds the
source operand and the carry flag to the destination
operand and places the result in the destination
operand.
Format:

ADC D, S

Action:

[D] + [S] + [CF]

One of the uses of the ADC instruction is in the


implementation of 32-bit addition (adding two 32-bit
numbers).
Basic Structure of Computer Hardware and Software

75

Example:

012F 8749H
3054 9312H
3184 1A5BH

Although there are no 32-bit addition


instructions, the problem is easily solved by
using the ADD and the ADC instructions.
MOV AX, 012FH
MOV BX, 8749H
MOV CX, 3054H
MOV DX, 9312H
ADD BX, DX
ADC AX, CX

The INC Instruction


The INC (Increment) instruction adds 1 to the
destination operand.
Format:

INC D

Action:

[D] + 1

Destination
Example
register
INC AX
MM
INC byte ptr [BX]

Basic Structure of Computer Hardware and Software

76

Pointers:
1.
2.
3.

4.

The destination operand is viewed as an unsigned


integer.
The INC instruction does not affect the carry
flag.
Segment registers cannot be used as the
destination operand. Therefore, the instruction
INC CS is invalid.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the INC instruction to denote the data size of the
destination operand.

The DAA Instruction


The DAA (Decimal Adjust for Addition) instruction
adjusts the result of a previous addition of two valid
packed decimal operands.
Format:

DAA

Pointers:
1.
2.
3.

The result of the previous operation should be in


register AL.
OF is undefined after execution.
DAA should be executed immediately after an
ADD, ADC, or INC instruction.

Basic Structure of Computer Hardware and Software

77

4.

The instruction will adjust the result as follows: if


AF = 1, or either of the nibbles is greater than 9,
then 6 is added to the nibble(s) concerned.

Example:
MOV AL, 15H
MOV BL, 15H
ADD AL, BL
DAA
In this example, the values of AL and BL are
viewed as packed BCD. Since DAA is used to
adjust the addition operation, the destination
operand should be at AL. Prior to DAA, the
value of AL is 2AH. After the DAA instruction,
the value of AL is adjusted to 30H. The
operation is as follows:
15H = 0001
15H = 0001
0010
+
0011

0101
0101
1010 = 2AH
0110
0000 = 30H

Since the least significant nibble of the


intermediate result is greater than 9, DAA adjusts
the result by adding 6 to the least significant
nibble.
Basic Structure of Computer Hardware and Software

78

The AAA Instruction

The AAA (ASCII Adjust for Addition) instruction


adjusts the result of a previous addition of two valid
unpacked decimal operands.
Format:

AAA

Pointers:
1.

The result of the previous operation should be in


register AL.

2.

OF, PF, SF, and ZF are undefined after


execution.

3.

AAA should be executed immediately after an


ADD, ADC, or INC instruction.

4.

The instruction will adjust the result as follows: if


the least significant nibble is greater than 9, then
6 is added to AL, and 1 is added to AH.

5.

Regardless of the value of the least significant


nibble, the most significant nibble is always
zeroed out.

Basic Structure of Computer Hardware and Software

79

Example:

MOV AL, 35H;


MOV BL, 34H;
ADD AL, BL
AAA

ASCII value of 5
ASCII value of 4

In this example, the values of AL and BL are


viewed as unpacked BCD (ASCII numbers).
Since AAA is used to adjust the addition
operation, the destination operand should be at
AL. Prior to AAA, the value of AL is 69H.
After the AAA instruction, the value of AL is
adjusted to 09H. The operation is as follows:

35H = 0011 0101


34H = 0011 0100
0110 1001

= 69H

Since the least significant nibble not greater than


9, the only adjustment needed is to zero out the
most significant nibble.

Basic Structure of Computer Hardware and Software

80

The SUB Instruction

The SUB instruction subtracts the source operand


from the destination operand and the places the result
in the destination operand.

Format:

SUB D, S

Action:

[D] - [S]

The SBB Instruction

The SBB (Subtract with Borrow) instruction subtracts


the source operand and the carry flag from the
destination operand and then places the result in the
destination operand.
Format:

SBB D, S

Action:

[D] - [S] - [CF]

Just like in addition, subtracting a 32-bit number from


another 32-bit number can be done with the
combination of the SUB and the SBB instructions.

Basic Structure of Computer Hardware and Software

81

Example:
3054 8312H
012F 8749H
2F24 FBC9H

MOV
MOV
MOV
MOV
SUB
SBB

AX, 3054H
BX, 8312H
CX, 012FH
DX, 8749H
BX, DX
AX, CX

The DEC Instruction

The DEC (Decrement) instruction subtracts 1 from


the destination operand.
Format:

DEC D

Action:

[D] - 1

Destination
Example
register
DEC AX
MM
DEC word ptr [BX]

Basic Structure of Computer Hardware and Software

82

Pointers:

1.

The destination operand is viewed as an unsigned


integer.

2.

The DEC instruction does not affect the carry


flag.

3.

Segment registers cannot be used as the


destination operand. Therefore, the instruction
DEC CS is invalid.

4.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the DEC instruction to denote the data size of the
destination operand.

The NEG Instruction


The NEG (Negate) instruction converts the specified
operand to its 2s complement equivalent and the
result returned to the operand location. This is, in
effect, reversing the sign of an integer.
Format:
Action:

NEG D
D

0 - [D]

Destination
Example
register
NEG AX
MM
NEG byte ptr [BX]

Basic Structure of Computer Hardware and Software

83

Pointers:
1. Attempting to negate an operand having a value
of zero causes no change to the operand and
resets the carry flag (CF = 0).
2. Attempting to negate an operand having a value
of either 80H or 8000H causes no change to the
operand and sets the overflow flag (OF = 1).
3. Segment registers cannot be used as the
destination operand. Therefore, the instruction
NEG CS is invalid.
4. If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the NEG instruction to denote the data size of the
destination operand.
Example:
Determine the value of AL and the value of
the flags following the instruction sequence:
MOV AL, 05H
NEG AL
AL contains:
0000 0000
- 0000 0101
1111 1011 = FBH = - 5
The flags are affected as follows:
CF = AF = SF =1, PF = ZF = OF = 0

Basic Structure of Computer Hardware and Software

84

The DAS Instruction

The DAS (Decimal Adjust for Subtraction)


instruction adjusts the result of a previous subtraction
of two valid packed decimal operands.

Format:

DAS

Pointers:

1.

The result of the previous operation should be in


register AL.

2.

OF is undefined after execution.

3.

DAS should be executed immediately after a


SUB, SBB, or DEC instruction.

4.

The instruction will adjust the result as follows: if


AF = 1, or either of the nibbles is greater than 9,
then 6 is subtracted from the nibble(s) concerned.

Basic Structure of Computer Hardware and Software

85

Example:

MOV AL, 34H


MOV BL, 19H
SUB AL, BL
DAS

In this example, the values of AL and BL are


viewed as packed BCD. Since DAS is used to
adjust the subtraction operation, the destination
operand should be at AL. Prior to DAS, the
value of AL is 1BH. After the DAS instruction,
the value of AL is adjusted to 15H. The
operation is as follows:

34H = 0011
19H = 0001
0001
0001

0100
1001
1011 = 1BH
0110
0101 = 15H

Since the least significant nibble of the


intermediate result is greater than 9, DAS adjusts
the result by subtracting 6 to the least significant
nibble.

Basic Structure of Computer Hardware and Software

86

The AAS Instruction


The AAS (ASCII Adjust for Subtraction) instruction
adjusts the result of a previous subtraction of two
valid unpacked decimal operands.
Format:

AAS

Pointers:
1.

The result of the previous operation should be in


register AL.

2.

OF, PF, SF, and ZF are undefined after


execution.

3.

AAS should be executed immediately after a


SUB, SBB, or DEC instruction.

4.

The instruction will adjust the result as follows: if


the least significant nibble is greater than 9, then
6 is subtracted from AL, and 1 is subtracted from
AH.

5.

Regardless of the value of the least significant


nibble, the most significant nibble is always
zeroed out.

Basic Structure of Computer Hardware and Software

87

Example:

MOV AL, 39H;


MOV BL, 34H;
SUB AL, BL
AAS

ASCII value of 9
ASCII value of 4

In this example, the values of AL and BL are viewed as


unpacked BCD (ASCII numbers). Since AAS is
used to adjust the subtraction operation, the
destination operand should be at AL. Prior to
AAS, the value of AL is 05H. After the AAS
instruction, the value of AL is adjusted to 05H.
The operation is as follows:

39H = 0011 1001


34H = 0011 0100
0000 0101

= 05H

Since the least significant nibble not greater than


9, the only adjustment needed is to zero out the
most significant nibble.

Basic Structure of Computer Hardware and Software

88

The CMP Instruction


The CMP (Compare) instruction subtracts the source
operand from the destination operand. It then discards
the result but it updates the values of all the status
flags.
Format:
Action:

CMP D, S
[D] - [S]

Destination
Source
Example
register
register CMP BX, CX
register
MM
CMP CX, BETA
MM
register CMP BETA, DX
register
immediate CMP SI, ABCDH
MM
immediate CMP byte ptr [BX], 34H
Pointers:
1. The CMP instruction does not allow both source
and destination operands to be memory locations
(no memory to memory comparison). CMP
[BX], BETA is therefore invalid.
2. Both source and destination operands should be
of the same data size. Therefore, the instruction
CMP AX, CL is invalid.
3. As with the MOV instruction, if the destination
operand is a memory location and the source
operand is immediate data, the prefix byte ptr or
word ptr should appear after the CMP instruction
to denote the data size of the immediate operand.

Basic Structure of Computer Hardware and Software

89

Program Tracing Example:

Trace the following program. Assume the following:


all flags and registers (unless specified otherwise) are
initially zero, DS = 8000H, SS = 8001H, the label
ALPHA = 0020H. Use the attached memory map (if
necessary).

MOV AX, ALPHA


MOV SP, AX
POP BX
ADD BX, AX
SUB BX, 0020H
XCHG BX, BP
MOV CX, [BP]
SBB AX, CX
ADC AX, 0029H
ADD AL, CL
DAA
NEG AX
LEA SI, ALPHA
MOV DX, [SI]

Basic Structure of Computer Hardware and Software

90

Solution:
1.

The instruction MOV AX, ALPHA simply loads the


contents of the memory location whose offset is
ALPHA to AX.
Physical Address

= DS x 10H + ALPHA
= 80000H + 0020H
= 80020H

Since [80020H] = 50H and [80021H] = 00H, the


contents of AX will be 0050H. The flags are not
affected (all flags are still zero).
2.

The instruction MOV SP, AX copies the contents of


AX to SP. SP will therefore be equal to 0050H. Flags
are not affected.

3.

The instruction POP BX transfers the contents of the


top of the stack to register BX.
Top of the Stack

= SS x 10H + SP
= 80010H + 0050H
= 80060H

Since [80060H] = 10H and [80061H] = 00H, the


contents of BX will be 0010H. The new contents of
SP will be SP + 2 = 0052H. Flags are not affected.

Basic Structure of Computer Hardware and Software

91

4.

The instruction ADD BX, AX adds the contents of BX


to the contents of AX and stores the results in BX.

AX =
BX =

0050H
0010H
0060H

The new contents of BX will be 0060H. The flags


will be:
OF
0

5.

SF
0

ZF
0

AF
0

PF
1

CF
0

The instruction SUB BX, 0020H will subtract 0020H


from the contents of register BX.
BX =
-

0060H
0020H
0040H

The new contents of BX will be 0040H. The flags


will be:
OF
0

SF
0

Basic Structure of Computer Hardware and Software

ZF
0

AF
0

PF
0

CF
0

92

6.

The instruction XCHG BX, BP will merely exchange


the contents of BX and BP with one another.
Since BP = 0000H and BX = 0040H, the new contents
will be BP = 0040H and BX = 0000H. The flags are
not affected and will remain as (from previous
instruction):
OF
0

7.

SF
0

ZF
0

AF
0

PF
0

CF
0

The instruction MOV CX, [BP] moves the contents of


the memory location whose offset is pointed to by BP
to CX. Since BP is used, the SS register is addressed
instead of DS.
Physical Address

= SS x 10H + BP
= 80010H + 0040H
= 80050H

Since [80050H] = 31H and [80051H] = 1FH, then the


new contents of CX will be 1F31H. The flags are not
affected and will remain as (from previous
instruction):
OF
0

SF
0

Basic Structure of Computer Hardware and Software

ZF
0

AF
0

PF
0

CF
0

93

8.

The instruction SBB AX, CX will subtract the contents


of CX and the carry flag from AX and stores the
results to AX.

AX =
CX =
CF =

0050H
1F31H
0
E11FH

The new contents of AX will be E11FH. The flags


will be:
OF
0
9.

SF
1

ZF
0

AF
1

PF
0

CF
1

The instruction ADC AX, 0029H adds the contents of


the hexadecimal number 0029H and the carry flag to
AX and stores the results to AX.
AX =
+
+

CF =

E11FH
0029H
1
E149H

The new contents of AX will be E149H. The flags


will be:
OF
0

SF
1

Basic Structure of Computer Hardware and Software

ZF
0

AF
1

PF
0

CF
0

94

10. The instruction ADD AL, CL will add the contents of


AL to CL and store the results to AL.

AL =
CL =

49H
31H
7AH

The new contents of AL will be 7AH. The flags will


be:
OF
0

SF
0

ZF
0

AF
0

PF
0

CF
0

11. The instruction DAA means that the previous addition


should be treated as a BCD addition.
Since the result of the previous addition is an invalid
BCD number (7AH), the DAA instruction will adjust
the result.
AL =
+

7AH
06H
80H

The new contents of AL will be 80H. The flags will


be:
OF
X

SF
1

Basic Structure of Computer Hardware and Software

ZF
0

AF
1

PF
0

CF
0

95

12. The instruction NEG AX will simply perform 2s


complement on the contents of AX.
The contents of AX is E180H. The twos complement
of E180H is 1E80H.
The new contents of AX will be 1E80H. The flags
will be:

OF
0

SF
0

ZF
0

AF
0

PF
0

CF
1

13. The instruction LEA SI, ALPHA will load the


effective address or offset represented by the label
ALPHA to register SI.
Since ALPHA is 0020H, the new contents of SI will
be 0020H.
The flags are not affected and will remain as (from
previous instruction):

OF
0

SF
0

Basic Structure of Computer Hardware and Software

ZF
0

AF
0

PF
0

CF
1

96

14. The instruction MOV DX, [SI] simply moves the


contents of the memory location whose offset is
pointed to by SP to DX.

Physical Address

= DS x 10H + SI
= 80000H + 0020H
= 80020H

Since [80020H] = 50H and [80021H] = 00H, the


contents of DX will be 0050H.
The flags are not
affected and will remain as (from previous
instruction):

OF
0

SF
0

Basic Structure of Computer Hardware and Software

ZF
0

AF
0

PF
0

CF
1

97

MEMORY MAP

80000H

11H

80020H

50H

80040H

85H

80060H

10H

80001H
80002H

2BH
3EH

80021H
80022H

00H
0AH

80041H
80042H

D0H
7AH

80061H
80062H

00H
59H

80003H

22H

80023H

6FH

80043H

EDH

80063H

42H

80004H

80H

80024H

A5H

80044H

47H

80064H

87H

80005H

67H

80025H

2FH

80045H

46H

80065H

50H

80006H

54H

80026H

17H

80046H

A7H

80066H

9FH

80007H

5FH

80027H

DAH

80047H

7EH

80067H

5AH

80008H

0EH

80028H

08H

80048H

96H

80068H

C0H

80009H

0FH

80029H

0BH

80049H

F2H

80069H

97H

8000AH

F4H

8002AH

2EH

8004AH

BCH

8006AH

AEH

8000BH

6BH

8002BH

CFH

8004BH

52H

8006BH

7CH

8000CH

4CH

8002CH

25H

8004CH

8BH

8006CH

1AH

8000DH

75H

8002DH

D7H

8004DH

F9H

8006DH

84H

8000EH

AAH

8002EH

39H

8004EH

53H

8006EH

2EF

8000FH

EFH

8002FH

56H

8004FH

BBH

8006FH

9EH

80010H

FDH

80030H

20H

80050H

31H

80070H

B9H

80011H

3DH

80031H

DFH

80051H

1FH

80071H

C2H

80012H

4FH

80032H

8FH

80052H

F7H

80072H

2EH

80013H

08H

80033H

44H

80053H

FFH

80073H

2DH

80014H

9AH

80034H

69H

80054H

13H

80074H

51H

80015H

49H

80035H

F6H

80055H

B1H

80075H

ADH

80016H

5DH

80036H

29H

80056H

CCH

80076H

36H

80017H

33H

80037H

5BH

80057H

16H

80077H

69H

80018H

CDH

80038H

DDH

80058H

26H

80078H

00H

80019H

F1H

80039H

ACH

80059H

92H

80079H

F9H

8001AH

0AH

8003AH

72H

8005AH

7BH

8007AH

1DH

8001BH

ABH

8003BH

F6H

8005BH

BFH

8007BH

FEH

8001CH

07H

8003CH

91H

8005CH

C7H

8007CH

61H

8001DH

62H

8003DH

20H

8005DH

B2H

8007DH

A9H

8001EH

19H

8003EH

82H

8005EH

39H

8007EH

DEH

8001FH

9EH

8003FH

DCH

8005FH

BDH

8007FH

4DH

Basic Structure of Computer Hardware and Software

98

LOGIC INSTRUCTIONS

Logic instructions include the logic operations AND,


OR, XOR, and NOT. Also included in this group is
the TEST instruction. The TEST instruction is
somewhat similar to the CMP instruction where the
flags are modified but the operands are not altered.

The AND Instruction


The AND (Logical AND) instruction logically ANDs
the source and the destination operands and stores the
result in the destination operand.

Format:

AND D, S

Action:

Destination
register
register
MM
register
MM

Source
register
MM
register
immediate
immediate

Basic Structure of Computer Hardware and Software

[D] [S]

Example
AND BX, CX
AND DX, [BP + SI]
AND BETA, CX
AND BX, 0015H
AND byte ptr BETA, 12H

99

Pointers:

1.

The AND instruction does not allow both source


and destination operands to be memory locations
(no memory to memory AND). Therefore, the
instruction AND SET, FILE is invalid.

2.

Both source and destination operands should be


of the same data size. The instruction AND AH,
BX is therefore invalid.

3.

The destination operand cannot be immediate


data. Therefore, the instruction AND 1800H, CX
is invalid.

4.

CF and OF are always 0 after execution while AF


is undefined.

5.

As with the MOV instruction, if the destination


operand is a memory location and the source
operand is immediate data, the prefix byte ptr or
word ptr should appear after the AND instruction
to denote the data size of the immediate operand.

Basic Structure of Computer Hardware and Software

100

6.

The AND instruction can be used to clear out or


zero out certain bits in a byte or word. In order
to do this, simply logically AND a bit mask
pattern and the byte or word concerned. A bit
mask pattern contains a pattern of 1s and 0s. A
0 in a bit position will cause that bit position to
be zeroed out, while a 1 in a bit position will not
change the value.

Example:
MOV AL, 05H
MOV BL, FEH
AND AL, BL

(mask)

AL = 0 0 0 0 0 1 0 1
BL = 1 1 1 1 1 1 1 0
AL = 0 0 0 0 0 1 0 0

bit 0 is zeroed out, the rest of the


bits remain the same.
Flags:
CF, OF, PF, ZF, SF, are all equal to 0.
AF is undefined.

Basic Structure of Computer Hardware and Software

101

The OR Instruction
The OR (Logical OR) instruction logically ORs the
source and the destination operands and stores the
result in the destination operand.
Format:
Action:
Destination
register
register
MM
register
MM

OR D, S
D
[D] + [S]
Source
register
MM
register
immediate
immediate

Example
OR BX, CX
OR DX, [BP + SI]
OR BETA, CX
OR BX, 0015H
OR byte ptr BETA, 12H

Pointers:
1.

2.

3.

4.

The OR instruction does not allow both source


and destination operands to be memory locations
(no memory to memory OR). OR SET, FILE is
therefore invalid.
Both source and destination operands should be
of the same data size. Therefore, the instruction
OR AH, BX is invalid.
The destination operand cannot be immediate
data. Thus, the instruction OR 1800H, CX is
invalid.
CF and OF are always 0 after execution while AF
is undefined.

Basic Structure of Computer Hardware and Software

102

5.

6.

As with the MOV instruction, if the destination


operand is a memory location and the source
operand is immediate data, the prefix byte ptr or
word ptr should appear after the OR instruction
to denote the data size of the immediate operand.
The OR instruction can be used to set a certain
bit to 1 in a byte or word. In order to do this,
simply logically OR a bit mask pattern and the
byte or word concerned. A bit mask pattern
contains a pattern of 1s and 0s. A 1 in a bit
position will cause that bit position to be set to 1,
while a 0 in a bit position will not change the
value.
Example:
MOV CL, 05H
MOV DL, 80H
OR CL, DL

(mask)

CL = 0 0 0 0 0 1 0 1
DL = 1 0 0 0 0 0 0 0
CL = 1 0 0 0 0 1 0 1
bit 7 is set to 1, the rest of the bits
remain the same.
Flags:
CF, OF , PF, and ZF are all equal to 0.
SF = 1 while AF is undefined.

Basic Structure of Computer Hardware and Software

103

The XOR Instruction


The XOR (Logical XOR) instruction logically XORs
the source and the destination operands and stores the
result in the destination operand.
Format:

XOR D, S

Action:

Destination
register
register
MM
register
MM

Source
register
MM
register
immediate
immediate

[D] [S]

Example
XOR BX, CX
XOR DX, [BP + SI]
XOR BETA, CX
XOR BX, 0015H
XOR byte ptr BETA, 12H

Pointers:
1.

The XOR instruction does not allow both source


and destination operands to be memory locations
(no memory to memory XOR). XOR SET,
FILE is therefore invalid.

2.

Both source and destination operands should be


of the same data size. The instruction XOR AH,
BX is invalid.

Basic Structure of Computer Hardware and Software

104

3.

The destination operand cannot be immediate


data. Thus, the instruction XOR 1800H, CX is
invalid.

4.

CF and OF are always 0 after execution while AF


is undefined.

5.

As with the MOV instruction, if the destination


operand is a memory location and the source
operand is immediate data, the prefix byte ptr or
word ptr should appear after the XOR instruction
to denote the data size of the immediate operand.

6.

It is faster for the 8086/8088 to initialize a


register to zero using the XOR instruction rather
than the MOV instruction. Since any value
XORed to itself to zero, XOR AL, AL is faster
to execute than MOV AL, 00H.

Basic Structure of Computer Hardware and Software

105

The NOT Instruction


The NOT (Logical NOT) instruction performs a 1s
complement on the operand.

Format:

NOT D

Action:

[D]

Destination
Example
register
NOT AX
MM
NOT byte ptr BETA

Pointers:
1.

The destination operand cannot be immediate


data. Thus, the instruction NOT 1800H is
invalid.

2.

Flags are not affected.

3.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the NOT instruction to denote the data size of the
destination operand.

Basic Structure of Computer Hardware and Software

106

The TEST Instruction


The TEST instruction logically ANDs the source and
the destination operands. The result is discarded but
the values of the status flags are updated.
Format:

TEST D, S

Action:

[D] [S]

Pointers:
1.

The TEST instruction does not allow both source


and destination operands to be memory locations
(no memory to memory AND). Therefore, the
instruction TEST SET, FILE is invalid.

2.

Both source and destination operands should be


of the same data size. The instruction TEST AH,
BX is therefore invalid.

3.

CF and OF are always 0 after execution while AF


is undefined.

4.

As with the MOV instruction, if the destination


operand is a memory location and the source
operand is immediate data, the prefix byte ptr or
word ptr should appear after the TEST
instruction to denote the data size of the
immediate operand.

Basic Structure of Computer Hardware and Software

107

SHIFT INSTRUCTIONS

Shift instructions are instructions that also perform bit


manipulation.

Shift Instructions can be classified as either logical


shift or arithmetic shift.

Shift instructions can also be classified by the


direction of the shift (i.e., shift to the left or shift to
the right).

Thus there are four types of shift instructions: shift


logical left (SHL), shift logical right (SHR), shift
arithmetic left (SAL), and shift arithmetic right
(SAR).

Logical shifts are used mostly to isolate bits in bytes


or words, while arithmetic shifts are used mostly to
multiply and divide binary numbers by powers of two.

Basic Structure of Computer Hardware and Software

108

The SHL/SAL Instructions


SHL (Shift Logical Left) and SAL (Shift Arithmetic
Left) are two different mnemonics but perform the
same operation. Both instructions shift to the left the
destination operand by the number of bits specified in
the count operand. As bits are shifted, zeroes are
shifted in on the right.
Format:

SAL D, Count or SHL D, Count

Action:

0
CF

Destination
register
MM
register
MM

Basic Structure of Computer Hardware and Software

Operand

Example
SHL AL, CL
SHL byte ptr BETA, CL
SHL AL, 1
SHL byte ptr BETA, 1

109

Pointers:
1.

The number of bits to be shifted can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be shifted.

2.

CF always contains the last bit shifted out of the


destination operand.

3.

OF is undefined if more than 1 bit is shifted. If


only 1 bit is shifted, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.

4.

AF is undefined after execution.

5.

SAL/SHL can be used to multiply by powers of


two (i.e., D * 2CL). For example, if two bits are
shifted to the left, the value of the destination
operand is multiplied by 4 (22).

6.

For an 8-bit operand, when shifting it to the left 8


times or more, the destination operand will result
to 0. For a 16-bit operand, when shifting it to the
left 16 times or more, the destination operand
will result to 0.

Basic Structure of Computer Hardware and Software

110

7.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the SAL/SHL instruction to denote the data size
of the destination operand.

Examples:
MOV AL, 04H
SHL AL, 1
After execution, AL = 08H. The flags will
be:
SF = 0, ZF = 0, PF = 0, CF = 0, OF = 0
AF = undefined

MOV AL, 02H


MOV CL, 03H
SHL AL, CL
After execution, AL = 10H. The flags will
be:
SF = 0, ZF = 0, PF = 0, CF = 0,
OF = undefined
AF = undefined

Basic Structure of Computer Hardware and Software

111

The SHR Instruction


The SHR (Shift Logical Right) instruction shifts to
the right the destination operand by the number of bits
specified in the count operand. As the bits are being
shifted, zeros are shifted in on the left.
Format:

SHR D, Count

Action:

0
Operand

Destination
register
MM
register
MM

CF

Example
SHR AL, CL
SHR byte ptr BETA, CL
SHR AL, 1
SHR byte ptr BETA, 1

Pointers:
1.

The number of bits to be shifted can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be shifted.

Basic Structure of Computer Hardware and Software

112

2.

CF always contains the last bit shifted out of the


destination operand.

3.

OF is undefined if more than 1 bit is shifted. If


only 1 bit is shifted, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.

4.

AF is undefined after execution.

5.

SHR can be used to divide (unsigned division) by


powers of two (i.e. D / 2CL). For example, if two
bits are shifted to the right, the value of the
destination operand is divided by 4 (22). The
result of the division is truncated.

6.

For an 8-bit operand, when shifting it to the right


8 times or more, the destination operand will
result to 0. For a 16-bit operand, when shifting it
to the right 16 times or more, the destination
operand will result to 0.

7.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the SHR instruction to denote the data size of the
destination operand.

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113

Examples:

MOV AL, 05H


SHR AL, 1
After execution, AL = 02H. The flags will
be:
SF = 0, ZF = 0, PF = 0, CF = 1, OF = 0
AF = undefined

MOV AL, 20H


MOV CL, 03H
SHR AL, CL
After execution, AL = 04H. The flags will
be:
SF = 0, ZF = 0, PF = 0, CF = 0,
OF = undefined
AF = undefined

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114

The SAR Instruction


The SAR (Shift Arithmetic Right) instruction shifts to
the right the destination operand by the number of bits
specified in the count operand. As the bits are being
shifted, the most significant bit is shifted in to the left,
preserving the sign bit.

Format:

SAR D, Count

Action:

Operand

Destination
register
MM
register
MM

Basic Structure of Computer Hardware and Software

CF

Example
SAR AL, CL
SAR byte ptr BETA, CL
SAR AL, 1
SAR byte ptr BETA, 1

115

Pointers:
1.

The number of bits to be shifted can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be shifted.

2.

CF always contains the last bit shifted out of the


destination operand.

3.

OF is undefined if more than 1 bit is shifted. If


only 1 bit is shifted, OF is always cleared to 0.
This is because the sign bit is replicated during
the shift.

4.

AF is undefined after execution.

5.

SAR can be used to divide (signed division) by


powers of two (i.e., D / 2CL). For example, if two
bits are shifted to the right, the value of the
destination operand is divided by 4 (22). The
result of the division is rounded down (i.e., 5/2 =
2; -5/2 = -3).

6.

For an 8-bit operand, when shifting it to the right


8 times or more, the destination operand will
result to the sign extension of the operand. For a
16-bit operand, when shifting it to the right 16
times or more, the destination operand will result
to the sign extension of the operand.

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116

7.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the SAR instruction to denote the data size of the
destination operand.

Examples:
MOV AL, FCH
SAR AL, 1
After execution, AL = FEH. The flags will
be:
SF = 1, ZF = 0, PF = 0, CF = 0, OF = 0
AF = undefined

MOV AL, 19H


MOV CL, 03H
SAR AL, CL
After execution, AL = 03H. The flags will
be:
SF = 0, ZF = 0, PF = 1, CF = 0,
OF = undefined; AF = undefined

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117

ROTATE INSTRUCTIONS

Rotate instructions rotate bits out into the other end of


the operand.

Rotate instructions can be classified by the direction


of the rotation (rotate to the left or rotate to the right).
They can also be classified as to whether the carry flag
is part of the rotate operation or not.

Rotate instructions can be used to isolate bits in bytes


or words.

The ROL Instruction


The ROL (Rotate Left) instruction rotates to the left
the destination operand by the number of bits
specified in the count operand.
Format:

ROL D, Count

Action:

CF

Basic Structure of Computer Hardware and Software

Operand

118

Destination
register
MM
register
MM

Example
ROL AL, CL
ROL byte ptr BETA, CL
ROL AL, 1
ROL byte ptr BETA, 1

Pointers:
1.

The number of bits to be rotated can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be rotated.

2.

CF always contains the last bit rotated out of the


destination operand.

3.

OF is undefined if more than 1 bit is rotated. If


only 1 bit is rotated, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.

4.

Only CF and OF are affected, the rest are not.

5.

For an 8-bit operand, when rotating it to the left 8


times, the value of the destination operand will
remain the same. For a 16-bit operand, when
rotating it to the left 16 times, the destination
operand will remain the same.

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119

6.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the ROL instruction to denote the data size of the
destination operand.

Examples:
MOV AL, 04H
ROL AL, 1
After execution, AL = 08H. The flags will
be:
CF = 0, OF = 0

MOV AL, 55H


MOV CL, 03H
ROL AL, CL
After execution, AL = AAH. The flags will
be:
CF = 0; OF = undefined

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120

The ROR Instruction


The ROR (Rotate Right) instruction rotates to the
right the destination operand by the number of bits
specified in the count operand.
Format:

ROR D, Count

Action:

Operand

Destination
register
MM
register
MM

CF

Example
ROR AL, CL
ROR byte ptr BETA, CL
ROR AL, 1
ROR byte ptr BETA, 1

Pointers:
1.

2.

The number of bits to be rotated can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be rotated.
CF always contains the last bit rotated out of the
destination operand.

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121

3.

4.
5.

6.

OF is undefined if more than 1 bit is rotated. If


only 1 bit is rotated, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.
Only CF and OF are affected, the rest are not.
For an 8-bit operand, when rotating it to the right
8 times, the value of the destination operand will
remain the same. For a 16-bit operand, when
rotating it to the right 16 times, the destination
operand will remain the same.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the ROR instruction to denote the data size of the
destination operand.
Examples:
MOV AL, 04H
ROR AL, 1
After execution, AL = 02H. The flags will
be:
CF = 0, OF = 0

MOV AL, 55H


MOV CL, 03H
ROR AL, CL
After execution, AL = AAH. The flags will
be:
CF = 0; OF = undefined
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122

The RCL Instruction


The RCL (Rotate Left through Carry) instruction
rotates to the left the destination operand by the
number of bits specified in the count operand. The
carry flag is treated as part of the rotate.
Format:
Action:

RCL D, Count

CF

Destination
register
MM
register
MM

Operand

Example
RCL AL, CL
RCL byte ptr BETA, CL
RCL AL, 1
RCL byte ptr BETA, 1

Pointers:
1.

2.

The number of bits to be rotated can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be rotated.
CF is part of the rotate operation. This means
that the CF is rotated into the LSB of the operand
and the MSB of the operand goes to CF.

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123

3.

4.
5.

6.

OF is undefined if more than 1 bit is rotated. If


only 1 bit is rotated, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.
Only CF and OF are affected, the rest are not.
For an 8-bit operand, when rotating it to the left 9
times, the value of the destination operand will
remain the same. For a 16-bit operand, when
rotating it to the left 17 times, the destination
operand will remain the same.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the RCL instruction to denote the data size of the
destination operand.
Examples:
MOV AL, 04H
RCL AL, 1
Assume that CF = 1. After execution, AL =
09H. The flags will be:
CF = 0, OF = 0

MOV AL, 55H


MOV CL, 03H
RCL AL, CL
Assume CF = 0. After execution, AL =
A9H. The flags will be:
CF = 0; OF = undefined

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124

The RCR Instruction


The RCR (Rotate Right through Carry) instruction
rotates to the right the destination operand by the
number of bits specified in the count operand. The
carry flag is treated as part of the rotate.
Format:
Action:

RCR D, Count

Operand

Destination
register
MM
register
MM

CF

Example
RCR AL, CL
RCR byte ptr BETA, CL
RCR AL, 1
RCR byte ptr BETA, 1

Pointers:
1.

2.

The number of bits to be rotated can be specified


as a constant of 1 (only a constant value of 1 is
allowed) or in register CL. Register CL is used if
more than 1 bit is to be rotated.
CF is part of the rotate operation. This means
that the CF is rotated into the MSB of the
operand and the LSB of the operand goes to CF.

Basic Structure of Computer Hardware and Software

125

3.

4.
5.

6.

OF is undefined if more than 1 bit is rotated. If


only 1 bit is rotated, OF is cleared to 0 if the sign
bit retains its original value; otherwise, it is set to
1.
Only CF and OF are affected, the rest are not.
For an 8-bit operand, when rotating it to the right
9 times, the value of the destination operand will
remain the same. For a 16-bit operand, when
rotating it to the right 17 times, the destination
operand will remain the same.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the RCL instruction to denote the data size of the
destination operand.
Examples:
MOV AL, 04H
RCR AL, 1
Assume that CF = 1. After execution, AL =
82H. The flags will be:
CF = 0, OF = 1

MOV AL, 55H


MOV CL, 03H
RCR AL, CL
Assume CF = 0. After execution, AL =
4AH. The flags will be:
CF = 1; OF = undefined
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126

FLAG CONTROL INSTRUCTIONS

The 8086/8088 provides a group of instructions that


directly affects the state of the flags.

The LAHF Instruction


The LAHF (Load AH from flags) instruction copies
the SF, ZF, AF, PF, and CF into bits b 7, b6, b4, b2, and
b0 respectively of register AH.
Format:

LAHF

Action:

AH

SF ZF x AF x PF x CF

Pointers:
1.

Bits b5, b3, and b1 of register AH are undefined


after execution.
Example:
Assume the value of the following flags:
SF = 1, ZF = 0, AF = 1, PF = 0, CF = 1
After executing the LAHF instruction, AH
will have the value of 10x1x0x1. Assuming
the undefined bits have a value of 0, then
AH is equal to 91H.

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127

The SAHF Instruction


The SAHF (Store AH into flags) instruction transfers
bits b7, b6, b4, b2, and b0 from register AH into SF, ZF,
AF, PF, and CF, respectively.

Format:

SAHF

Action:

SF ZF x AF x PF x CF

AH

Example:
MOV AH, 25H
SAHF

After executing the SAHF instruction, the


value of the flags will be:

0 0 1 0 0 1 0 1

SF ZF

Basic Structure of Computer Hardware and Software

AF

PF

CF

128

The CLC Instruction


The CLC (Clear Carry Flag) instruction clears the
carry flag.

Format:

CLC

Action:

CF

The STC Instruction


The CLC (Set Carry Flag) instruction sets the carry
flag to 1.

Format:

STC

Action:

CF

The CMC Instruction


The CMC (Complement Carry Flag) instruction
complements the carry flag.
Format:

CMC

Action:

CF

Basic Structure of Computer Hardware and Software

[CF]

129

The PUSHF Instruction

The PUSHF (Push Status Register onto Stack)


instruction pushes the status register onto the stack.
PUSHF decrements SP by 2 and then moves the status
register to the top of the stack.

Format:

PUSHF

Action:

SP

SP - 2

SP

[status register]

The POPF Instruction

The POPF (Pop Flags off the Stack) instruction


transfers the word pointed to by SP to the status
register, thereby altering the value of the flags.

Format:

POPF

Action:

status register
SP

Basic Structure of Computer Hardware and Software

[SP]
SP + 2
130

CONTROL TRANSFER INSTRUCTIONS

The code segment and IP keep track of the next


instruction to be executed. This means that programs
are executed sequentially.

However, there are times when there is a need to alter


the flow of program execution such as program loops
or function calls.

The instructions that can alter the flow of a program


are iteration control instructions, conditional
transfers, unconditional transfers, and subroutines.

The JMP Instruction


The JMP (Unconditional Jump) instruction
unconditionally transfers control to the target location.
Format:

JMP operand

Action:

Jump is initiated to the address


specified by the operand.

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131

Operand
Short-label
Near-label
Far-label
Regptr16
Memptr16
Memptr32

Example
JMP short L1
JMP L1
JMP far L1
JMP DX
JMP [BX]
JMP far [BX]

Pointers:
1.

The JMP Instruction can either be Intrasegment


Jump or Intersegment Jump. In intrasegment
jump, the jump is limited within the code
segment only. Only the value of IP is modified.
For intersegment jump, the jump is allowed to
any other code segment. This means both CS
and IP are modified.

2.

Operands may be labels (representing the address


of the target location).

3.

Operands could either be relative or absolute. In


relative operand, the operand is a signed
displacement (or offset) from the JMP instruction
to the target location. This means that the
address of the target location is obtained by
adding the displacement to IP. In the absolute
operand, the operand itself is the address of the
target location.

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132

4.

Intrasegment jumps support both absolute and


relative operands, while intersegment jumps
support absolute operands only.

5.

Relative operands for intrasegment jump could


either be short-label or near-label. For shortlabel, program transfers control within -128 to
127 bytes from the location of the jump
instruction (the displacement operand is only 1
byte). The prefix short signifies a short-label
jump. For near-label, program transfers control
within -32,768 to 32,767 bytes from the location
of the jump instruction (the displacement operand
has 2 bytes).

Summary:
JMP

Intrasegment Jump

Relative

Absolute

short-label
near-label

Basic Structure of Computer Hardware and Software

RegPtr16
MemPtr16

Intersegment Jump

Absolute
far-label
MemPtr32

133

Examples:
1.

Short-label
MOV AX, 0001H
JMP short L1
MOV BX, 0002H
L1: MOV BX, 0001H
After execution, BX will contain 0001H. In
terms of execution, both short-label jump
and near-label jump are the same. The only
difference is the distance of the jump. Near
label jump could jump farther than shortlabel jump. Note that the jump could either
be a forward jump or a backward jump.

2.

Far-Label
MOV AX, 0001H
JMP far L1
MOV BX, 0002H
MOV BX, 0001H
.
.
.
L1: MOV BX, 0003H
In this example, label L1 is assumed to be
on another code segment. The prefix far
signifies an intersegment jump.

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134

3.

RegPtr16
MOV BX, 0000H
JMP BX

In this example, the JMP instruction will


jump to absolute address CS:0000. This
address is pointed by register BX. Since
this is an intrasegment jump, BX contains
the new IP value.

4.

MemPtr16
MOV BX, 0000H
JMP [BX]
DS :0001H

01H

DS :0000H

00H

In this example, the JMP instruction will


jump to absolute address CS:0100. This
address is located in the memory pointed by
register BX. Since this is an intrasegment
jump, the memory contains the new IP
value.

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135

5.

MemPtr32

MOV BX, 0000H


JMP far [BX]

DS :0003H

01H

DS :0002H

00H

DS :0001H

02H

DS :0000H

00H

In this example, the JMP instruction will


jump to absolute address 0200:0100. The
address is located in the memory pointed by
register BX. Since the JMP instruction is an
intersegment jump, that memory contains
both the new CS and IP values.

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136

The Jcc Instructions


The Jcc (Conditional Jump) instructions are jumps
that may or may not transfer control depending on the
state of the status flags at the time the instruction is
executed.
Format:

Jcc operand

Action:

If the specified condition cc is


true, it will jump to the address
specified
in
the
operand;
otherwise the next instruction is
executed.

Comparing Unsigned Numbers


Mnemonic
JA/JNBE
JAE/JNB
JB/JNA
JBE/JNA

Jump if
above/not below nor equal
above or equal/not below
below/not above nor equal
below or equal/not above

Condition
(CF or ZF) = 0
CF = 0
CF = 1
(CF or ZF) = 1

Comparing Signed Numbers


Mnemonic
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG

Jump if
greater than/not less than or equal
greater than or equal/not less than
less than/not greater than or equal
less than or equal/not greater than

Basic Structure of Computer Hardware and Software

Condition
ZF=0 or (SF=OF)
SF = OF
SF OF
ZF=1 or (SFOF)
137

Test Flags
Mnemonic
JE/JZ
JNE/JNZ
JC
JNC
JS
JNS
JP/JPE
JNP/JPO
JO
JNO

Jump if
equal to/zero
not equal to/not zero
carry
not carry
sign
not sign
parity/parity even
no parity/parity odd
overflow
no overflow

Condition
ZF = 1
ZF = 0
CF = 1
CF = 0
SF = 1
SF = 0
PF = 1
PF = 0
OF = 1
OF = 0

Pointers:
1.

Only the short-label operand is supported by the


conditional jump instructions. This means that
the program could only transfer program control
within -128 to +127 bytes from the location of
the conditional jump instruction.

2.

Conditional jump should be placed immediately


after an instruction that will modify the status
flags (i.e., CMP, INC, DEC, etc.).

3.

To circumvent the limitation of the short label, an


unconditional jump is used around the
conditional jump.

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138

Examples:
1.

MOV AL, A5H


MOV BL, 73H
CMP AL, BL
JA L1
The JA L1 instruction is read as if AL is
higher than BL, then jump to L1. The
program will jump to L1 since the value of
AL (A5H or 165 in decimal) is higher than
the value of BL (73H or 115 in decimal).
Remember that the values are treated as
unsigned numbers.

2.

MOV AL, A5H


MOV BL, 73H
CMP AL, BL
JG L1
The JG L1 instruction is read as if AL is
greater than BL, then jump to L1. The
program will not jump to L1 since the value
of AL (A5H or -91 in decimal) is not greater
than the value of BL (73H or +115 in
decimal). Remember that the values are
treated as signed numbers.

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139

3.

MOV AL, 00H


MOV CL, 03H
AGAIN: ADD AL, 02H
DEC CL
JNZ AGAIN
When the program is executed, the value of
AL will become equal to 02H. Then the
value of CL will be decremented by 1. Its
value will therefore be equal to 02H. The
JNZ AGAIN instruction will check the value
of CL if it is zero or not (by checking the
zero flag). If it is not equal to 0, the
program will jump back to AGAIN. Since
CL is not zero, the program will go back to
the ADD AL, 02H instruction again.
The value of AL will now become equal to
04H. Then the value of CL will again be
decremented by 1. Its value will therefore
be equal to 01H. Since it is still not equal to
zero, the program will go back to the ADD
AL, 02H instruction again.
The value of AL will now become equal to
06H. Then the value of CL will again be
decremented by 1. Its value will therefore
be equal to 00H. Since it is now equal to
zero, the program will not jump. Instead it
will proceed to the next instruction after the
JNZ AGAIN instruction.

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140

4.

MOV AL, 7FH


MOV BL, 75H
ADD AL, BL
JO NEXT

The JO NEXT instruction will cause the


program to jump to NEXT if there was an
overflow condition. After executing the
ADD AL, BL instruction, the overflow flag
will become equal to 1 indicating that there
was an overflow. Therefore, the program
will jump to NEXT.

5.

MOV AL, 01H


DEC AL
JG L1
When a conditional jump is placed after an
instruction having one operand, the
comparison is between the operand and 0.
In this example, the JG L1 instruction is
read as decrement the value of AL by one,
if AL is greater than 0, then jump to L1.
After decrementing AL, it now has a value
of 0. Therefore, the program will not jump
to L1 since 0 is not greater than 0.

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141

6.

Circumventing the limitation of the shortlabel:

MOV BX, 0002H


MOV CX, 0002H
CMP BX, CX
JE L1
:
:
:
L1:
:
:

If there are 1,000 lines in between the JE


instruction and L1, the assembler will issue
an error message since the operand is only a
short-label.

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142

To solve the problem, use an unconditional


jump and reverse the test logic:

MOV BX, 0002H


MOV CX, 0002H
CMP BX, CX
JNE SKIPJUMP
JMP L1
SKIPJUMP:
:
:
:
:
L1:
:
:

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143

ASSEMBLY LANGUAGE
PROGRAMMING TECHNIQUES
PROGRAM 1

Write an assembly language program that will clear the


contents of a block of memory. The starting address of the
block has an offset of ALPHA and the ending address of
the block has an offset of OMEGA. These addresses have
random contents. Clearing these locations means that all
the memory locations should become zeros.

Program:

LEA SI, ALPHA


LEA DI, OMEGA
AGAIN: MOV byte ptr [SI], 00H
INC SI
CMP SI, DI
JBE AGAIN

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144

PROGRAM 2

Write an assembly language program that will clear 100


memory locations starting at offset ALPHA.

Program:

LEA SI, ALPHA


MOV CL, 64H

AGAIN: MOV byte ptr [SI], 00H


INC SI
DEC CL
JNZ AGAIN

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145

PROGRAM 3

Write an assembly language program that will move the


contents of memory block 1 (C100H to C120H) to memory
block 2 (C150H to C170H). This means that the contents
of C100H will move to location C150H and overwrite them
and so on. After executing the program, the contents of
two blocks should be the same.

Program:

MOV SI, C100H


MOV DI, C150H

AGAIN: MOV AL, [SI]


MOV [DI], AL
INC SI
INC DI
CMP SI, C121H
JNE AGAIN

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146

PROGRAM 4

Write an assembly language program that checks if ASCII


A (41H) exists in a list. The list is stored in memory
starting at memory location ALPHA. The list is terminated
with a sentinel number FFH (note that the sentinel is not
part of the list). If ASCII A is not found in the list, then
initialize memory location STAT with 00H, else initialize it
with FFH.

Solution:
MOV byte ptr STAT, 00H
LEA SI, ALPHA
L1:

CMP byte ptr [SI], FFH


JE END
CMP byte ptr [SI], 41H
JE FOUND
INC SI
JMP L1

FOUND: MOV byte ptr STAT, FFH


END:

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147

PROGRAM 5

Write an assembly language program that checks if all 100


elements in the list are ASCII A (41H). The list is stored
at memory location ALPHA. If all 100 elements in the list
are ASCII A, then initialize memory location STAT with
00H, else initialize it with FFH.

MOV CL, 64H


LEA SI, ALPHA
L1:

MOV AL, [SI]


CMP AL, 41H
JNE L2
INC SI
DEC CL
JNZ L1
MOV byte ptr STAT, 00H

JMP END
L2:

MOV byte ptr STAT, FFH

END:

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148

PROGRAM 6
Write an assembly language program that counts the number of odd and even numbers in a list
that is stored in memory starting at memory location ALPHA. The list is terminated with a sentinel
number FFH (note that the sentinel is not part of the list). Place the odd number count in memory
location ODD and the even number count in memory location EVEN. Assume that there is a possibility
of an empty list.

Solution:
MOV byte ptr ODD, 00H
MOV byte ptr EVEN, 00H
LEA SI, ALPHA
L1:

MOV AL, [SI]


CMP AL, FFH
JE END
SHR AL, 1
JC L2
INC byte ptr EVEN
INC SI
JMP L1

L2:

INC byte ptr ODD


INC SI
JMP L1

END:

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PROGRAM 7
Write an assembly language program that counts the
number of positive and negative numbers in the list. The
list contains byte-size signed numbers and is stored at
memory location ALPHA. The list is terminated with a
sentinel number FFH (note that the sentinel is part of the
list). Place the positive number count in memory location
POS and the negative number count in memory location
NEGA.
LEA SI, ALPHA
MOV byte ptr POS, 00H
MOV byte ptr NEGA, 00H
L1:

MOV AL, [SI]

CMP AL, FFH


JE END
SHL AL, 1
JC L2
INC byte ptr POS
INC SI
JMP L1
L2:

INC byte ptr NEGA


INC SI
JMP L1

END:

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150

PROGRAM 8
Write an assembly language instruction that gets the
highest and the lowest numbers in a list. The list contains
byte-size signed numbers and is stored at memory location
ALPHA. The list is terminated with a sentinel number
FFH (note that the sentinel is not part of the list). Place the
highest number in memory location HIGH and the lowest
number in memory location LOW. Assume that there is at
least one element in the list.
Solution:

L2:

L1:

LEA SI, ALPHA


MOV AL, [SI]
MOV HIGH, AL
MOV LOW, AL
INC SI
MOV AL, [SI]
CMP AL, FFH
JE END
CMP AL, HIGH
JLE L1
MOV HIGH, AL
JMP L2
CMP AL, LOW
JGE L2
MOV LOW, AL
JMP L2

END:

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PROGRAM 9
Write an assembly language program that adds the elements
in a list. The list contains byte-size signed numbers and is
stored at memory location ALPHA. The number of
elements in the list is stored at byte memory location
ALPHA. The number of elements in the list is stored at
byte memory location COUNT. Place the result in memory
location SUM. Assume that there is at least one element in
the list.

Solution:

LEA SI, ALPHA


MOV CL, COUNT
MOV byte ptr SUM, 00H

L1:

MOV AL, [SI]


ADD SUM, AL
INC SI
DEC CL
JNZ L1

END:

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152

PROGRAM 10
Write an assembly language program that reads a byte from
memory location INPUT. The program should then
examine this byte to determine which bit is a logic 1. If the
first bit (b0) is a logic 1, then the program should load 01H
to memory location OUTPUT. If the second bit (b1) is a
logic 1, then the program should load 02H to memory
location OUTPUT. And so on and so forth. If the byte is
equal to 00H (there is no bit equal to logic 1), then the
program should terminate. Assume that only one of the
bits (b0 to b7) can be equal to 1.

Solution:

MOV AL, INPUT


CMP AL, 00H
JE END
SHR AL, 1
JC FIRST
SHR AL, 1
JC SECOND
SHR AL, 1
JC THIRD
SHR AL, 1
JC FOURTH

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153

SHR AL, 1
JC FIFTH
SHR AL, 1
JC SIXTH
SHR AL, 1
JC SEVENTH
MOV OUTPUT, 08H
JMP END
FIRST:
SECOND:
THIRD:
FOURTH:
FIFTH:
SIXTH:
SEVENTH:

MOV OUTPUT, 01H


JMP END
MOV OUTPUT, 02H
JMP END
MOV OUTPUT, 03H
JMP END
MOV OUTPUT, 04H
JMP END
MOV OUTPUT, 05H
JMP END
MOV OUTPUT, 06H
JMP END
MOV OUTPUT, 07H

END:

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PROGRAM 11

Write an assembly language program that adds two 32-bit


numbers and stores the result in memory location
GAMMA. The first 32-bit number is located at memory
location ALPHA, while the second 32-bit number is
located at memory location BETA.

ALPHA:

78H

11H

89H

56H

22H

79H

34H

EEH

23H

12H

BETA:

FFH

GAMMA:

11H

Solution:
MOV SI, 0002H
MOV AX, ALPHA
MOV BX, BETA
MOV CX, ALPHA[SI]
MOV DX, BETA[SI]
ADD AX, BX
ADC CX, DX
MOV GAMMA, AX
MOV GAMMA[SI], CX

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155

PROGRAM 12
Write an assembly language program that adds
two 64-bit numbers and stores the result at
memory location GAMMA. The first 64-bit
number is located at memory location ALPHA,
while the second 64-bit number is located at
memory location BETA.
LEA SI, ALPHA
LEA DI, BETA
LEA BX, GAMMA
MOV AX, [SI]
MOV DX, [DI]
ADD AX, DX
MOV [BX], AX

PUSHF
MOV CL, 03H
L1:

INC SI

INC DI
MOV AX, [SI]
MOV DX, [DI]
POPF
ADC AX, DX
MOV [BX], AX
PUSHF
DEC CL
JNZ L1
END:
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156

PROGRAM 13

Write an assembly language program that adds two 2-decade BCD numbers and stores the result at memory
location GAMMA. The first 2-decade BCD number is located at memory location ALPHA, while the second 2-decade BCD
number is located at memory location BETA. Assume that there would not be a carry from the least significant decimal
number to the most significant decimal number.

78H
ALPHA:

56H

99H
BETA:

11H

77H
GAMMA:

68H

Solution:
MOV SI, 0001H
MOV AL, ALPHA
MOV BL, BETA
ADD AL, BL
DAA
MOV GAMMA, AL
MOV AL, ALPHA[SI]
MOV BL, BETA[SI]
ADD AL, BL
DAA
MOV GAMMA[SI], AL

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157

OTHER 8086/8088 INSTRUCTIONS


DATA TRANSFER INSTRUCTIONS

The LDS Instruction


The LDS (Load Register and DS) instruction transfers
a 32-bit pointer from the source operand to the
destination operand and register DS.
Format:

LDS D, MEM32

Action:

D
DS

[MEM32]
[MEM32 + 2]

Pointers:

1.

LDS instruction transfers a 32-bit pointer that is


stored in memory to the 16-bit register and
register DS. This means that the source operand
should be one of the memory addressing modes.
The destination operand is composed of a 16-bit
register and register DS.

2.

The least significant word of the 32-bit pointer is


stored in the 16-bit register while the most
significant word is stored in DS.

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Example:
Assume the following:
DS = 5000H
LIST = 1800H

51804H

66H

51803H

55H

51802H

44H

51801H

33H

51800H

22H

517FFH

11H

The instruction LDS DI, LIST will transfer


the 32-bit word starting at memory location
LIST to registers DI and DS. Therefore,
after execution:
DI = 3322H
DS = 5544H

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159

The LES Instruction

The LES (Load Register and ES) instruction transfers


a 32-bit pointer from the source operand to the
destination operand and register ES.

Format:

LES D, MEM32

Action:

D
ES

[MEM32]
[MEM32 + 2]

Pointers:

1.

LES instruction transfers a 32-bit pointer that is


stored in memory to the 16-bit register and
register ES. This means that the source operand
should be one of the memory addressing modes.
The destination operand is composed of a 16-bit
register and register ES.

2.

The least significant word of the 32-bit pointer is


stored in the 16-bit register while the most
significant word is stored in ES.

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160

The XLAT Instruction

The XLAT (Translate) instruction simplifies the


implementation of the look-up table.
Format:

XLAT

Action:

AL

[DS : (BX+AL)]

Pointers:

1.

Before executing the XLAT instruction, BX


should point to the beginning of the table while
AL contains the index into the table.

2.

The programming pattern


instruction is as follows:

3.

for

the

LEA BX, ____

fill in the base


address of the
table

MOV AL, ___

fill in the index


value

XLAT

After execution, AL is replaced by the byte at the


offset of the translation table.

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161

Example:
Assume the following:
DS

= 5000H and LIST = 1800H

51804H

66H

51803H

55H

51802H

44H

51801H

33H

51800H

22H

517FFH

11H

LEA BX, LIST


MOV AL, 02H
XLAT
The first instruction loads the effective address of
the start of the translation table (memory location
LIST) to BX. The second instruction loads the
offset (02H) to AL. By executing XLAT, register
AL will now be replaced by the data located at
memory location LIST offset by register AL.
After execution, register AL will have a value of
44H.
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162

ARITHMETIC INSTRUCTIONS

The MUL Instruction


The MUL (Multiplication) instruction performs
unsigned multiplication of the source operand and the
accumulator.
Format:

MUL S

Action:
1.

For 8-bit by 8-bit Multiplication


AX
[AL] x [S8]

2.

For 16-bit by 16-bit Multiplication


DX:AX
[AX] x [S16]

Source
register
MM

Example
MUL CX
MUL byte ptr [BX]

Pointers:
1.

If the source operand is a byte, it is multiplied


with register AL and the result is returned to
register AX.

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163

2.

3.

4.
5.

If the source operand is a word, it is multiplied


with register AX and the result is returned to
registers DX (most significant word) and AX
(least significant word).
If the upper half of the result (register AH for
byte source, register DX for word source) is zero,
CF and OF are reset; otherwise, they are set.
AF, PF, SF, and ZF are undefined after
execution.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the MUL instruction to denote the data size of the
destination operand.

Examples:
1.

MOV AX, 0002H


MOV BX, 0003H
MUL BL
After execution of the program:
AX = 0006H, CF = 0, OF = 0

2.

MOV AX, 1234H


MOV BX, 1800H
MUL BX
After execution of the program:
DX = 01B4H, AX = E000H
CF = 1, OF = 1

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164

The IMUL Instruction


The IMUL (Signed Multiplication) instruction
performs signed multiplication of the source operand
and the accumulator.
Format:

IMUL S

Action:
1.

For 8-bit by 8-bit Multiplication


AX
[AL] x [S8]

2.

For 16-bit by 16-bit Multiplication


DX:AX
[AX] x [S16]

Source
register
MM

Example
IMUL CX
IMUL byte ptr [BX]

Pointers:
1.

If the source operand is a byte, it is multiplied


with register AL and the result is returned to
register AX.

2.

If the source operand is a word, it is multiplied


with register AX and the result is returned to
registers DX (most significant word) and AX
(least significant word).

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165

3.

If the upper half of the result (register AH for


byte source, register DX for word source) is the
sign extension of the lower half of the result, CF
and OF are reset; otherwise, they are set.

4.

AF, PF, SF, and ZF are undefined after


execution.

5.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the IMUL instruction to denote the data size of
the destination operand.

Examples:
1.

MOV AX, 00FEH


MOV BX, 00FEH
IMUL BL
After execution of the program:
AX = 0004H, CF = 0, OF = 0

2.

MOV AX, 1234H


MOV BX, F000H
IMUL BX
After execution of the program:
DX = FEDCH, AX = C000H
CF = 1, OF = 1

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166

The DIV Instruction


The DIV (Unsigned Division) instruction performs
unsigned division of the accumulator by the source
operand.
Format:

DIV S

Action:
1.

For 8-bit Source Operand


AL
[AX] / [S8]
AH
[AX] % [S8]

2.

For 16-bit Source Operand


AX
[DX:AX] / [S16]
DX
[DX:AX] % [S16]
Source
register
MM

Example
DIV CX
DIV byte ptr [BX]

Pointers:
1.

2.

If the source operand is a byte, AX is divided by


this byte-sized source operand, with the results
returned in AL and the remainder in AH.
If the source operand is a word, register pair
DX:AX is divided by this word-sized source
operand, with the results returned in AX and the
remainder in DX.

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167

3.

4.
5.

If the quotient exceeds the capacity of the


destination registers (i.e., FFH for byte source,
FFFFH for word source), the quotient and
remainder are undefined, and an INT 0 is
generated.
All status flags are undefined after execution.
If the destination operand is a memory location,
the prefix byte ptr or word ptr should appear after
the DIV instruction to denote the data size of the
destination operand.

Examples:
1.

MOV AX, 0005H


MOV BL, 02H
DIV BL
After execution of the program:
AX = 0102H

2.

MOV DX, 0001H


MOV AX, FFFFH
MOV BX, 0005H
DIV BX
After execution of the program:
DX = 0001H, AX = 6666H

3.

MOV DX, 0002H


MOV AX, 49F5H
MOV BX, 000AH
DIV BX
After execution of the program:
DX = 0005H, AX = 3A98H

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168

The IDIV Instruction

The IDIV (Signed Division) instruction performs


signed division of the accumulator by the source
operand.

Format:

IDIV S

Action:
1.

2.

For 8-bit Source Operand


AL

[AX] / [S8]

AH

[AX] % [S8]

For 16-bit Source Operand


AX

[DX:AX] / [S16]

DX

[DX:AX] % [S16]

Source
register
MM

Basic Structure of Computer Hardware and Software

Example
IDIV CX
IDIV byte ptr [BX]

169

Pointers:

1.

If the source operand is a byte, AX is divided by


this byte-sized source operand, with the results
returned in AL and the remainder in AH.

2.

If the source operand is a word, register pair


DX:AX is divided by this word-sized source
operand, with the results returned in AX and the
remainder in DX.

3.

If the source operand is a byte, the maximum


positive quotient is 7FH and the minimum
negative quotient is 81H. If the source operand
is a word, the maximum positive quotient is
7FFFH and the minimum negative quotient is
8001H.

4.

If the quotient exceeds the maximum (positive)


or the minimum (negative), the quotient and
remainder are undefined, and an INT 0 is
generated.

5.

All status flags are undefined after execution.

6.

The remainder has the same sign as the dividend.

7.

If the destination operand is a memory location,


the prefix byte ptr or word ptr should appear after
the DIV instruction to denote the data size of the
destination operand.

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Examples:

1.

MOV AX, FFFBH


MOV BL, 02H
IDIV BL
After execution of the program:
AX = FFFEH

2.

MOV DX, FFFFH


MOV AX, FFFEH
MOV BX, FFFEH
IDIV BX
After execution of the program:
DX = 0000H
AX = 0001H

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171

The AAM Instruction


The AAM (ASCII Adjust for Multiplication)
instruction adjusts the result of a previous
multiplication of two valid unpacked BCD.
Format:
Action:

AAM
AH
AL

AL / 0AH
AL % 0AH

Pointers:
1. The most significant nibble of an operand should
be zero. This can be compared with addition and
subtraction in which operands are viewed as
ASCII (most significant nibble is 3).
2. The result of the previous operation should be in
AX.
3. OF, CF, and AF are undefined after execution.
4. AAM should be executed immediately after a
MUL or IMUL instruction.
Example:
MOV AL, 05H
MOV BL, 03H
MUL BL
AAM
After executing the MUL instruction, AX has a
value of 000FH (equivalent to 15 in decimal).
After the AAM instruction, AX now contains the
adjusted unpacked BCD value of the previous
result (0105 is the unpacked BCD equivalent of
15).
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172

The AAD Instruction


The AAD (ASCII Adjust for Division) instruction
adjusts the result of a previous division of two valid
unpacked BCD.
Format:
Action:

AAD
AL
AH

AH * 0AH + AL
0

Pointers:
1.

2.

3.
4.

AAD should be executed before issuing the DIV


instruction when dividing two valid unpacked
BCD operands.
The instruction will adjust the operand (register
AL) as follows: the value of AH is multiplied
with 0AH and added with the value of AL. The
result is placed in AL. AH is zeroed out after
adjustment.
OF, CF, and AF are undefined after execution.
AAD works hand in hand with DIV only.

Example:
MOV AX, 0105H;
AAD
MOV BL, 02H;
DIV BL
After executing the AAD instruction, AX has a
value of 000FH (equivalent to 15 in decimal).
This is then divided by BL. AX will then contain
0107H.
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173

The CBW Instruction


The CBW (Convert Byte to Word) instruction sign
extends the byte data in AL to register AH.
Format:
Action:

CBW
AH

MSB of AL

Pointers:
1.
2.
3.

CBW works with AL only.


After execution, AH contains the sign extension
of register AL.
CBW does not affect any of the status flags.

The CWD Instruction


The CWD (Convert Word to Double Word)
instruction sign extends the word data in AX to
register DX.
Format:
Action:

CWD
DX

MSB of AX

Pointers:
1.
2.
3.

CWD works with AX only.


After execution, DX contains the sign extension
of register AX.
CWD does not affect any of the status flags.

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174

FLAG CONTROL INSTRUCTIONS

The CLI Instruction

The CLI (Clear Interrupt Flag) instruction clears the


interrupt flag, thereby disabling interrupt request. The
8086/8088 will therefore not recognize any external
interrupt request with the exception of the nonmaskable interrupt.

Format:

CLI

Action:

IF

The STI Instruction

The STI (Set Interrupt Flag) instruction sets the


interrupt flag to 1, thereby enabling the 8086/8088 to
recognize any interrupt request.

Format:

STI

Action:

IF

Basic Structure of Computer Hardware and Software

1
175

The CLD Instruction

The CLD (Clear Direction Flag) instruction clears the


direction flag, thereby causing the string instruction to
auto-increment the index registers (SI or DI).

Format:

CLD

Action:

DF

The STD Instruction

The STD (Set Direction Flag) instruction sets the


direction flag to 1, thereby causing the string
instruction to auto-decrement the index registers (SI or
DI).

Format:

STD

Action:

DF

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176

CONTROL TRANSFER INSTRUCTIONS

The LOOP Instruction

The LOOP instruction decrements CX by 1 and


transfers control to the target location if CX is not 0;
otherwise, the instruction following LOOP is
executed.

Format:

LOOP short-label

Action:

CX

[CX] - 1

If CX 0, then jump to the


address specified by the operand;
otherwise execute the instruction
following the LOOP.
Pointers:
1.

The LOOP instruction is used to write loop


sequences.

2.

The LOOP instruction is used with respect to the


CX register. Register CX contains the number of
times the loop is repeated.

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177

3.

Only short-label operands are supported by the


LOOP instruction. This means that the program
could only transfer control within -128 bytes to
+127 bytes from the location of the loop
instruction.

4.

If register CX has an initial value of 0, the loop


instruction will be executed FFFF times (65,536
times). This is because CX is decremented first
before the condition is checked.

Example:

MOV CX, 0003H


MOV AX, 0000H
L1: INC AX
LOOP L1

After execution of the program:


AX = 0003H
CX = 0000H

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178

The LOOPE/LOOPZ Instruction


The LOOPE/LOOPZ (Loop while equal/Loop while
zero) instruction decrements CX by 1 and transfers
control to target location if CX is not zero and if ZF is
1;
otherwise
the
instruction
following
LOOPE/LOOPZ is executed.
Format:

LOOPE short-label
LOOPZ short-label

Action:

CX
[CX] - 1
If CX 0 and ZF = 1, then jump
to the address specified by the
operand; otherwise execute the
instruction
following
the
LOOPE/LOOPZ.

Pointers:
1.
2.

LOOPE and LOOPZ are different mnemonics for


the same instruction.
LOOPE works exactly like LOOP.
The
difference lies in the checking of condition.
When the loop is executed, register CX is
automatically decremented by 1 and then the
values of both register CX and ZF are checked.
If CX is not equal to 0 and ZF is 1 (a comparison
inside the loop is not equal), it jumps to the
instruction specified in the operand; otherwise,
the loop is complete and the instruction following
the LOOPE/LOOPZ is executed.

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179

3.

Only short-label operands are supported by the


LOOPE/LOOPZ instruction. This means that the
program could only transfer control within -128
bytes to +127 bytes from the location of the loop
instruction.

Example:
MOV CX, 0005H
MOV SI, FFFFH
MOV AL, 01H
L1: INC SI
CMP BETA[SI], AL
LOOPE L1

01H
01H
03H
01H
BETA:

01H

In this example, the loop is terminated even


before CX is 0. This is because the third element
(BETA[2]) is not equal to 01H (it has a value of
03H) and, therefore, ZF is reset, causing the loop
to be terminated. Therefore CX = 0002H after
execution.
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180

The LOOPNE/LOOPNZ Instruction


The LOOPNE/LOOPNZ (Loop while not equal/Loop
while not zero) instruction decrements CX by 1 and
transfers control to the target location if CX is not
zero and ZF is 0; otherwise the instruction following
LOOPNE/LOOPNZ is executed.
Format:

LOOPNE short-label
LOOPNZ short-label

Action:

CX
[CX] - 1
If CX 0 and ZF = 0, then jump
to the address specified by the
operand; otherwise execute the
instruction
following
the
LOOPNE/LOOPNZ.

Pointers:
1. LOOPNE and LOOPNZ are different mnemonics
for the same instruction.
2. LOOPNE works exactly like LOOP.
The
difference lies in the checking of condition.
When the loop is executed, register CX is
automatically decremented by 1 and then the
values of both register CX and ZF are checked.
If CX is not equal to 0 and ZF is 0 (a comparison
inside the loop is equal), it jumps to the
instruction specified in the operand; otherwise,
the loop is complete and the instruction following
the LOOPNE/LOOPNZ is executed.
Basic Structure of Computer Hardware and Software

181

3.

Only short-label operands are supported by the


LOOPE/LOOPZ instruction. This means that the
program could only transfer control within -128
bytes to +127 bytes from the location of the loop
instruction.

Example:
MOV CX, 0005H
MOV SI, FFFFH
MOV AL, 01H
L1: INC SI
CMP BETA[SI], AL
LOOPNE L1

04H
07H
01H
05H
BETA:

03H

In this example, the loop is terminated even


before CX is 0. This is because the third element
(BETA[2]) is equal to 01H causing ZF to be
reset, thereby terminating the loop. Therefore
CX = 0002H after execution.

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182

The JCXZ Instruction


The JCXZ (Jump if CX is 0) instruction transfers
control to the target operand if CX is 0.
Format:

JCXZ short-label

Action:

If CX = 0, then jump to the


address specified by the operand.

Pointers:
1.

JCXZ is useful at the beginning of a loop to


bypass the loop if CX has a value of 0.

2.

Only short-label operands are supported by the


JCXZ instruction. This means that the program
could only transfer control within -128 bytes to
+127 bytes from the location of the JCXZ
instruction.

Example:
MOV CX, 0000H
MOV AL, 00H
JCXZ L2
L1: INC AL
LOOP L1
L2:
:
:
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183

The CALL Instruction

The CALL (Subroutine Call) instruction transfers


control to a subroutine.
After executing the
subroutine, control is transferred back to the
instruction following the CALL instruction.

Format:

CALL operand

Action:

Execution continues from the


address of the subroutine specified
by the operand.
After the
subroutine is executed, control is
transferred to the instruction after
the CALL instruction.

Operand
Near-proc
Far-proc
Regptr16
Memptr16
Memptr32

Basic Structure of Computer Hardware and Software

Example
CALL L1
CALL far L1
CALL DX
CALL [BX]
CALL far [BX]

184

Pointers:
1.

After executing the subroutine, control is


transferred back to the instruction following the
CALL instruction. In order to do this, the
contents of either both registers CS and IP, or
register IP only (depending on the type of
CALL), is pushed into the stack before control is
relinquished to the subroutine.
After the
subroutine has finished executing, the contents of
both registers CS and IP, or register IP only, is
popped out of the stack. In this way, the program
is able to continue execution on the instruction
after the CALL instruction.

2.

The CALL instruction could be classified as


intrasegment call (near call) or intersegment
jump (far call).
In intrasegment call, the subroutine to be called is
located within the current code segment. In this
case, only the value of register IP is pushed into
the stack.
For intersegment call, the subroutine to be called
may be placed in any other code segment. This
means that both registers CS and IP are pushed
into the stack.

Basic Structure of Computer Hardware and Software

185

3.

Operands used with the CALL instruction could


be represented as labels. These labels are
procedure names of the called subroutine.

4.

Operands could either be relative or absolute.


In the relative operand, the operand is a signed
displacement (or offset) from the CALL
instruction to the target subroutine location. This
means that the address of the target subroutine
location is obtained by adding the displacement
from the CALL instruction to the contents of IP.
In the absolute operand, the operand itself
already contains the address of the target
subroutine.

5.

Intrasegment call supports both absolute and


relative operands, while intersegment call
supports absolute operands only.

6.

Relative operands for intrasegment call are nearlabels. This means that program transfer could
transfer control to the subroutine within -32,768
bytes to 32,767 bytes from the location of the
CALL instruction.

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186

Summary:

CALL

Intrasegment CALL

Relative

Absolute

near-proc

Basic Structure of Computer Hardware and Software

Intersegment CALL

Absolute

RegPtr16

far-proc

MemPtr16

MemPtr32

187

The RET Instruction


The RET (Return) instruction transfers control from a
subroutine back to the instruction following the CALL
instruction.
Format:

RET operand
RET

Action:

Transfer control from a subroutine


back to the instruction following
the CALL instruction.
Operand
None
Disp16

Example
RET
RET 2

Pointers:
1.

For intrasegment CALL, RET pops out the


contents of register IP at the top of the stack. For
intersegment CALL, RET pops out both the
contents of register IP and CS at the top of stack.

2.

The optional Disp16 operand is an offset value


added to register SP after restoring the return
address into registers CS and IP, or register IP
only. This is provided to discard the parameters
that are pushed into the stack before the CALL
instruction is initiated.

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188

STRING INSTRUCTIONS

String instructions are a powerful set of instructions.


The basic string instructions operate on a series of
data, one element (byte or word) at a time, located in
consecutive memory locations. But combined with
string prefixes, the basic string instructions are
executed repeatedly until the entire series of data are
performed upon.

String instructions are sometimes called block


instructions or string primitives.

There are two functional groups of string instructions.


These are the data movement group and the data
scanning and comparison group.
In the data movement group, the operation involves
moving data from one memory location to
accumulator (and vice versa) or from one memory
location to another.
For the data scanning and comparison group, the
operation involves locating data in the memory or
comparing two memory locations.

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189

String Prefix
1.

REP
The REP (repeat) prefix is not an instruction. It
is an instruction prefix that works with string
instructions only. The REP prefix causes the
basic string instruction to be repeated until CX is
zero. The operation of the REP prefix is as
follows:
while CX < > 0
begin
execute string instruction
CX = CX - 1
end
Pointers:
1.

REP is used in conjunction with the MOVS


and STOS instructions.

2.

CX contains the number of times the string


instruction is to be repeated.

3.

CX is checked first before the string


instruction is executed.
CX is then
decremented by 1 after the string instruction
is executed. If CX is zero, then the loop is
terminated. If CX is initially 0, the string is
not executed and control goes to the next
instruction.

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190

2.

REPE/REPZ
The REPE/REPZ (repeat while equal) prefix
causes the string instruction to be repeated until
CX = 0 or ZF = 0. The operation of the
REPE/REPZ prefix is as follows:
while CX < > 0
begin
execute string instruction
CX = CX 1
If ZF = 0 terminate loop
end

Pointers:
1.

REPE/REPZ is used in conjunction with the


CMPS and SCAS instructions.

2.

CX contains the number of times the string


instruction is to be repeated.

3.

CX is checked first before the string


instruction is executed.
CX is then
decremented by 1 after the string instruction
is executed. The loop is terminated if ZF =
0 or CX = 0. If CX is initially 0, the string
is not executed and control goes to the next
instruction.

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191

3.

REPNE/REPNZ
The REPNE/REPNZ (repeat while not equal)
prefix causes the string instruction to be repeated
until CX = 0 or ZF = 1. The operation of the
REPNE/REPNZ prefix is as follows:
while CX < > 0
begin
execute string instruction
CX = CX 1
If ZF = 1 terminate loop
end

Pointers:
1.

REPNE/REPNZ is used in conjunction with


the CMPS and SCAS instructions.

2.

CX contains the number of times the string


instruction is to be repeated.

3.

CX is checked first before the string


instruction is executed.
CX is then
decremented by 1 after the string instruction
is executed. The loop is terminated if ZF =
1 or CX = 0. If CX is initially 0, the string
is not executed and control goes to the next
instruction.

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192

Data Movement Group

1.

STOS (STOSB/STOSW)
The STOS (store string) instruction transfers a
byte from register AL (STOSB), or a word from
register AX (STOSW) to the memory location
pointed to by DI. DI is updated to point to the
next memory location.
The operation of the STOSB instruction is as
follows:
(ES:DI)
AL
if DF = 0
DI = DI + 1
else
DI = DI 1

The operation of the STOSW instruction is as


follows:
(ES:DI)
AX
if DF = 0
DI = DI + 2
else
DI = DI 2

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193

Pointers:
1.

The source operand is the accumulator


(i.e., AL or AX) and the destination
operand is the memory location pointed by
register DI.
Note that the destination
operand is assumed to be in the extra
segment.

2.

After executing the STOS instruction, DI is


automatically incremented if DF is 0.
Otherwise, it is automatically decremented.

3.

If this instruction is used in conjunction


with the REP prefix, it provides a
convenient way to initialize consecutive
memory locations with a constant value.

Example:
CLD
MOV CX, 0005H
LEA DI, ALPHA
XOR AL, AL
REP STOSB
In this example, memory location ALPHA,
which is pointed by DI is initialized with the
value of AL (00H). Since DF is 0, DI is
automatically incremented by 1.
This
process is repeated 5 times (since CX is 5).
Basic Structure of Computer Hardware and Software

194

2.

LODS (LODSB/LODSW)

The LODS (load string) instruction transfers a


byte or word from a memory location pointed by
SI into register AL (LODSB) or AX (LODSW).
SI is updated to point to the next memory
location.

The operation of the LODSB instruction is as


follows:

AL
(DS:SI)
if DF = 0
SI = SI + 1
else
SI = SI 1

The operation of the LODSW instruction is as


follows:

AX
(DS:SI)
if DF = 0
SI = SI + 2
else
SI = SI 2
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195

Pointers:
1.

The
destination
operand
is
the
accumulator (i.e., AL or AX) and the
source operand is the memory location
pointed by register SI. Note that the source
operand is assumed to be in the data
segment.

2.

After executing the LODS instruction, SI is


automatically incremented if DF is 0.
Otherwise, it is automatically decremented.

Example:
STD
LEA SI, ALPHA
LODSB

ALPHA

12H

SI

56H
78H

In this example, register AL is initialized with the


value of the memory pointed to by SI. Thus, AL
has value of 12H after execution. Since DF is 1,
DI is automatically decremented by 1.
Basic Structure of Computer Hardware and Software

196

3.

MOVS (MOVSB/MOVSW)
The MOVS (move string) instruction transfers a
byte (MOVSB) or a word (MOVSW) from one
memory location pointed by SI into another
memory location pointed by DI. Both SI and DI
are updated to point to the next memory location.
The operation of the MOVSB instruction is as
follows:
(ES:DI)
(DS:SI)
if DF = 0
SI = SI + 1
DI = DI + 1
else
SI = SI 1
DI = DI 1

The operation of the MOVSW instruction is as


follows:
(ES:DI)
(DS:SI)
if DF = 0
SI = SI + 2
DI = DI + 2
else
SI = SI 2
DI = DI 2
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197

Pointers:
1.

2.

3.

The destination operand located in the


memory location pointed by DI and the
source operand is located in the memory
location pointed by register SI. Use LEA to
initialize both SI and DI registers. Note that
the source operand is assumed to be in the
data segment while the destination operand
is assumed to be in the extra segment.
After executing the LODS instruction, both
SI and DI are automatically incremented if
DF is 0. Otherwise, they are automatically
decremented.
If this instruction is used in conjunction
with the REP prefix, it provides a
convenient way to perform memory-tomemory transfer.

Example:
CLD
MOV CX, 0005H
LEA SI, ALPHA
LEA DI, BETA
REP MOVSB
In this example, memory location BETA is
initialized with the contents of memory location
ALPHA which is pointed by SI. Since DF is 0,
both SI and DI are incremented by 1. This
process is repeated 5 times (since CX is 0005H).
Basic Structure of Computer Hardware and Software

198

Data Scanning and Comparison Group


1.

SCAS (SCASB/SCASW)
The SCAS (scan string) instruction compares the
value of register AL (SCASB) or register AX
(SCASW) with the memory location pointed by
DI. DI is updated to point to the next memory
location.
The operation of the SCASB instruction is as
follows:
CMP AL, (ES:DI)
if DF = 0
DI = DI + 1
else
DI = DI 1

The operation of the SCASW instruction is as


follows:
CMP AX, (ES:DI)
if DF = 0
DI = DI + 2
else
DI = DI 2

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199

Pointers:
1.

After executing the SCASS instruction, DI


is automatically incremented if DF is 0.
Otherwise, it is automatically decremented.

2.

Neither the contents of the accumulator nor


the memory location are affected after
execution. But the status flags are affected.

3.

If this instruction is used in conjunction


with the REPE/REPNE prefix, it provides a
convenient way to locate a value in the
memory.

Example:
CLD
MOV CX, 0007H
LEA DI, ALPHA
MOV AL, 02H
REPNE SCASB
In this example, the program scans the
memory starting at ALPHA (a total of 7
memory locations) for the value 02H.

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200

2.

CMPS (CMPSB/CMPSW)
The CMPS (compare string) instruction compares
a memory location pointed by SI with another
memory location pointed by DI. Both SI and DI
are updated to point to the next memory location.
The operation of the CMPSB instruction is as
follows:
CMP (ES:DI), (DS:SI)
if DF = 0
SI = SI + 1
DI = DI + 1
else
SI = SI 1
DI = DI 1

The operation of the CMPSW instruction is as


follows:
CMP (ES:DI), (DS:SI)
if DF = 0
SI = SI + 2
DI = DI + 2
else
SI = SI 2
DI = DI 2

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201

Pointers:
1.

After executing the CMPS instruction, both


SI and DI are automatically incremented if
DF is 0. Otherwise, they are automatically
decremented.

2.

Both memory locations are not affected after


execution. But the status flags are affected.

3.

If this instruction is used in conjunction


with the REPE/REPNE prefix, it provides a
convenient way to compare two memory
locations.

Example:
CLD
MOV CX, 0007H
LEA SI, ALPHA
LEA DI, BETA
REPE CMPSB

In this example, the program compares


whether two memory locations are exactly
the same.

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202

Sample Program on Strings

Write an assembly language program that checks if


ASCII A (41H) exists in a 6-lement list. The list is
stored at memory starting at location ALPHA. If
ASCII A is not found in the list, then initialize
memory location STAT with 00H, else initialize it
with FFH.

Program:

MOV byte ptr STAT, 00H


MOV CX, 0006H
CLD
LEA DI, ALPHA
MOV AL, 41H
REPNE SCASB
JNE FINISH
MOV byte ptr STAT, FFH
FINISH:

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203

USING ASSEMBLERS
THE FORMAT OF A LINE

Assembly language source code lines follow this


format:

<label> <instruction/directive> <operands> <;comment>

where:
<label> is an optional symbolic name

<instruction/directive> is either the mnemonic


for an instruction or a directive

<operands> contains a combination of zero, one,


or two (or sometimes more) constants, memory
references, register references, and text strings, as
required by the particular instruction or directive

<;comment> is an optional comment

Basic Structure of Computer Hardware and Software

204

LABELS

Labels are nothing more than names used for referring


to numbers and character strings or memory locations
within a program. Labels allow programmers to give
names to memory variables, values, and the locations
of particular instructions.

Labels can consist of the following characters:


A-Z

a-z

0-9

The digits 0-9 cannot be used as the first character of a


label. A single $ or ? has a special meaning, so they
may not be used as a user symbolic name. The
maximum length of a label is 31 characters (this
limitation depends on the actual assembler used).
Do not use register names or built-in symbols (such as
BX, byte, ptr, word, add) as labels.
Sample labels:
MainLoop
start_computing
Error0
initialize
Draw$Dot
Delay_100_milliseconds

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205

CONSTANTS AND EXPRESISONS

A numeric literal is a combination of digits and other


optional parts, a sign, a decimal point, and an
exponent.
Examples:
5
5.5
-5.5
26.E+05

Integer constants can end with a radix symbol that


identifies the numeric base. The bases are:
h
q or o
d
b

=
=
=
=

hexadecimal
octal
decimal
binary

If no radix is specified, decimal is the default.


26
1Ah
1101b
36q
0F6h

decimal
hexadecimal
binary
octal
hexadecimal

When a hexadecimal constant begins with a letter, it


must contain a leading zero.
Basic Structure of Computer Hardware and Software

206

A constant expression consists of combinations of


numeric literals, operators, and defined symbolic
constants. The expression value must be able to be
determined at assembly time, and its value cannot
change at runtime. Here are some examples of
expressions involving only numeric literals:
5
26.5
4 * 20
-3 * 4 / 6
-2.301E+04

A symbolic constant is created by assigning a constant


expression to a name. For example:

rows = 5
column = 10
TablePos = rows * columns

Although these declarations look like runtime


statements written in a high-level language, it is
important to realize that they can only be evaluated at
assembly time.

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207

A constant may also represent a string of characters


enclosed in either single or double quotation marks.
Recall that a string is a contiguous sequence of bytes
or words. Embedded quotes are permitted, as the
following examples show:
ABC
X
This is a test
4096
This isnt a test
Say hello to Bill.
Notice that the string constant containing 4096 is
four bytes long, each containing the ASCII code for a
single character. To be specific, the string 4096 is
equivalent to:
34H

30H

39H

36H

While the number 4,096 is equivalent to 1000H.

Take note also that strings are enclosed in either single


or double quotes. If a string constant is enclosed in
single quotes, it may contain a double quote as an
embedded character. If a string is enclosed in double
quotes, it may contain a single quote as an embedded
character.
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208

INSTRUCTION MNEMONICS AND DIRECTIVES

Mnemonics are human-readable names for the


machine language instructions the 8086/88 executes
directly (such as ADD, MOV, and JMP).

The assembler assembles each instruction mnemonic


directly to the corresponding machine-language
instruction (1s and 0s).

Directives are quite the opposite of instruction


mnemonics: they generate no executable code at all,
but rather control various aspects of how the
assembler operates. They enable the programmer to
control the way a program assembles and lists.

Directives act only during the assembly of a program


and generate no machine-executable code.

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209

DATA DEFINITION DIRECTIVES

Data definition directives (also called data allocation


directives) allow programmers to reserve memory for
future data. In other words, data definition directives
allow programmers to define memory variables.

The data definition directives are:


1.

DB (define byte). This defines 1 byte.

2.

DW. This defines 1 word (2 bytes).

3.

DD. This defines 2 words (4 bytes).

4.

DQ. This defines 4 words (8 bytes).

5.

DT. This defines 10 bytes.

Examples:
1.

The directive:
ByteVar

DB

20H

will store 20H in a certain memory location


and the offset of that location is assigned to
label ByteVar.
Basic Structure of Computer Hardware and Software

210

Sample instruction that uses ByteVar.


MOV AL, ByteVar
2.

The directive:
WordVar

DW

1234H

will store 1234H in a certain memory


location and the offset of the first location is
assigned to label WordVar.

Sample instruction that uses WordVar.


MOV AX, WordVar

Initializing Arrays
Multiple values may appear with a single data
definition directive.
Example:
1.

SampleArray1

DB 10H, 20H, 30H, 40H, 50H

This creates a five-entry array SampleArray1


made up of byte-sized elements. The contents of
the array are initialized to 10H, 20H, 30H, 40H,
and 50H (in that order).
Basic Structure of Computer Hardware and Software

211

SampleArray1 points to the offset of the first


memory location of the array.

2.

SampleArray2

DB 10H, 20H, 30H, 40H, 50H


DB 60H, 70H, 80H, 90H, A0H

This creates a 10-entry array SampleArray2 made


up of byte-sized elements.

3.

SampleArray3

05H DW DUP (1000H)

This creates a 5-entry array SampleArray3 made


up of word-sized elements. Each element of the
array is initialized to 1000H.

4.

SampleArray4

05H DB DUP (?)

This creates a 5-entry array SampleArray4 made


up of byte-sized elements. Each element of the
array is not set to any specific value.

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212

Initializing Character Strings

Characters are valid operands to the data definition


directives. This allows programmers to define a
character string as follows:

1.

String1 DB A, B, C, D, E

This creates a five-entry array String1 made up of


byte-sized elements. The contents of the array
are initialized with the ASCII values of the
characters A, B, C, D, and E.

2.

String1 DB ABCDE

This is a shortcut for the previous example.

3.

String2 DB Mitch M. Andaya

This creates a 15-entry array String2 made up of


byte-sized elements.
Basic Structure of Computer Hardware and Software

213

Sample Assembled Program:

0000
0001
0002
0003
0004
0010

00
30
30
7A
000C[ 00 ]
43 6F 6D
65 72 20
63 65 73
73
34 37 38
01 4A 61
65 62

BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6

DB
DB
DB
DB
DB
DB

?
48
30H
01111010B
12 DUP(0)
Computer Processors

BYTE7
BYTE8

DB
DB

47835
01, Jan, 02, Feb

WORD1
WORD2
WORD3
WORD4

DW
DW
DW
DW

0FFF0H
01111010B
BYTE7
2, 4, 6, 7, 9

0040

FFF0
007A
0023 R
0002 0004 0006 0007
0009
0006 [ 0000 ]

WORD5

DW

6 DUP(0)

004C
0050
0054
005C
0060

00000000
00007457
0000001B 00000038
00000001
00005043

DWORD1
DWORD2
DWORD3
DWORD4
DWORD5

DD
DD
DD
DD
DD

?
29783
27, 56
BYTE3 BYTE2
PC

0064 0000000000000000
006C 0000000000005E39
0074 0000000000007457

QWORD1
QWORD2
QWORD3

DQ
DQ
DQ

?
05E39H
29783

007C 000000000000000000
00
0086 000000000000002978
30
0090 000000000000000050
43

TENB1

DT

TENB2

DT

297830

TENB3

DT

PC

0023
0028

0030
0032
0034
0036

70 75 74
50 72 6F
73 6F 72
33 35
6E 02 46

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214

BYTE1, BYTE2, BYTE3, BYTE4, and BYTE5 are


examples of numeric DB constants .
BYTE6 and BYTE7 are examples of DB character
expressions (that contain a string of any length up to
the end of the line). The object code shows the ASCII
character for each byte in normal left-to-right
sequence, where 20H represents a blank character
(space).
BYTE8 shows a mixture of numeric and string
constants suitable for defining a table.
The assembler converts DW numeric constants to
binary object code (represented in hex), but stores the
bytes in reverse sequence. Consequently, a decimal
value defined as 12345 converts to hex 3039, but is
stored as 3930.
WORD1 and WORD2 are examples of DW numeric
constants.
WORD3 defines the operand as an address in this
case, the offset address of BYTE7. The generated
object code is 0023 (the R to the right means
relocatable), and a check of the sample program
shows that the offset address of BYTE7 is indeed
0023.
WORD4 defines a table of five numeric constants.
Note that the length of each constant is 1 word (2
bytes).
Basic Structure of Computer Hardware and Software

215

WORD5 defines a table initialized with 6 zeros.

The assembler converts DD numeric constants to


binary object code (represented in hex), but stores the
bytes in reverse sequence.
Consequently, the
assembler converts a decimal value defined as
12345678 to 00BC614EH and stores it as
4E61BC00H.
DWORD2
DWORD3
generates
addresses;
BYTE2.

defines a DD numeric constant while


defines two numeric constants. DWORD4
the difference between two defined
in this case, the result is the length of

The assembler handles DQ numeric values and


character strings just as it does DD and DW numeric
values. QWORD2 and QWORD3 illustrate numeric
values.
The DT directive defines data items that are 10 bytes
long. Its purpose is to define packed BCD numeric
values, which are more useful for numeric
coprocessors than for standard arithmetic operations.
A BCD number is packed with two decimal digits per
byte. Note that DT, unlike the other data directives,
stores numeric constants as decimal rather than as
hexadecimal values. For a constant defined as
12345678, it is stored as 00 00 00 00 00 00 12 34 56
78.
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216

THE LABEL DIRECTIVE

Another way of naming a memory location is by using


the LABEL directive. The Label directive allows the
programmer to define a name with specific attributes.
The format is:
name

LABEL type

Example:

KeyBuffer

LABEL BYTE
DB 0AH DUP(?)

This is the same as:

KeyBuffer

0AH DB DUP(?)

Some of the label types that can be defined with


LABEL include:

BYTE
WORD
DWORD
TWORD
Basic Structure of Computer Hardware and Software

217

THE EQU (EQUATE) DIRECTIVE

The EQU directive does not define a data item.


Instead, it defines a value that the assembler can use to
substitute in other instructions. The format is:

name

EQU

expression

Example:
COUNTR

EQU

05

Whenever the word COUNTR appears in a


instruction or another directive, the assembler
substitutes the value 05.

MOV AL, COUNTR

The assembler replaces COUNTR in the MOV


instruction with the value 05, making the operand
an immediate value, as if it were coded as:

MOV AL, 05

Basic Structure of Computer Hardware and Software

218

The EQU directive can also be used in conjunction


with the data definition directives. For example:

ITEM1
ITEM2
ITEM3

DB 1024 DUP (?)


DB 2*1024 DUP (?)
DB 3*1024 DUP (?)

These can be replaced by:

K
ITEM1
ITEM2
ITEM3

EQU
1024
DB K DUP (?)
DB 2*K DUP (?)
DB 3*K DUP (?)

Equates are particularly useful when you have


statements that depends on certain fundamental
values. Using equates, a programmer can represent
the values by symbolic names. If the values need to
be changed, all the programmer has to do is change
the equates and reassemble the program.

Moreover, the intelligent use of equates makes a


program more readable by substituting meaningful
names for numbers.

Basic Structure of Computer Hardware and Software

219

THE PAGE AND TITLE DIRECTIVES

The PAGE and TITLE directives help to control the


format of a listing of an assembled program. This is
their only purpose, and they have no effect on
subsequent execution of the program.

The PAGE directive designates the maximum number


of lines to list on a page and the maximum number of
characters on a line. Its general format is
PAGE

[length] [,width]

For example, the directive PAGE 60,132 provides 60


lines per page and 132 characters per line.
Omission of a PAGE statement causes the assembler
to default to PAGE 50,80.
A programmer may also want to force a page to eject
at a specific line in the program listing. At the
required line, simply code PAGE with no operand.
On encountering PAGE, the assembler advances to the
top of the next page where it resumes the listing.

The TITLE directive causes a title for a program to


print on line 2 of each page of the program listing. Its
general format is
TITLE

Basic Structure of Computer Hardware and Software

text

220

THE STANDARD SEGMENT DIRECTIVES

Segment directives facilitate segment control. There


are two kinds of segment directives: simplified
segment directives and standard segment directives.

Standard Segment Directives.


These give the
programmer full control over segment type, alignment,
naming, and the way segments are combined.
The SEGMENT directive defines the start of a
segment. The segment name must be present, must be
unique, and must follow assembler naming
conventions. The ENDS statement indicates the end
of the segment and contains the same name as the
SEGMENT statement. They have the following
format:

NAME
name

name

OPERATION
SEGMENT
.
.
.
ENDS

OPERAND
[options]

COMMENT
;Begin segment

;End segment

The operand of a SEGMENT statement may contain


three types of options: alignment, combine, and class,
coded in this format:
name

SEGMENT

Basic Structure of Computer Hardware and Software

align combine class


221

The align entry indicates the alignment type or the


boundary on which the segment is to begin. For the
typical requirement, PARA, the segment aligns on a
paragraph boundary, so that the starting address is
evenly divisible by 16 or 10H. Omission of the align
operand causes the assembler to default to PARA.

The combine entry indicates the combine type. This


indicates whether to combine the segment with other
segments when they are linked after the assembly
process. Combine types are STACK, COMMON,
PUBLIC, and AT expression. For example, the stack
segment is commonly defined as:
name SEGMENT PARA STACK
A programmer may use PUBLIC and COMMON
where it is intended to combine separately assembled
programs when linking them. Otherwise, where a
program is not to be combined with other programs,
the programmer may omit this option or code NONE.

The class entry indicates the class type (enclosed in


apostrophes. This is used to group related segments
when linking. It uses the classes code for the code
segment, data for the data segment, and stack for
the stack segment.
Basic Structure of Computer Hardware and Software

222

THE PROC (PROCEDURE) DIRECTIVE

The code segment contains executable code for a


program, which consists of one or more procedures.

The PROC directive defines these procedures.

A segment that contains only one procedure would


appear as follows:

NAME
segname
procname

procname
segname

OPERATION
SEGMENT
PROC
.
.
.
ENDP
ENDS

OPERAND
PARA
FAR

COMMENT
;one
;procedure
;within
;the code
;segment

The procedure name must be present, must be unique,


and must follow assembler naming conventions. The
operand FAR in this case is related to program
execution. When the execution of the program is
requested, the program loader uses this procedure as
the entry point for the first instruction to execute.

The ENDP directive indicates the end of the


procedure and contains the same name as the PROC
statement to enable the assembler to relate the end to
the start.

Basic Structure of Computer Hardware and Software

223

THE ASSUME DIRECTIVE

An .EXE program uses the SS register to address the


stack, the DS register to address the data segment, and
the CS register to address the code segment (as oppose
to a .COM program in which the code, data, and the
stack are contained in one segment).

Because of this, the programmer must tell the


assembler the purpose of each segment in the
program. The required directive is ASSUME, coded
in the code segment as follows:

OPERATION
ASSUME

OPERAND
SS:stackname, DS:datasegname, CS:codesegname,

SS:stackname means the assembler is to associate the


name of the stack segment with the SS register, and
similarly for the other operands shown. The operands
may appear in any sequence.

Like other directives, the ASSUME is just a message


to help the assembler convert symbolic code to
machine code; the programmer may still have to code
instructions that physically load addresses in segment
registers at execute time.

Basic Structure of Computer Hardware and Software

224

THE END DIRECTIVE

The ENDS directive ends a segment and the ENDP


directive ends a procedure. An END directive ends
the entire program and appears as the last statement.

Its general format is:

OPERATION
END

OPERAND
[procname]

The operand may be blank if the program is not to


execute; for the example, the programmer may want to
assemble only data definitions, or the programmer
may want to link the program with another module.

In most programs, the operand contains the name of


the first or only PROC designated as FAR, where
program execution is to begin.

Basic Structure of Computer Hardware and Software

225

INSTRUCTIONS FOR INITIALIZING A PROGRAM

Sample Program

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

PAGE 60,132
TITLE
A04ASM1
Skeleton of an .EXE Program
;-----------------------------------------------------------------------------------------STACKSG SEGMENT PARA STACK Stack

Explanation by line number

STACKSG ENDS
;-----------------------------------------------------------------------------------------DATASG
SEGMENT PARA Data
DATASG
ENDS
;-----------------------------------------------------------------------------------------CODESG
SEGMENT PARA Code
MAIN
PROC
FAR
ASSUME
SS;STACKSG,DS:DATASG,CS:CODESG
MOV
AX, DATASG
;Set address of data
MOV
DS, AX
; segment in DS
...
MOV
AX, 4C00H
;End processing
INT
21H
MAIN
ENDP
;End of procedure
CODESG
ENDS
;End of segment
END
MAIN
;End of program

The PAGE directive for this listing establishes 60


lines and 132 columns per page.

The TITLE directive identifies the programs


name as AO4ASM1.

Lines 3, 7, and 11 are comments that clearly set


out three defined segments

Basic Structure of Computer Hardware and Software

226

4-6

These statements define the stack segment,


STACKSG (but not its contents in this example).

8-10

These statements define the data segment (but not


its contents).

12-21

These statements define the code segments only


procedure, named MAIN in this example. This
procedure illustrates common initialization and
exit requirements for an .EXE program. The two
requirements for initializing are (1) notify the
assembler which segments to associate with
segment registers and (2) load DS with the
address of the data segment.

14

The ASSUME directive notifies the assembler to


associate certain segments with certain segment
registers, in this case, STACKSG with SS,
DATASG with DS, and CODESG with CS.

By associating segments with segment registers,


the assembler can determine offset addresses for
items in the stack, for data items in the data
segment, and for instructions in the code
segment.

Basic Structure of Computer Hardware and Software

227

15,16

Two instructions initialize the address of the data


segment in the DS register:

MOV AX, DATASG


MOV DS, AX

;Get address of data segment


;Store address in DS

The first MOV loads the address of the data


segment into AX and the second MOV copies
this address from AX into DS. Two MOVs are
required because no instruction can move data
directly from memory to a segment register.

18,19

These two instructions request an end to program


execution and a return to the operating system,

22

The END statement tells the assembler that this is


the end of the program, and the MAIN operand
provides the entry point for subsequent program
execution. MAIN could be any other name
acceptable to the assembler.

Basic Structure of Computer Hardware and Software

228

INSTRUCTIONS FOR ENDING PROGRAM EXECUTION

INT 21H is a common DOS interrupt that uses a


function code in the AH register to specify an action
to be performed.

The many functions of INT 21H include keyboard


input, screen handling, disk I/O, and printer output.

The function code 4CH is recognized by INT 21H as a


request to end program execution.

A programmer may use this operation to pass a return


code in AL for subsequent testing in a batch file (via
the IF ERRORLEVEL statement), as follows:

MOV AH, 4CH


MOV AL, retcode
INT 21H

;Request end processing


;Optional return code
;Call interrupt service

The return code for normal completion of a program is


usually 0 (zero). The programmer may also code the
two MOVs as one statement:

MOV AX, 4C00H

Basic Structure of Computer Hardware and Software

;Request normal exit

229

EXAMPLE OF A SOURCE PROGRAM

Sample Program
PAGE 60,132
TITLE
A04ASM1 (EXE)
Move and add operations
;-----------------------------------------------------------------------------------------STACKSG SEGMENT PARA STACK Stack
DW
32 DUP (0)
STACKSG ENDS
;-----------------------------------------------------------------------------------------DATASG
SEGMENT PARA Data
FLDD
DW
175
FLDE
DW
150
FLDF
DW
?
DATASG
ENDS
;-----------------------------------------------------------------------------------------CODESG
SEGMENT PARA Code
MAIN
PROC
FAR
ASSUME
SS;STACKSG,DS:DATASG,CS:CODESG
MOV
AX, DATASG
;Set address of data
MOV
DS, AX
; segment in DS

MAIN
CODESG

MOV
ADD
MOV

AX, FLDD
AX, FLDE
FLDF, AX

;Move 175 to AX
;Add 150 to AX
;Store sum in FLDF

MOV
INT
ENDP
ENDS
END

AX, 4C00H
21H

;End processing

MAIN

;End of procedure
;End of segment
;End of program

The segments are defined in this way:


STACKSG contains one entry, DW, that contains
32 words initialized to zero, an adequate
size for small programs.

Basic Structure of Computer Hardware and Software

230

DATASG defines three words named FLDD


(initialized with 175), FLDE (initialized
with 150), and FLDF (uninitialized).

CODESG contains executable instructions for the


program, although the first statement,
ASSUME, generates no executable code.

The ASSUME directive performs these operations:

Assigns STACKSG to the SS register, so that the


system uses the address in the SS register for
addressing STACKSG.
Assigns DATASG to the DS register, so that the
system uses the address in the DS register
for addressing DATASG.
Assigns CODESG to the CS register, so that the
system uses the address in the CS register
for addressing CODESG.

When loading a program from disk into memory for


execution, the program loader sets the actual addresses
in the SS and CS registers, but as shown by the first
two MOV instructions, the programmer has to
initialize the DS (and possibly the ES) register.

Basic Structure of Computer Hardware and Software

231

THE SIMPLIFIED SEGMENT DIRECTIVES

The assembler provides short cuts in defining


segments.

Simplified Segment Directives make segment control


relatively easy. However, it supports only some of the
segment-related features of an assembler.

The .MODEL directive specifies the memory model


for an assembler module that uses the simplified
segment directives. The general format is:
.MODEL

memory-model

The different memory models are:


tiny
small

all data and code in one segment


all data in one segment and all code in
one segment
medium all data in one segment but code in
more than one segment
compact data in more than one segment but code
in one segment
large
both data and code segment in more
than one segment but no array may
exceed 64K
huge
both data and code segment in more
than one segment and arrays may
exceed 64K
Basic Structure of Computer Hardware and Software

232

A programmer may use any of these models for a


stand-alone program (that is, a program that is not
linked to another program).
The TINY model is intended for use of .COM
programs, which have their data, code, and stack in
one 64K segment.
The SMALL model requires that code fits within a
64K segment and data fits within another 64K
segment; this model is suitable for most programs.
The MODEL directive automatically generates the
required ASSUME statement.

The .STACK, .DATA, and .CODE directives define


the stack, data, and code segments. The general format
is:
.STACK
.DATA
.CODE

[size]
[name]

Each of these directives causes the assembler to


generate the required SEGMENT statement and its
matching ENDS.
The default segment names (which do not have to be
defined) are STACK, _DATA, and _TEXT (for the
code segment).
Basic Structure of Computer Hardware and Software

233

The programmer may override the default name for


the code segment.
The default size of the stack is 1,024 bytes, which the
programmer may also override.
The instructions to be used to initialize the address of
a data segment in DS are:
MOV AX, @data
MOV DS, AX

Sample Program

PAGE 60,132
TITLE
A04ASM1 (EXE)
Move and add operations
;-----------------------------------------------------------------------------------------.MODEL
SMALL
.STACK
64
;Define stack
.DATA
;Define data
FLDD
DW
175
FLDE
DW
150
FLDF
DW
?
;-----------------------------------------------------------------------------------------.CODE
;Define code
segment
MAIN
PROC
FAR
MOV
AX, @data
;Set address of data
MOV
DS, AX
; segment in DS

MAIN

MOV
ADD
MOV

AX, FLDD
AX, FLDE
FLDF, AX

;Move 175 to AX
;Add 150 to AX
;Store sum in FLDF

MOV
INT
ENDP
END

AX, 4C00H
21H

;End processing

Basic Structure of Computer Hardware and Software

MAIN

;End of procedure
;End of program

234