EE370 Chapter1 Slides

7/31/2015
Computer
An electronic device which is capable of
receiving information (data) in a particular form
and of performing a sequence of operations in
accordance with a predetermined but variable set
of procedural instructions (program) to produce a
result in the form of information or signals.
EE370
Digital Electronics
Yogesh S. Chauhan
Department of Electrical Engineering
IIT Kanpur
Email: chauhan@iitk.ac.in
Office: WL125, Phone: 7244
Minimize human efforts with speed and

efficiency.
Y. S. Chauhan, IIT Kanpur
Why Digital?
Digital System
Noise Margin Can be reduced to the limit we

want
Fidelity/Regeneration
Robustness
Scalability
Data Storage
Ease of data handling
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ENIAC - The first electronic computer

(1946)
The First Computer
17,468 vacuum
tubes
7200 crystal
diodes
1500 relays
70,000 resistors
10,000 capacitors
Weight > 27 Ton
1800 sq. ft.
150 kW of
electricity
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
The Transistor Revolution
The First Integrated Circuits

Bipolar logic
1960s
ECL 3-input Gate

Motorola 1966
First transistor
Bell Labs, 1948
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Intel 4004 Micro-Processor
Intel Pentium (IV) microprocessor
1971
1000transistors
1MHzoperation
Moores Law
10
Transistor Counts
1975
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION
In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology
will double its effectiveness every 18 months
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Moores law in Microprocessors
Die Size Growth
1000
100
Transistors(MT)
100
10
P6
Pentium proc
486
Diesize(mm)
2Xgrowthin1.96years!
386
286
0.1
8086
8085
8080
8008
4004
0.01
0.001
1970
10
8080
8008
4004
1980
1990
Year
2000
1
1970
2010
TransistorsonLeadMicroprocessorsdoubleevery2years
8086
8085
286
386
P6
486 Pentiumproc
~7%growthperyear
~2Xgrowthin10years
1980
1990
Year
2000
2010
Diesizegrowsby14%tosatisfyMooresLaw
13
Frequency
14
Power Dissipation
100
P6
Pentiumproc
10000
Frequency(Mhz)
1000
100
486
10
8085
1
0.1
1970
8086 286
Power(Watts)
Doublesevery
2years
P6
Pentiumproc
386
8086 286
1
4004
8080
8008
4004
1980
10
8008
486
386
8085
8080
0.1
1971
1990
Year
2000
1974
1978
1985
1992
2000
Year
2010
LeadMicroprocessorspowercontinuestoincrease
LeadMicroprocessorsfrequencydoublesevery2years
15
Courtesy,Intel
16
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Power density
Power is a major problem

100000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
HotPlate
P6
Pentium proc
8008 8085
386
286
486
8080
1
1970
1980
1990
2000
Year
18KW
5KW
1.5KW
500W
10000
Power(Watts)
PowerDensity(W/cm2)
10000
1000
Pentium proc
100
286
486
8086 386
10
8085
8080
8008
1 4004
0.1
1971
2010
1974
1978 1985 1992

Year
2000 2004
2008
Powerdeliveryanddissipationwillbeprohibitive
Powerdensitytoohightokeepjunctionsatlowtemp
17
Not Only Microprocessors
Challenges in Digital Design
Macroscopic Issues
Microscopic Problems
Small
SignalRF
18
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
etc.
Ultra-high speed design

Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution.
Power
RF
Power
Management
Analog
Baseband
Everything Looks a Little Different
and Theres a Lot of Them!
DigitalBaseband
(DSP+MCU)
CellPhone
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Why Scaling?
Design Abstraction Levels

SYSTEM
Technology shrinks by 0.7/generation

With every generation can integrate 2X more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
MODULE
+
GATE
CIRCUIT
How to design chips with more and more functions?

Design engineering population does not double every
two years
DEVICE
G
Hence, a need for more efficient design methods
S
n+
Exploit different levels of abstraction

21
Design Metrics
DesignAutomationisthekey.
22
Cost of Integrated Circuits
How to evaluate performance of a digital

circuit (gate, block, )?
NRE (non-recurring engineering) costs

Design time and effort, mask generation
One-time cost factor
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
D
n+
Recurring costs
Silicon processing, packaging, test
proportional to volume
proportional to chip area
23
24
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Cost of Integrated Circuits
NRE Cost is Increasing
Cost per IC = Variable cost per IC + (fixed

cost/volume)
The impact of fixed cost is more pronounced
for small volume products.
25
Die Cost
26
Cost per Transistor
Single die
cost:
-per-transistor
1
0.1
Fabrication capital cost per transistor (Moores law)
0.01
0.001
Wafer
0.0001
0.00001
0.000001
Going up to 12 (30cm)
From http://www.amd.com
27
0.0000001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012
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Yield
Yield
No. of good chips per wafer

100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
No. of good chips per wafer

100%
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
Dies per wafer
wafer diameter/22 wafer diameter
die area
2 die area
29
Defects
defects per unit area die area

die yield 1
30
Some Examples (1994)
is approximately 3
die cost f (die area)4
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Reliability
Noise in Digital Integrated Circuits
Example of Capacitive Coupling

Signal wire glitches as large as 80% of the supply voltage will be
common due to crosstalk between neighboring wires as feature sizes
continue to scale
Noise unwanted variations of voltages and

currents at the logic nodes
Crosstalkvs.Technology
v(t)
V DD
PulsedSignal
0.12mCMOS
0.16mCMOS
i(t)
Inductive coupling
Currentchangeonone
wirecaninfluencesignal
ontheneighboringwire
Capacitive coupling
Power and ground

noise
Voltagechangeonone
wirecaninfluencesignal
ontheneighboringwire
crosstalk
33
Lets start Digital Electronics
Blacklinequiet
Redlinespulsed
0.25mCMOS
Glitchesstrengthvstechnology
0.35mCMOS
FromDunlop,Lucent,2000
34
Analog to Digital conversion
Digital Electronics uses binary number system

Logic 0 == Logic Low
Logic 1 == Logic High
Real world is not digital
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Binary digital signal
Digital Logic Inverter

The logic inverter is the most basic element in digital circuit
design.
It plays a role parallel to that of the amplifier in analog
circuits.
Inverter inverts the logic value of its input signal.
Thus, for a logic-0 input, the output will be a logic 1, and vice
versa.
37
Input-Output characteristics of an
Inverter
38
Amplifier vs. Inverter
Lets draw.
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DC Operation
Voltage Transfer Characteristic (VTC)
IsitInverter?
VIL Max. value

vI can have while
being interpreted
as logic 0.
VIH Min. value
vI can have while
being interpreted
as logic 1.
Noise Margins
Insensitivity of the inverter output to the
exact value of vI within allowed regions is a
great advantage that digital circuits have
over analog circuits.
Consider an inverter driving inverter.
Exactvalueofinputdoesntmatter.
41
Noise Margins
42
Voltage Transfer Characteristic
Four parameters, VOH, VOL, VIH, and VIL, define the VTC of an
inverter and determine its noise margins
Switching Threshold Voltage
Changes in vI within the noise margins are rejected by the inverter.

Noise is not allowed to propagate further through the system, a definite
advantage of digital over analog circuits.
You can think of the inverter as restoring the signal levels to

standard values (VOL and VOH) even when it is presented with
corrupted input signal levels (within the noise margins).
Vout
OH
Vout=Vin
ImportantParametersoftheVTCoftheLogicInverter
VM SwitchingThreshold
V OL
V OL
43
OH
Vin
NominalVoltageLevels
44
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Voltage Transfer Characteristic
Mapping between analog and digital signals

The regions of acceptable high and low voltages are delimited
by VIH and VIL that represent the points on the VTC curve
where the gain = -1
Switching Threshold Voltage (VM)

Output is short circuited with input.
Vout=f(Vin)
V(x)
V(y)
V(y)=V(x)
VM
V
0
VIH
V(x)
VDD
VDD
"1"
VOH
NMH = VOH - VIH
Noise Margin High
Noise Margin Low
Slope = -1
IL
V
OL
45
Noise Margins
"0"
Gnd
Gate Input
OL
IL
IH
in
46
The Regenerative Property

A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level
v0
VIH
Undefined
Region
VIL
NML = VIL - VOL
Gnd
Gate Output
Slope = -1
OH
Switching Threshold
For robust circuits, want the 0 and 1 intervals to be as

large as possible
VOL
out
Undefined
Region
VOL = f (VIH)
VIL
V
IH
VOH = f (VIL)
V
OH
v1
v2
v3
v4
v5
v6
v2
5
V (volts)
V(y)
v0
v1
1
-1
Large noise margins Y.are

desirable, but not sufficient 47
S. Chauhan, IIT Kanpur
t (nsec)
10
48
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Conditions for Regeneration

v0
v1
v2
v3
v4
v5
Noise Immunity
v6
Noise margin expresses the ability of a circuit to overpower

a noise source
v1 = f(v0) v1 = finv(v2)
out
out
v3
f(v)
noise sources: supply noise, cross talk, interference, offset
Absolute noise margin values are deceptive
finv(v)
a floating node is more easily disturbed than a node driven by a

low impedance (in terms of voltage)
v1
v3
v1
finv(v)
v2
in
v0
Regenerative Gate
Noise immunity expresses the ability of the system to

process and transmit information correctly in the presence
of noise
f(v)
v0
v2
in
Nonregenerative Gate
To be regenerative, the VTC must have a transient

region with a gain greater than 1 (in absolute value)
bordered by two valid zones where the gain is smaller
than 1. Such a gate has two stable operating points.
Transfer function between noise source and signal node is <<1.

For good noise immunity, the swing (VOH VOL) and noise
margin have to be large enough to overpower the impact of fixed
sources of noise
49
Directivity
50
Fan-in and Fan-out
A gate must be unidirectional: changes in an output

level should not appear at any unchanging input of the
same circuit
In real circuits full directivity is an illusion (e.g., due to
capacitive coupling between inputs and outputs)
Fan-out number of load gates

connected to the output of the driving
gate
Fan-in the number of inputs to

the gate
Gates with large fan-in are
bigger and slower
Gates with large fan-out are slower
Key metrics: output impedance of the driver and input

impedance of the receiver
ideally, the output impedance of the driver should be zero

input impedance of the receiver should be infinity
51
Fan-out N
Fan-in M
52
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VTC of an ideal inverter
VTC of an ideal inverter

The ideal gate should have
V out
Infinite gain in the transition region

Switching threshold located in the middle of the logic swing
High and low noise margins equal to half the swing
Input and output impedances of infinity and zero, respectively
Ri =
Ro = 0
Fanout =
NMH = NML = VDD/2
g=
53
An Old-time Inverter
5.0
4.0
VOH
NM L
Vout (V)
3.0
VM
NM H
1.0
VOL
0.0
VOL 1.0
VIL
2.0
3.0
Vin (V)
VOH 4.0
V
IH Kanpur
Y. S. Chauhan, IIT
V in
54
Performance
VOH=3.5V
VIH=2.35V
VM=1.64V
NMH=1.15V
VOL=0.45V
VIL=0.66V
NML=0.21V
2.0
Note
Asymmetric
NML is low
Swing=3.05V
5.0
<VDD=5V
55
The performance of a digital circuit expresses the computational

load that the circuit can manage.
A microprocessor is characterized by the number of instructions it can
execute per second. This performance metric depends on
Architecture of the processor - for instance, the number of instructions it can
execute in parallel &
Actual design of logic circuitry.
When focusing on the pure design, performance is most often

expressed by the duration of the clock period or clock frequency.
The minimum value of the clock period for a given technology and
design is set by a number of factors such as
Time it takes for the signals to propagate through the logic
Time it takes to get the data in and out of the registers
Uncertainty of the clock arrival times.
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Delay Definitions
Vin
How fast we can toggle?
Vout
Vin
Vout
tpLH and tpHL can be asymmetric
Vin
Propagationdelay
input
waveform
50%
tp =(tpHL +tpLH)/2
tpHL
Time period T> max(tpLH, tpHL)x2

If symmetric, T> max(tp)x2
Duty cycle
tpLH
Vout
90%
output
waveform
10%
tf
time for which it is ON/ (Time period)

Usually its 50%: Rise and fall should occur within T/2 time
signalslopes
50%
tr
57
How to compare delay in different

technologies?
Modeling Propagation Delay
RingOscillator
Model circuit as first-order RC network

vout (t) = (1 et/)V
V
0
v0
v1
v2
v3
v4
v5
v1
Time to reach 50% point is
vin
v5
T = 2 tp N
where = RC
vout
C
v0
58
N=numberofinverters
59
60
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vout (t) = (1 et/)V
V
0
R
vout
C
vout (t) = (1 et/)V
V
0
where = RC
Time to reach 90% from 10% point is
vin
where = RC
vout
C
vin
Time to reach 50% point is

t = ln(2) = 0.69
Time to reach 90% from 10% point is
t = ln(9) = 2.2
Matches the delay of an inverter gate

61
Power and Energy Dissipation
62
Static and Dynamic power
Power consumption: how much energy is consumed per

operation and how much heat the circuit dissipates
Supply line sizing (determined by peak power)
Ppeak = Vdd.ipeak=max(p(t))
Battery lifetime (determined by average power dissipation)
.
Two important components: static and dynamic

Static power dissipation:
Caused by static conductive paths between the supply rails or by
leakage currents.
Always present, even when the circuit is in stand-by.
Minimization of this consumption source is a worthwhile goal.
Dynamic power dissipation:
Occurs only during transients, when the gate is switching.

Charging of capacitors & temporary current paths between supply rails.
Proportional to the switching frequency: the higher the number

of switching events, the higher the dynamic power consumption.
Packaging and cooling requirements
63
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A First-Order RC Network
R
vin
A First-Order RC Network
R
vout
vin
CL
Energydissipated V(t)=VDD
fromsource
T
E
= P t dt
01
0
vout
CL
Energydissipated
Vdd
fromsource
T
T
E 0 1 = P t dt = V dd i sup ply t dt = Vdd CL dV out = C L V dd 2
0
0
0
Energytransferred
tocapacitor
T
T
Vdd
1
2
E
= P
t dt = V
i
t
= C V
dV
= --- C V
dd
ca p
cap
out ca p dt
L out out
2 L
0
0
0
Energytransferred
tocapacitor
T V(t)=Vout
E
= P
t dt
ca p
cap
0
65
Energy and Power
Whereisotherhalf?
66
Energy and Energy-Delay

Propagation delay and power consumption of a gate are related
Propagation delay is mostly determined by the speed at which a given
amount of energy can be stored on the gate capacitors.
The faster the energy transfer (or the higher the power consumption),
the faster the gate.
E (joules) = CL Vdd2 P01 + tsc Vdd Ipeak P01 + Vdd Ileakage
Product of power consumption and propagation delay is generally a

constant for a given technology and gate topology.
Power-Delay Product (PDP) =
f01 = P01 * fclock

P (watts) = CL Vdd2 f01 + tscVdd Ipeak f01 + Vdd Ileakage
E = Energy per operation = Pav tp
An ideal gate is one that is fast, and consumes little energy.
The energy-delay product is a combined metric that brings those two

elements together, and is often used as the ultimate quality metric.
Energy-Delay Product (EDP) =
67
quality metric
of gate = E tp
68
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Analog vs. Digital

Analog
Analog vs. Digital
Digital
Analog
Digital
1. Computewithcontinuousvaluesof
physicalvariablesinsomerange
Computewithdiscretevaluesofphysical
variables
4.
Noiseisduetothermalfluctuationsin
physicaldevices.
2.
Primitivesofcomputationarisefromthe
physicsofthecomputingdevices:
physicalrelationsoftransistors,
capacitors,resistors,floatinggate
devices,Kirchoffs currentandvoltage
lawsandsoforth.Theuseofthese
primitivesisanartformanddoesnot
lenditselfeasilytoautomation. The
amountofcomputationsqueezedoutof
asingletransistorishigh.
Primitivesofcomputationarisefromthe
mathematicsofBooleanlogic:logicalrelations
likeAND,OR,NOT,NAND,andXOR.Theuseof
theseprimitivesisascienceandlendsitself
easilytoautomation.Thetransistorisusedas
aswitch,andtheamountofcomputation
squeezedoutofasingletransistorislow.
5.
Signalisnotrestoredateachstageofthe Signalisrestoredto1or0ateachstageof
computation.
thecomputation.
6.
Inacascadeofanalogstages,noise
startstoaccumulate.Thus,complex
systemswithmanystagesaredifficultto
build.
Roundofferrordoesnotaccumulate
significantlyformanycomputations.Thus,
complexsystemswithmanystagesareeasy
tobuild.
7.
Staticpowerdissipation
PA=N.VDD.I
Static powerisduetoleakagecurrentsonly.
8.
Littleornodynamicpowerdissipation
DynamicpowerconsumptionPD=N.f.C.VDD2
Computationisoffsetpronesinceitis
sensitivetomismatchesinthe
parametersofthephysicaldevices.The
degradationinperformanceisgraceful.
Computationisnotoffsetpronesinceitis
insensitivetomismatchesintheparameters
ofthephysicaldevices.However,asinglebit
errorcanresultincatastrophicfailure.
3.
69
Inside chip
70
Acknowledgement
Noiseisduetoroundofferror.
71
Jan M. Rabaey book

Irwin & Vijays slides, Penn State University
Sedra and Smith book
S.S.K. Iyer, IIT Kanpur
Course TAs
72
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7/31/2015

Minimize human efforts with speed and

Noise Margin Can be reduced to the limit we

Y. S. Chauhan, IIT Kanpur

ENIAC - The first electronic computer

The First Computer

The Transistor Revolution

Y. S. Chauhan, IIT Kanpur

The First Integrated Circuits

ECL 3-input Gate

Y. S. Chauhan, IIT Kanpur

Intel 4004 Micro-Processor

Intel Pentium (IV) microprocessor

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

LOG2 OF THE NUMBER OF

In 1965, Gordon Moore noted that the number of

Y. S. Chauhan, IIT Kanpur

Moores law in Microprocessors

Die Size Growth

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

Power is a major problem

1978 1985 1992

Not Only Microprocessors

Y. S. Chauhan, IIT Kanpur

Challenges in Digital Design

Ultra-high speed design

Everything Looks a Little Different

and Theres a Lot of Them!

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

Design Abstraction Levels

Technology shrinks by 0.7/generation

How to design chips with more and more functions?

Hence, a need for more efficient design methods

Exploit different levels of abstraction

Cost of Integrated Circuits

How to evaluate performance of a digital

NRE (non-recurring engineering) costs

Y. S. Chauhan, IIT Kanpur

Cost of Integrated Circuits

NRE Cost is Increasing

Cost per IC = Variable cost per IC + (fixed

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

Cost per Transistor

Fabrication capital cost per transistor (Moores law)

Y. S. Chauhan, IIT Kanpur

Y. S. Chauhan, IIT Kanpur

No. of good chips per wafer

No. of good chips per wafer

Dies per wafer

wafer diameter/22 wafer diameter

Y. S. Chauhan, IIT Kanpur

defects per unit area die area

Y. S. Chauhan, IIT Kanpur

Some Examples (1994)

Y. S. Chauhan, IIT Kanpur

Example of Capacitive Coupling

Noise unwanted variations of voltages and

Power and ground

Lets start Digital Electronics