Chapter 7 Sequential Circuits

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7 Sequential Circuits
We have so far been looking at combinational circuits in which their output values are computed entirely from
their current input values. We will now study the behavior of sequential circuits where their output values are
computed using both the current and past input values. The dependence of past input values implies the need for
memory elements to remember this history of inputs. The values stored in the memory elements define the state of
the sequential circuit. Since memory is finite, therefore, the sequence size must also be finite, which means that the
sequential logic can contain only a finite number of states. Because of this, sequential circuits are also referred to as
finite-state machines (FSM).
Finite-state machines are a very important part in the designing of microprocessors as we will find out in
Chapter 9. Finite-state machines can be classified into two main types: Moore and Mealy (or a mixture of the two).
A Moore type FSM is one where the output of the machine is independent on the input, whereas a Mealy type FSM
is one where the output is dependent on the input.
Sequential circuits can also either be asynchronous or synchronous. Asynchronous sequential circuits change
their state and output values whenever a change in input values occurs. Synchronous sequential circuits, on the other
hand, change their states and output values only at fixed points in time, which usually are at the active clock edge.

7.1

Finite-State-Machine (FSM) Model

Sequential logic circuits or finite-state machines have a finite number of states. The state memory, consisted of
flip-flops, remembers the current state that the machine is in. In other words, the current state of the machine is
determined by the current contents of the flip-flops. The operation of the finite-state machine is determined by how
it transitions from one state to the next. The circuitry that is responsible for the transitioning of the states is known as
the next-state logic circuit or function. The next-state logic function excites or causes the state memory flip-flops to
change states. In addition to the next-state logic function, there is an output logic function that generates output
signals that are dependent on either the current state only or on both the current state and the input signals. Figure
1(a) shows the general schematic for the finite-state machine where its output is dependent only on its current state.
These types of finite-state machines are known as Moore type machines. Figure 1(b) shows the general schematic
for a Mealy type finite-state machine where its outputs are dependent on both the current state of the machine and
also the inputs.

input signals

Next-state
Logic
Function
F

excitation
Clock

State
Memory current state
Flip-Flops

Output
Logic
Function
G

output signals

(a)

input signals

Next-state
Logic
Function
F

Principles of Digital Logic Design

excitation
Clock

State
Memory current state
Flip-Flops

Enoch Hwang

Output
Logic
Function
G

output signals

Last updated 3/18/2002 2:56 PM

Chapter 7 Sequential Circuits

Page 2 of 14

(b)
Figure 1. Finite-state machines: (a) Moore machine; (b) Mealy machine.

7.2

Analysis of Sequential Circuits

Analysis of sequential circuits is the process in which we are given a sequential circuit and we want to obtain a
precise description of the operation of the circuit. The description can be in the form of a next-state and output table,
and/or a state diagram. The steps for the analysis of sequential circuits is as follows:
1.
2.
3.
4.
5.
6.

Derive the excitation equations for all the flip-flops inputs.

Derive the next-state equations by substituting the excitation equations obtained from step 1 into the flipflops characteristic equations.
Derive the output equations (if any) from the circuit.
Derive the next-state / output table from the next-state and output equations.
Draw the state diagram.
(Optional) Draw the timing diagram.

Example 7.1: A Moore FSM

Figure 2 shows a sample sequential circuit. Comparing this circuit with the general FSM schematic in Figure 1,
we conclude that this is a Moore type FSM, where the state memory consists of two SR flip-flops, the next-state
logic consists of four AND gates, and the output logic consists of one AND gate. We will follow the above steps to
do a detail analysis of this circuit.
C

Input

S1

Q1

Clk

Output

R1

Q'1

S0

Q0

Clk
R0

Q'0

Clk
Next-state logic

State memory

Output logic

Figure 2. A sample Moore finite-state machine.

Step 1: Derive the Excitation Equations.

The excitation equations are what cause the flip-flops to change states. These logic equations, expressed as a
function of the current state and input, provide the excitation signals or inputs to the flip-flops. The current state is
determined by the current contents of the flip-flops, that is, the flip-flops output signals Qi and Qi'. The input is
simply the primary input of the circuit, in the example, it is just the signal C. The excitation equations are derived
from the circuit diagram, and there is one equation for each flip-flops input. Our sample circuit has two SR flipflops having the four inputs S1, R1, S0, and R0, so the four excitation equations for these four inputs are:

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Chapter 7 Sequential Circuits

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S1 = CQ1'Q0
R1 = CQ1Q0
S0 = CQ0'
R0 = CQ0

Step 2: Derive the Next-State Equations

The next-state equations specify what the flip-flops next state should be, and are dependent on the functional
behavior of the flip-flops and the inputs to the flip-flops. The functional behavior of a flip-flop, as you recall, is
described formally by its characteristic equation and was discussed in Section 5.9.6 and summarized in Figure 5.15.
The inputs to the flip-flops are provided by the excitation equations derived in step 1. Thus, to derive the next-state
equations, we substitute the excitation equations into the corresponding flip-flops characteristic equations.
The characteristic equation for the SR flip-flop, from Figure 5.15, is
Qnext = S + R'Q
Since we have two flip-flops, we will have two next-state equations, one for Q0next and one for Q1next. Substituting
the excitation equations into the characteristic equations, we get:
Q0next = S0 + R0'Q0
= CQ0' + (CQ0)'Q0
Q1next = S1 + R1'Q1
= CQ1'Q0 + (CQ1Q0)'Q1

Step 3: Derive the Output Equations

The output equations specify the primary outputs for the FSM and can be dependent on either only the current
state (for a Moore type machine) or on the current state and input (for a Mealy type machine). In the sample circuit,
we have only one output signal Y that is dependent only on the current state of the machine. The output equation as
derived from the circuit diagram is:
Y = Q1Q0

Step 4: Derive the Next-State / Output Table

The next-state table simply lists for every combination of the current state and input values, what the next state
values should be. These next state values are obtained by substituting the current state and input values into the
appropriate next-state equations as derived in step 2. The next-state table for the sample circuit is:

Current State
Q1Q0
00
01
10
11

Next State
Q1next Q0next
C=0
C=1
00
01
01
10
10
11
11
00

For example, to find the Q0next value for the current state Q1Q0 = 00 and C = 1, we substitute the values Q1 = 0,
Q0 = 0 and C = 1 into the equation Q0next = CQ0' + (CQ0)'Q0 = (11) + (10)' 0 to get the value 1. Similarly, we get
Q1next = 0 by substituting the same values for Q1, Q0, and C into the equation Q1next = CQ1'Q0 + (CQ1Q0)'Q1.

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Chapter 7 Sequential Circuits

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After constructing the next-state table, we can add in the output values as obtained from the output equations.
The output table for a Moore machine is slightly deferent from a Mealy machine. For a Moore machine, we can
simply add an extra column in the next-state table for each output signal. For a Mealy machine, the output values
have to be included with the next-state values. The next-state / output table for the sample circuit is as follows:
Current State
Q1Q0
00
01
10
11

Next State
Q1next Q0next
C=0
C=1
00
01
01
10
10
11
11
00

Output
Y
0
0
0
1

Step 4: Derive the State Diagram

The state diagram is a graphical representation of the next-state table where the nodes are the states and the arcs
are the transitions from one state to another, and are labeled with the input signals that causes that transition. The
state diagram for the sample circuit of Figure 2 is:

Q 1 Q 0 = 00
Y =0

C =0

Q 1 Q 0 = 01
Y =0

C =1

C =1

C =1

Q 1 Q 0 = 11
Y =1

C =0

C =0

C =1

Q 1 Q 0 = 10
Y =0

C =0

Step 5: Derive the Timing Diagram

Clk
C
Q1
Q0
Y
t0

t1

t2

t3

From the state diagram and the timing diagram, we can conclude that the circuit of Figure 2 is for a modulo-4

counter where the input C enables or disables the counting.

Example 7.2: A Mealy FSM
Figure 3 shows a sample Mealy FSM. As you recall, the only difference between a Mealy and a Moore FSM is
that for the Mealy FSM, the output is dependent on both the current state and the input. The analysis for a Mealy
FSM proceeds in the same fashion as before. In this example, we have used two different kinds of flip-flops in the
state memory.

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Chapter 7 Sequential Circuits

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Input

J1

Q1

Clk

Clk

Output

K1

Q'1

T0

Q0

Clk
Q'0

Next-state logic

State memory

Output logic

Figure 3. A sample Mealy finite-state machine.

The excitation equations are
J1 = CQ0
K1 = CQ0
T0 = C
and the characteristic equations for the JK and T flip-flops, from Figure 7.15, are respectively
Q1next = K'Q + JQ'
Q0next = T Q.
Substituting the excitation equations into the characteristic equation, we get the following next-state equations
Q1next = K1'Q1 + J1Q1'
= (CQ0)'Q1 + CQ0Q1'
Q0next = T0 Q 0
= C Q0.
The output equation is
Y = CQ1Q0.
From the above next-state / output equations, we get the following next-state / output table
Current State
Q 1Q 0
00
01
10
11

Next State / Output

Q1 next Q0 next / Y
C=0
C=1
00 / 0
01 / 0
01 / 0
10 / 0
10 / 0
11 / 0
11 / 0
00 / 1

Notice the difference between this next-state / output table with the one from the previous example for the
Moore FSM. Here, the output values are dependent on both the current state and the input values, therefore, they are
included together with the next-state values rather than as a separate column. Other than that, all the next-state
values are identical.

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Chapter 7 Sequential Circuits

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Since the output value is dependent on both the state and the input, we also need to modify the way we label the
outputs in the state diagram slightly. Instead of labeling the outputs in the states, we label the outputs on the edges.
Hence, we get the following state diagram

C =0
Y =0

C =1
Y =0

Q 1 Q 0 = 00

Q 1 Q 0 = 01

C =1
Y =1
C =0
Y =0

C =0
Y =0

C =1
Y =0
C =1
Y =0

Q 1 Q 0 = 11

Q 1 Q 0 = 10

C =0
Y =0

The timing diagram for this circuit is

Clk
C
Q1
Q0
Y
t0

t1

t2

t3 t4

We see that this Mealy circuit is also a modulo-4 counter like in the previous example. The only difference is in
the Y output trace. For the Moore machine at t2 when C is de-asserted, Y remains asserted, whereas, for the Mealy

machine at t2 when C is de-asserted, Y is also de-asserted.

7.3

Synthesis of Sequential Circuits

Synthesis of sequential circuits is just the reverse procedure of the analysis of sequential circuits. In synthesis,
we start with what is usually an ambiguous functional description of the circuit that we want. From this description,
we need to come up with a precise state diagram and next-state / output table, from which we can derive the circuit.
During the synthesis process, there are many possible circuit optimizations in terms of the circuit size, speed, and
power consumption. Some basic choices for circuit size optimization include state minimization, state encoding, and
flip-flop type. In many situations, optimizing the circuit size will also result in optimizing the speed and power
consumption. Our discussion will focus mainly on circuit size optimization. Readers interested in speed and power
optimization are referred to the references.
We will first demonstrate the synthesis process without considering optimizations by applying the following
basic steps on a simple example.
1.
2.
3.
4.
5.
6.

Produce a state diagram from the functional description of the circuit.

Derive the next-state / output table from the state diagram.
Derive the implementation table based on the next-state table and the flip-flops excitation table.
Derive the excitation equations for each flip-flop input from the implementation table.
Derive the output equations.
Draw the circuit diagram.

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Chapter 7 Sequential Circuits

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Example 7.3: Synthesis without Optimization

For our simple synthesis example, we will construct a modulo-6 up counter using T flip-flops having a count
enable input C and an output Y that is asserted when the count is equal to five. The count is to be represented directly
by the contents of the flip-flops.

Step 1: Construct State Diagram

From the above functional description, we need to construct a state diagram that will show the precise operation
of the circuit. A modulo-6 counter counts from zero to five, and then back to zero. Since the count is represented by
the flip-flop values and we have six different counts (from zero to five), we will need three flip-flops (Q2,Q1,Q0) that
will produce the sequence 000, 001, 010, 011, 100, 101, 000, when C is asserted, otherwise, when C is deasserted, the counting stops. In other words, from state 000, which is count = 0, there will be an edge that goes to
state 001 with the label C = 1. From state 001, there is an edge that goes to state 010 with the label C = 1, and so on.
For the counting to stop at each count, there will be edges at each state that loop back to the same state with the label
C = 0. Furthermore, we want to assert Y in state 101, so in this state, we set Y to a 1. In the rest of the states, Y is set to
a 0. Hence, we obtain the following state diagram for a modulo-6 up counter:

C= 0

Q2Q1Q0 = 000
Y=0

C= 1

Q2Q1Q0 = 001
Y=0

C= 1

Q2Q1Q0 = 101
Y=1

C= 1

C= 0

C= 0

Q2Q1Q0 = 010
Y=0
C= 1

C= 1
C= 0

C= 0

Q2Q1Q0 = 100
Y=0

C= 1

Q2Q1Q0 = 011
Y=0

C= 0

Step 2: Derive Next-State / Output Table

The next-state / output table is a direct translation from the state diagram. We have three flip-flops (Q2,Q1,Q0)
and one primary input (C), so there are 16 entries in the next-state table. For each entry in the next-state table, we
need to say what the next state is for each of the three flip-flops, so there are three values (Q2next,Q1next,Q0next) for each
entry. For example, when the current state Q2Q1Q0 = 010 and C = 1, the next state Q2next,Q1next,Q0next is 011.
Since Y is dependent only on the current state, we can add an extra column to the next-state table for the output.
According to the state diagram, Y is asserted only in state 101, so Y has a 1 only in that entry, while the rest of them
are 0s. The next-state / output table for the above state diagram is shown next

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Next State
Q2next Q1next Q0next
C=0
C=1
000
001
001
010
010
011
011
100
100
101
101
000

Current State
Q2Q1Q0
000
001
010
011
100
101

Output
Y
0
0
0
0
0
1

Step 3: Derive Implementation Table

Before we can derive the implementation table, we need to decide on what type or types of flip-flops to use.
Any type or combinations of flip-flops can realize any sequential circuit, although one type might give a more
optimize circuit than another. For example, the circuits of Figure 2 and Figure 3 both give a modulo-4 counter, but
we can clearly see that the circuit of Figure 3 uses fewer gates. We will deal with this question in more detail in
section 7.4. For our current example, we have arbitrarily selected to use the T flip-flop.
The implementation table answers the question of what the flip-flop inputs should be in order to realize the
next-state table. In order to do this, we need to use the excitation table for the selected flip-flop. Recall that the
excitation table is used to answer the question of what the inputs should be when given the current state that the flipflop is in and the next state that we want the flip-flop to go to. So to get the entries for the implementation table, we
substitute the next-state values in the next-state table with the corresponding entry from the excitation table.
The excitation table for the T flip-flop from Figure 7.15 is repeated here
Q
0
0
1
1

Qnext
0
1
0
1

T
0
1
1
0

For example, in the next-state table for C = 1 and the current state Q2Q1Q0 = 010, we want the next state
to be 011. The corresponding entry in the implementation table using T flip-flops would be T2T1T0 =
001 because for flip-flop2 we want its content to go from Q2 = 0 to Q2next = 0. The excitation table tells us that to
realize this change, the T2 input needs to be a 0. Similarly, for flip-flop1 we want its content to go from Q1 = 1 to
Q1next = 1, and again the T1 input needs to be a 0 to realize this change. Finally, for flip-flop0 we want its content to go
from Q0 = 0 to Q0next = 1, this time, we need T0 to be a 1. Continuing in this manner for all the entries in the next-state
table, we obtain the following implementation table
Q2nextQ1nextQ0next

Current State
Q2Q1Q0
000
001
010
011
100
101

Implementation
T2 T1 T0
C=0
C=1
000
001
000
011
000
001
000
111
000
001
000
101

Step 4: Derive Excitation Equations

The next step is to derive the excitation equations for all the flip-flop inputs in terms of the current state and the
primary inputs. These equations are obtained directly from the implementation table and should be simplified. The
three K-maps and excitation equations for T2, T1, and T0 are shown below:

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Chapter 7 Sequential Circuits

T2

CQ2Q0
CQ1Q0

T1

CQ2

Q1 Q0

Page 9 of 14

00

01

11

10

00

01

11

10

T0

CQ2

Q1 Q0

00

01

11

10

00

01

11

10

CQ2'Q0

T2 = CQ2Q0 + CQ2Q1

CQ2
00

01

11

10

00

01

11

10

T1 = CQ2'Q0

Q1Q0

T0 = C

Step 5: Derive Output Equations

From the next-state / output table, we get the output equation below
Y = Q2Q1'Q0

Step 6: Draw the Circuit Diagram

We know that the circuit is a Moore FSM that uses three T flip-flops for its state memory having one primary
input C and one output Y. The next-state function circuit is derived from the excitation equations and the output
function circuit is derived from the output equation. The full circuit is
C

T2

Q2

Clk
Q'2
T1

Q1

Clk
Q'1
T0
Clk

Q0

Clk
Q'0

Example 7.4
We will illustrate the synthesis process with another example. We will design a counter that counts in the
following sequence:
1, 4, 6, 7, 1, 4, 6, 7, .
The count is to be represented directly by the contents of the flip-flops. The counter is enabled by the input C. The
count stops when C = 0. The next-state table, therefore, is

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Next State
Q2next Q1next Q0next
C=0
C=1
001
100
100
110
110
111
111
001

Current State
Q2Q1Q0
001
100
110
111

To do something different, we will use a JK flip-flop, a D flip-flop and a SR flip-flop in this order starting from
the most significant bit for the three flip-flops needed. Converting from the next-state table to the implementation
table requires the excitation tables for the three flip-flops that well be using. The excitation tables from Figure 7.15
are repeated here for convenience.
Q
0
0
1
1

Qnext
0
1
0
1

J
0
1

1
0

D
0
1
0
1

S
0
1
0

0
1
0

Each entry in the implementation table will have five values for the five inputs (J2 K2 D1 S0 R0) needed for our
three flip-flops. The first bit Q2next from the next-state table will convert to the two input bits J2 and K2. The Q1next bit
will convert to the D1 input, and Q0next will convert to the two input bits S0 and R0.
Implementation
J2 K2 D1 S0 R0
C=0
C=1
000
1001
000
010
010
0110
010
100

Current State
Q2Q1Q0
001
100
110
111

From the implementation table, we get the following five K-maps and excitation equations
J2
Q1Q0

D1

K2

CQ2
00

01

11

10

00

01

11

10

CQ2

Q1Q0

00

CQ1

10

CQ2

Q1Q0

00

01

11

10

00

01

01

11

11

10

10

CQ0

K2 = CQ0
R0

CQ2

Q1Q0

11

00

J2 = C
S0

01

00

01

11

10

00

01

11

10

S0 = CQ1

Principles of Digital Logic Design

CQ0'
C'Q1

D1 = CQ0' + C'Q1

CQ2

Q1Q0

CQ1'

00

01

11

10

00

01

11

10

R0 = CQ1'

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From these equations, we get the following circuit diagram

C

J2

Q2

Clk
K2

Q'2

D1

Q1

Clk
Q'1
S0

Q0

Clk
R0
Clk

Q'0

Example 7.5: Modulo-4 Counter using T flip-flops

Next-state table:
Current State
Q1 Q0
00
01
10
11

Next State
Q1next Q0next
C=0 C=1
00
01
01
10
10
11
11
00

Implementation table:
Current State
Q1 Q0
00
01
10
11

Next State
T1 T0
C=0 C=1
00
01
00
11
00
01
00
11

Excitation equations:
T1 = CQ0
T0 = C

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Chapter 7 Sequential Circuits

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T1

Q1

Clk
Q'1

T0
Clk

Q0

Clk
Q'0

7.4

Circuit Minimization of Sequential Circuits

7.4.1 State Reduction

7.4.2 State Encoding

7.4.3 Choice of Flip-Flops

7.5

VHDL for Sequential Circuits

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MooreFSM IS
PORT(
clk
: IN BIT;
cnt
: IN BIT;
Y : OUT BIT);
END MooreFSM;
ARCHITECTURE Behavioral OF MooreFSM IS
TYPE STATE_TYPE IS (s0, s1, S2);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN s0=>
Y <= '0';
IF cnt = '1' THEN
state <= s1;
ELSE
state <= s0;
END IF;
WHEN s1=>

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Y <= '0';
IF cnt = '1' THEN
state <= s2;
ELSE
state <= s1;
END IF;
WHEN s2=>
Y <= '1';
IF cnt = '1' THEN
state <= s0;
ELSE
state <= s2;
END IF;
END CASE;
END IF;
END PROCESS;
END Behavioral;

ARCHITECTURE Behavioral OF MooreFSM IS

TYPE STATE_TYPE IS (s0, s1, S2);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN s0=>
IF cnt = '1' THEN
state <= s1;
ELSE
state <= s0;
END IF;
WHEN s1=>
IF cnt = '1' THEN
state <= s2;
ELSE
state <= s1;
END IF;
WHEN s2=>
IF cnt = '1' THEN
state <= s0;
ELSE
state <= s2;
END IF;
END CASE;
END IF;

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Chapter 7 Sequential Circuits

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END PROCESS;
Y <= '1' WHEN state = s2 ELSE '0';
END Behavioral;

Principles of Digital Logic Design

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