September 2013
Process
Back-End
Process
TM
TM
A conductor carries
electricity like a pipe
carries water.
Conductor
A semiconductor
controls the flow of
electricity like a faucet
controls water.
An insulator stops
the flow of
electricity like a
plug blocks water.
TM
Insulator
TM
"flood gate"
Water
reservoir
(SOURCE)
Water
reservoir
(DRAIN)
The "flood gate" regulates the flow of water between the two lakes (source and drain).
A real transistor switches the flow of electric current on and off instead of water.
TM
water
reservoir
(SOURCE)
water
reservoir
(DRAIN)
n-type
n-type
Only way we can get water from one p-type reservoir to another is by
way of a n-type channel.
By using a capacitor and applying a positive voltage to that capacitor,
we can change the apparent conductivity of the channel from p to n
and turn the transistor on.
In reality, the drain is usually at a lower elevation than the source so
the water will flow downhill to the drain.
TM
Doped
polysilicon
Direction of
current flow
isolation
(oxide)
n+
source
n-
n-
channel
p-type silicon
Cross-Section View
TM
n+
drain
isolation
(oxide)
Capacitor
Isolation
(oxide)
source
drain
Top View
TM
10
VDD
PMOS
IN
Normally ON
OUT
NMOS
Normally OFF
IN
GND
V
0V
Vdd
TM
OUT
Logic
0
1
11
V
Logic
~Vdd 1
0V
0
Digital devices do not deal in the values of actual voltages; rather, they
simply detect the presence or absence of a voltage. The presence of a
voltage is represented digitally as a 1, with the absence represented as a
0. These 1s and 0s can be processed and manipulated digitally with great
flexibility.
Mixed Signal These devices include both analog and digital circuitry.
Mixed signal devices are difficult to design and build, but bring the benefits of
both analog and digital processing together.
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12
Memory Memory devices are used to store data either for short periods of time
or permanently. Includes volatile (DRAM, SRAM) and non-volatile (flash, ROM)
memory.
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15
Multi-die SiP
Semi-Discrete Solution
Standard MCU
Single package
Die-to-die bonding
Application Specific
Analog IC (ASIC)
TM
17
Monolithic SiP
Z axis
Elements
X axis
Elements
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18
Harmems, Interdigitated
X and XY Sensing
g-cell cap
Wire bonds
g-cell device
1.98mm
ASIC
Lead Frame
6 mm
Automotive Qualified Package:
In production since 2006
ASIC
Die
g-Cell
Die
TM
19
G-Cell Die
ASIC Die
Mold Compound
TM
20
CAN
Door Lock
H-bridge
Door Lock
H-bridge
Door Lock
H-bridge
Door Lock
H-bridge
System
Basis Chip
SBC
Timer
CAN
CAN
CAN
Transceiver
CAN
CAN
Transeiver
LIN
LIN Transeiver
LIN
LIN Transeiver
LIN
LIN Transeiver
PWM
Watchdog
MCU
S08
ADC
Real
Time
Clock
MCU
MPC5xxx / S12x
Multiplexer
MSDI
Multiplexer
MSDI
Multiplexer
MSDI
UHF
Transceiver
MC33696
Amplifier
Antenna
LIN
SPI
High-side e-switches
Low-side switches
LED Drivers COSS
TM
Warning LEDs
21
Internal Lighting
Horn
External lighting
LED control
Seat control
Various Outputs
Compute Engine
Analog Signal Conditioning
Low Voltage
Core/NVM
High Voltage
Protection
Power Drivers
Mother Nature
TM
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23
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24
5 million transistors
2 polysilicon layers
0.25 m technology
Red CPU
Blue ETPU
Green EQADC
Purple DSPI
Yellow EMIOS
Orange FlexCAN
White EBI
Magenta JTAG
Grey SCI
ADC
Flash
RAM
PLL
TM
25
NVM Bitcell
TM
Logic
26
55 nm is 1/2000th the
width of a human hair
0.5 um
27
Physical
overview
Layout Rules
Electrical
specifications
Reliability
TM
28
Process Options
Individual
Allowed
device offerings
Metallization
options
process flow
TM
29
Poly
Active
Rule
Description
Value
Active-poly distance
>0.05um
Active-poly corner
>0.1um
>0.16um
TM
30
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31
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32
TM
Chemical deposits
Poly/Nitride/TEOS Coat
Oxide Growth
Silicon Wafer
Chemical deposits
IC manufacturing uses a
recursive deposition and
masking process to define
patterns of doped areas,
isolation films and metal
conductors to create solid state
devices.
TM
Substrate
34
Metals/Films
connects devices
electrically and isolates
circuit pathways.
Probe/Test
test device
functions
Room Temp
Probe
TM
Hot Temp
Probe
Dicing
(for KGD)
35
Outgoing
Inspection,
Pack & Ship
Doped
polysilicon
Direction of
current flow
isolation
(oxide)
n+
source
n-
n-
channel
p-type silicon
Cross-Section View
TM
36
n+
drain
isolation
(oxide)
Purification operations
SiO2 + C
Si + CO2
Si + 3HCl
SiHCL3 + H2
SiHCL3 + H2
Si + 3HCl
The white sand of Abel Tasmans beaches in New Zealands South Island
is a typical source of silicon dioxide.
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38
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39
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40
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41
The Process
Design Driven
Increased complexity
TM
42
No OPC
With OPC
Optical Proximity
Correction (OPC)
Mask
Printed
Mask
Printed
Quartz
recess
Chrome
TM
43
Approximately 3%
of the wafer
thickness
Contaminant-free
for the subsequent
construction of
transistors
TM
44
45
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46
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47
Dispenses
Wafers receivers
Hot plate
Loading
Unloading
Track 1
Track 2
Control keyboard
TM
48
Mercury Lamp
Shutter
Reticles
Storage
Reticle
Lens
Wafer Stage
Wafer
Loading /Unloading
TM
49
Wafers receivers
Dispense
Loading
Track 2
Un loading
Track 1
Control panel
TM
Hot plates
50
TM
51
Process gases
Process
chamber
under
vacuum
Radio frequency
power supply
Ionized
Gas
ETCH
Exhaust management
Wafers with resist
Vacuum system
45:00
45:00
45:00 45:00
Acid
Acid
QDR
QDR
Process control
QDR
Heating
element
Rinse
TM
52
TM
53
Exhaust
GAS
Gases Management
Vertical Furnace
TM
54
Gas
box
Source
Ion Accelerator
Ion Accelerator
Too light ions
Loading
Machine Management
TM
55
optical
mask
oxidation
photoresist
removal (ashing)
process
step
TM
photoresist coating
stepper exposure
acid etch
56
photoresist
development
Contact locations
p-w ell
n-w ell
n-channel
transistor
p-channel transistor
p+ substrate
Process Conditions
Temperature: Piranha Strip
is 180 degrees C.
RCA Clean
1 Organics 2 Oxides
H2SO4 +
H2O2
H2O Rinse
HF +
H2O
H2O Rinse
3 Particles 4 Metals
NH4OH +
HCl +
H2O2 + H2O H2O2 + H2O
H2O Rinse H2O Rinse
5
5 Dry
H2O or IPA +
N2
Piranha Strip
H3PO4
Oxide Strip
HF + H2O
H2SO4 + H2O2
TM
57
N2O
NMP
O2
Proprietary Amines (liquid)
CF4 + O2 Dry Cleans
O3
HF
O2 Plasma
Alcohol + O3
TM
58
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59
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60
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61
Process Chamber
EtchChamber
2
1
Heating
Chamber
Aluminium
Target
Gas:
Argon
Al Sputerred
Load-lock
Vacuum Pump
TM
62
Cause
Compromise
etch uniformity
Compromise
TM
63
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64
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65
Cleared Bond
Pad Opening
POLYIMIDE
POLYIMIDE
SION exposed
to Pad Clear
Etch
150 PEN
MHAT Fuse
150 PEN
4500 SION
METAL 4
METAL 4
Via 3
Via 3
SION
PEN ESL
PETEOS
METAL 3
METAL 3
Via 2
Via 2
PEN ESL
METAL 2
METAL 2
Via 1
Via 1
PEN ESL
METAL 1
METAL 1
TEOS+SION
LI
LI BAR
LI
LI
BPTEOS
ESL
n+
n+
n+
P-Well
Epi 2.0 m
P + Substrate
TM
66
P+
P+
N-Well
TM
67
1.
Silicon substrate
2.
Oxide growth
3.
Oxide etching
4.
Deposition of
structural layer
5.
Structural layer
etching
6.
Oxide removal
TM
68
AG004
FNF
CDs
CDs
PID4
Product Die
BE753
RO101
TM
BE750
G210
OPN01
Label IDs
BE123
BE701
FE04
C90_OPCTP
T100A
T110A
FE50
Product Die
PID4
SIMS
PID3
PID3
IRPR3
Product Die
TS300
TS400
FE49
G110
C100
C110
FNF
PRB01
TS311
FNF
Product Die
T182
T192
BITL5
Product Die
Product Die
TS311
T100
R0111
T110
LCAP8
C90SOI_RLM_RO
C110A
CDs Scat
BITP2
BITP3
BITL4
TS311
BE752
BE102
FE48
Product Die
BE145
TS301
BE767
TS401
C90_OPCTP BE700
Product Die
FE47
C22
CDs
IRPR1
Product Die
ESD17
C180
C190
BITM1
PRB01
BITD1
BE751
FE05
CDs
TS311
Reticle
field
Product Die
PID1
Product Die
PID1
Product Die
CDs
FNF
TS311
Transistors
Metal to
metal
linkage
Contact
chains
Via chains
Resistors
Capacitors
Gate Oxide
Probe pad
Metal 1
Probe pad
D05 Gate
Active
TM
Probe pad
Probe pad
70
pwell contact
2
1
Rotated table
Unloading
TM
71
Loading
TM
Air
Air
Air
Air
Recirc
Recirc
Recirc
Recirc
Air
Recirc
Interstitial
ULPA Ceiling
Work
Zone
Class 1
Work
Zone
Class 1
Utility Zone
Class 100
Process
Tool
Process
Tool
Fan Deck
Center
Corridor
Work
Zone
Class 1
Utility Zone
Class 100
SEM,
Computer Center,
Smock Rooms
Work
Zone
Class 1
Process Level
Process
Tool
Process
Tool
Raised Floor
Exhaust
HPM Rooms
Piping
Ele
c.
Electric
Rooms
Exhaust
Subfab
Piping
Support
Tools
Support
Tools
Crawl Space
TM
73
Ele
c.
Maintenance Shops
Parts, Quartz,
Wafer Storage
TM
74
First stage makeup air pre-filters are 30% efficient for 3-10um
sized particles.
TM
75
Implant
Etch
4.2k sf
Polyimide
5.8k sf
Probe
9k sf
Diffusion/
Cleans
10k sf
Lot
Start
Ship
Implant
Diffusion/
Cleans
6.6k sf
Implant
Cleans
CVD
4k sf
ETCH CLNS
Metals
PVD
11 k sf
Photo
i - line
7k sf
Gown
2.1ksf
MRAM
Probe
27k sf
YE
2.5k sf
CMP
22k sf
Photo
DUV
6.1k sf
ETCH
8.2k sf
Metals
(W,RTP)
TM
Implant
23k sf
Epi
Photo
6.5ksf
C Bldg
Analytical
8.3k sf
CVD
(TEOS,
PAS)
5.6k sf
76
85,000+ square feet of sub-class 1 clean room space supporting wafer capacity of
6,000 WPW
Factory moves ~6,400,000 CFM, enough to fill 120 hot air balloons every minute
Factory has more than 17 miles of stainless steel piping and more than 50 miles
of electrical wiring
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78
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79
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80
2000
4"
8"
45%
10%
12%
5"
2012
33%
6"
6"
13%
2016
52%
6"
29%
8"
10%
8"
12"
Source: Gartner (March 2012)
61%
12"
Source: Gartner (March 2012)
TM
81
24%
MSI
3,000
2,500
2,000
1,500
1,000
500
0
4Q97
4Q98
4Q99
4Q00
4Q01
4Q02
4Q03
100 mm
4Q04
125 mm
4Q05
150 mm
TM
82
4Q06
4Q07
200 mm
4Q08
300 mm
4Q09
4Q10
4Q11
4Q12
4Q13
productivity
Enhanced
TM
83
TM
84
Increase partnership
Low Power
CMOS
HPSOI
High
Performance
SOI
CMOS
LP / GP
Packaging
e-Non
Volatile
Memory
LP-Bulk
TM
RF
CMOS
TM
SmartMOS
Sensors
Research
Power &
Analog
TM
GaN
GaAs
RF
Increase differentiation
TM
85
TM
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87
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88
Process Description
Epoxy is dispensed in the die flag area of the
substrate in a specified pattern (usually star)
followed by a pick and place process that
removes the die from the tape carrier and
places it over the dispensed epoxy.
Die Bond Cure Process
Substrates are placed in a nitrogen purged
oven. During the cure time, the epoxy resin
completes the cross linking process to form a
rigid material. Nitrogen is used to replace the
trapped air/moisture that may interfere with the
cross linking process.
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90
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91
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92
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93
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94
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95
TM
$350
+5%
-2% to
to +6%
-4%
Billions of Dollars
$300
$250
$200
$150
$100
$50
$0
'84 '85 '86 '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12 '13
TM
97
46
50
42
38
40
29
30
Average Growth
2001-2011: 8.0% per Year
37
32
23 23
19
20
10
32
28
8 10
18
-3
-10
-20
-9 -8
-9
-2
-17
-30
Semiconductor Market
Billions of Dollars
-40
2000
$204
-50
'84
'86
2001
$139
'88
-32
2002
$141
2003
$166
2004
$213
2005
$227
2006
$248
'92
'94
'96
'98
'00
'90
TM
98
'02
'04
'06
'08
'10
'12
Asia
Pacific
55
50
45
40
35
30
25
China
Americas
Japan
20
15
Europe
10
'96
'97
'98
'99
'00
'01
'02
'03
'04
'05
'06
Years By Quarter
Source: WSTS
TM
99
'07
'08
'09
'10
'11
'12
Electronics revenues
CAGR 2007-11: 1%
CAGR 2001-11: 3%
CAGR 1991-11: 3%
Semiconductor content
Semiconductor revenues
Source: IHS iSuppli, Q212; WSTS
TM
100
1000
100
10
SC Market
Annual Trend Growth
1970s 18%
1980s 16%
1990s 14%
2000-06 7%
2000-10 4%
0.1
1970
1975
1980
1985
1990
1995
Years By Quarter
101
2000
2005
2010
8%
40%
22%
1%
11%
18%
TM
102
Automotive
Communication
Consumer
Industrial
Military
Data Processing
15%
20%
5%
7%
8%
26%
3%
14%
TM
103
2%
MPU
MCU
DSP
Logic
Analog
Sensors
Opto
Discretes
Memory
Automotive Market
Overall Market
MPU:14%
MCU:5%
DSP:3%
Logic:26%
DRAM:12%
Flash:
9%
Analog: 14%
Discretes:
Sensors: Opto:6%
7%
2%
Other
Memory:
2%
Logic
Memory
Discrete
Analog
Sensor
Opto
MCU
24.3%
4.8%
13.2%
12.8%
10.2%
4.8%
29.8%
TM
104
Automotive
Industrial
Consumer
Multimedia
processors
Wireless
Handsets
Networking
Infrastructure
Multimedia processors
Microcontrollers
Communication
processors
Embedded microprocessors
Control
processors
TM
105
RF, PA and
baseband
Capacity
Total
Demand
Other Markets
Demand
Factory Closure
or Obsolete
Technology
Automotive
Demand
Qual
Samples
(+10-20 years)
Ramp
Customer
Qual Cycle
(2-3 years)
TM
Time
106
TM
MC68HC11
MC68F333
2T-S Flash
EEPROM
1.5T Flash
MPC555
MPC565
MPC5554
CDR1
CDR3
Scale Drawing
High Density
ETOX Flash
High Density
TM
ETOX Flash
130nm
108
1T Fl as h
High Density
CDR1 0.35m
FN/FN 1T
2.7m2
HiP7 130nm
HCI/FN 1T
0.359m2
CDR3 0.25m
HCI/FN 1T
0.995m2
CMOS90
HCI/FN 1T
0.18m2
TM
109
CMOS55 CMOS40
HCI/FN 1T HCI/FN 1T
<0.15m2 < 0.1m2
MPC555
Black Oak
MPC565
Spanish Oak
MPC5554
Copperhead
CDR1 0.35u
448K Flash
CDR3 0.25u
1MB Flash
HIP7 0.13u
2MB Flash
14 million transistors
34 million transistors
7 million transistors
TM
110
8 Output Switch
0.375 ohm
SMARTMOS 2.5
TM
16 Output Switch
0.375 ohm
SMARTMOS 5AP
111
Frequency
Test
time
EMC
components
Capital
equipment
Frequency
Package
Die Test
Package
Machinery
Board
size
Capital
equipment
Tier 1
volume
Silicon $
TM
Tier1 $
112
Micro $
TM
3000
2500
2000
1500
1000
500
0
10
30
50
70
90
110
130
150
170
190
210
230
250
270
290
310
330
350
370
Upper
limit
12
15
18
21
24
27
30
outliers
TM
114
Median
95th percentile
Upper limit
12
15
18
21
24
27
Calculation:
SBL = Median + K*Robust Sigma
30
Outliers
Specification window
Typical distribution
Static PAT
Statistical test limits are set in the
probe program to screen outlier
die.
Limits are reviewed every 3-6
months (Product Volume
dependent)
TM
Outliers
* **
Spec Limit
PAT Limit
115
**
** *
**** *
* **
**
**** *
* *
* ** *** * **
Typical product
Outliers
***
PAT Limit
Spec Limit
Before
TM
After
116
The problem description is first described at the system level (Die level failure description)
Data is collected to isolate the failure to a sub system (Functional Blocks within a device)
Analysis continues, eliminating all the possible causes until the source of the failure is identified
Electrical
Failure
Analysis
Process
Freescale
test
diagnostic
Specific circuit
element fault
5-30M
500k
1-2
Transistors
Transistors
Transistors
TM
117
Defect
causing
circuit fault
Known Good Die (KGD) analysis samples are typically returned to Freescale still
attached to the target application. The die must be removed and packaged for
analysis and protection of the die. Due to the fragile nature of the die, a visual
inspection is performed at each step to ensure device integrity.
Wirebonds pulled
Die encapsulation in epoxy
Customers board is milled down from the
backside until the die is freed from the target
application
Die removed from epoxy encapsulant
Milling/Die extraction
As received state
PBGA Package
TM
118
TM
119
After completion of the electrical verification, the device is submitted to the Product Analysis Lab
Duplicate reported Failure Mode found in physical analysis lab compared to correlation device.
Decapsulation (removal of top of plastic package to expose die surface) / Visual Inspection
good samples.
Full Die
Isolated
Resistance
change
Step 2: Microprobe
120
Microprobe Station
TM
121
In order to collect data via microprobe, the Analyst needs to be able to access various circuit nodes within the die.
Conceptually can be thought of as an electric knife or a microscopic Mill/Drill. Removal rate is measured on the order of
molecules.
Node to measure
Die Cross-section
Platinum
Plug
TM
122
Once the analyst has isolated the failure to a single circuit element, physical analysis begins.
There is no turning back once physical analysis begins as the device will no longer be
functional.
P assiva tio n
Pa ssiva tio n
M etal3
I L D2
M etal1
I L D1
DM06eta l1
ILD0
LI_BA R
L I_B A R
I L D0
L I_ SQ UA RE
L V N W ELL
H V P W e ll
H V N W el l
L I_B A R
H V P W el l
H V N WD eeE pL NL W e ll
L V PW EL L
H V P W e ll
H V N W el l
I L D0
LI_BA R L I_ SQ UA RE
ILD0
LI_ SQ UA RE
Z - d e v ice
LV PW ELL
L V N W ELL
LV PW ELL
Z - d e v ice
H V NW E LL
L V PW EL L
L V PW EL L
L V N W ELL
H V P W e ll
H V NW E LL
H V N W el l
H V P W e ll
H V N W el l
3.4um EPI
L in k I I
A r ra y l in k I m p la n t
LV N M OS
3. 4um E PI
P+ + Substra te
D ee p N W e ll
LV N M OS
L in k I I
L in k I I
L in k II
D ee p N W e ll
L in k II
3. 4um E PI
P++ S ubstrate
P+ + Substra te
M etal1
P o ly 1 a c c es s
A r ra y l in k I m p la n t
D ee p N W e ll
L in k I I
D 19
M etal1
L I_ SO UR CE B A R
LI_ SO UR CE BA R
D 06
A(Isol
rr a ated
y W e) ll
L in k II
LV N M OS
LV NMOS
Meta l1
ILD0
P o ly 1 a c c ess
A(Isolated
rr a y W e) ll
Z - d e v ice
LV NMOS
ILD1 M eta l1
I L D0
H V PW ell
H V NW E LL
L V PW EL L
L V N W ELL
L in k II
M etal2
D 19
I L D1
M etal1
Z - d e v ice
LV PW ELL
M etal2
M etal2
D 06
I L D0
LV N M LOSV P W E L L
M etal2
L I_ SO UR CE B A R
ILD0
LI_ SQ UA RE
M eta l3
A 29
ILD2
D 19
LI_ SO UR CE BA R
D 06
M eta l3
M etal3
A 29
M etal2
M etal2
Meta l1
A r ra y l in k I m p la n t
A r ra y l in k I m p la n t
3.4um EPI
P++ S ubstrate
HV Z-DEVICE
LV PMOS
LV PMOS
HV NMOS
HV Z-DEVICE
HV PMOS
HV NMOS
Array
HV PMOS
P+ + Substra te
P+ + Substra te
LV
LVPMOS
NMOS
HV Z-DEVICE
LV PMOS
Array
LV NMOS
HV NMOS
HV Z-DEVICE
ILD0
LI_SQ UA RE
Z - d e v ice
Z - de v ice
LV PW ELL
L V N W ELL
L V PW EL L
H V PW ell
H V NW E LL
H V P W e ll
H V N W el l
P o ly 1 a c c ess
LV PW ELL
L V N W ELL
L V PW EL L
H V PW ell
H V NW E LL
H V P W e ll
H V N W ell
Z - de v ice
P ol y 1 a c c ess
A(Isolated
rr a y W e) ll
LV PW ELL
A r ra y l in k Im p la n t
L ink II
L V N W ELL
L V PW EL L
H V PW ell
H V N W ell
P ol y 1 a c c ess
Z - d e v ice
LV PW ELL
A(Isolated
rr a y W e) ll
L in k II
L in k I I
L in k II
L ink II
H V N W ell
P++ Substrate
P ++ S ubstrate
P ++ S ubstrate
LV NMOS
HV PMOS
P ol y 1 a c c es s
A(Isol
rr a ated
y W e) ll
A r ra y l in k I m p la n t
3. 4um E PI
P++ Substra te
P++ Substra te
HV NMOS
H V P W e ll
3.4um EPI
3.4um EPI
A r ra y l in k I m p la nt
P++ S ubstrate
HV Z-DEVICE
H V P W el l
H V NW E LL
L in k I I
A r ra y l ink Im p la nt
3.4um EPI
LV PMOS
L V PW EL L
D ee p N W e ll
L in k II
P+ + Substrate
LV NMOS
L V N W ELL
D ee p N W e ll
D ee p N W e ll
L ink II
H V P W e ll
H V NW E LL
A(Isolated
rr a y W e) ll
D ee p N W e ll
LV NM OS
LV NMOS
LV PMOS
HV Z-DEVICE
HV NMOS
HV PMOS
LV NMOS
Array
LV PMOS
HV Z-DEVICE
HV NMOS
HV PMOS
LV PMOS
P ++ S ubs trate
HV Z-DEVICE
HV NMOS
HV PMOS
Array
Array
Array
Deprocessing Complete
Typically 1-5 days to
complete
TM
Z - d e v ice
H V P W el l
A(Isol
rr a ated
y W e) ll
Z - d e v ice
A r ra y l in k I m p la n t
3. 4um E PI
3. 4u m E PI
P++ Substra te
P++ S u b stra te
LV NMOS
123
LV PMOS
P ++ S ubs trate
P ++ S u bs trate
HV Z-DEVICE
HV NMOS
HV PMOS
Array
LV NMOS
LV PMOS
HV Z-DEVICE
HV NMOS
HV PMOS
Array
ArrayArray
TEM
TEM
TM
124
Completed cross-section
TM
Flexible Sourcing
Exit 150mm
200mm Internal/External
300mm External
Front-End
Manufacturing
Flexible Sourcing
Back-End
Manufacturing
TM
126
Freescale Tianjin
Final Manufacturing
Tianjin, China
AMERICAS
ASIA PACIFIC/
JAPAN
Freescale Kuala
Lumpur Final
Manufacturing-Kuala
Lumpur, Malaysia
TM
127
TSMC
Fab11
Dalsa
IBM
KES
TSMC, UMC,
ASE, Amkor,
Global Test
Amkor, ASE,
StatsChipPac
Tower
AMERICAS
EMEA
ASIA PACIFIC/
JAPAN
Amkor
StatsChipPac,
Carsem
Global Foundries,UMC,
StatsChipPac
Die Manufacturing
Probe, Assembly & Test
TM
128
Manufacturing: The
Right Model
Maximize
Efficiency
Key priorities
Customer
Success
Quality
Best
Partner
Aggressively
Cost
Asset
Utilization
Flexibility
& Assurance of
Supply
TM
129
Cross
Qualifications
Sourcing
Technology
Internal
TM
130
External
External Foundries
TM
Locations
Key Technologies
Taiwan, U.S.
Singapore, Dresden
Taiwan, Singapore
U.S.
High Performance
Canada
Sensors, Analog
Malaysia
Taiwan
GaAs
131
External Foundries
NFME
KES
TM
Locations
Key Technologies
Taiwan, Korea,
Philippines
Korea, Philippines
Malaysia, Korea,
Singapore
MAPBGA, PBGA
China
Malaysia
QFN
China, Malaysia
132
TM
133
TM