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MOSFET Operation

Day 11-12
ECE3030
Jeff Davis

CMOS Transistors!
(Complementary MOSFET)
p-channel MOSFET
acts like normally
closed switches
VDD
b

n-channel MOSFET
acts like normally
open switches

b
GRD

nMOS (or nFET) Transistor!


(Switch level model)
n-channel MOSFET acts like normally open switches
gate voltage = LOW
drain
drain

source

gate

source

gate voltage = HIGH

drain

source

pMOS (or pFET) Transistor!


(Switch level model)
p-channel MOSFET acts like normally closed switches
gate voltage = LOW
drain
source

drain
gate

gate voltage = HIGH

source

drain

source

A new device: MOSFET!


glass (silicon dioxide)

Gate

Source

Drain

M(etal)

silicon wafer surface

O(xide)

Add lots phosphorus to


source and drain junctions.

channel

n+

n+
S(emiconductor)
p

Band Diagram ACROSS the Channel


Gate
Source

Drain

x
channel

(in equilibrium)
Source
channel
EF

Drain

EC

Ev
x

Apply Voltage Across Drain and Source


Vdd

Vdd
Drain

Gate

+
VDS

Source

gate voltage = LOW

Band Diagram Long Channel Device


VG = 0
Unbiased Bias Junction

Ec

Ev

Unbiased Junction

VDS = 0

Band Diagram Long Channel Device


VG = 0
Unbiased Bias Junction

Ec

Unbiased Junction

VDS = 0
VDS = small voltage

Ev

Band Diagram Long Channel Device


VG = 0
Unbiased Bias Junction

Ec

Unbiased Junction

VDS = 0
VDS = small voltage

Ev

VDS = large voltage

Leakage Currents
VG = 0
Unbiased Bias Junction

Unbiased Junction

Ec
-

VDS = 0
VDS = small voltage

Ev

Drain-Induce Barrier Lowering


(DIBL) can occur on the source
junction as the drain junction
gets closer to the source!

VDS = large voltage


pn junction
leakage at reverse
bias drain junction

DIBL with 45nm Devices

Lau,Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100nm metaloxide-semiconductor transistors, Microelectronics Reliability, vol. 49 (2009)p. 1-7.

Band Diagrams for MOSFET

Simultaneous View of Both Directions

2 things we must understand!


1. MOS Capacitor

M(etal)
O(xide)
S(emiconductor)
n+

n+

2. MOSFET Channel Conduction


15

MOS Capacitor
Gate voltage VG

Metal Gate

Insulator

Semiconductor

Substrate grounded!
16

Example Calculation
Assuming for the moment that the semiconductor acts like a good conductor,
what is the capacitance of a MOS capacitor that has a gate length of 180nm and a
transistor width that is 10x the length. Assume that the oxide thickness is 5nm.
L = 180nm
180nm Technology
VDD = 1.8V
L = 180nm
xox = 5nm

xox = 5nm

C ox =

x ox

O(xide)

Z = width

S(emiconductor)

Special Parameter, Cox


K SiO2 o

M(etal)

(3.9)(8.85e 14[F /cm])


5e 7[cm]

C ox = 6.903e 7[F /cm 2 ]

capacitance per unit area!

Total Capacitance, Cgate

C gate = Cox ZL = (6.903e 7) *10 * (180e 7cm)(180e 7cm)


C gate = 2.236e 15[F ] = 2.236[ fF ]

gate capacitance estimation

Work Function/Affinity
Vacuum Level

Electron Affinity

M = work function of the metal


S = work function of the semiconductor
18

MOS Materials Capacitor

19

MOS Capacitor
Assumption of this discussion

M = S

20

MOS Capacitor Under Bias

21

Accumulation
VG > 0 with n-type substrate

These are referred to


as quasi-fermi levels!

VG

n
Accumulation of MAJORITY carriers!

M(etal)
O(xide)

e- e- e- e- e- e- e- e- e- e- e- e- e- e-

n = e(Fn Ei )/ kT
p=e

(Ei Fp )/ kT
22

Depletion
VG < 0 for n-type substrate

Depletion region forms at surface of semiconductor!

23

Inversion
VG < VT for n-type substrate
Note that VT is negative for this case!

pinterface = ND

n = e(Fn Ei )/ kT
p=e

(Ei Fp )/ kT

Inversion layer of minority carriers (holes) is created


at surface!
24

Strong Inversion
VG << VT for n-type substrate

n = e(Fn Ei )/ kT
p=e

The number of minority carriers (holes) at surface is increased


significantly!

(Ei Fp )/ kT
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Bias Types for P-type Material


ACCUMULATION

DEPLETION

INVERSION

26

Surface Potential
(x) = electrostatic potential inside the
semiconductor at a depth x

1
(x ) = [Ei BULK Ei (x )] electrostatic potential
q
and

P-type Example

1
[Ei BULK Ei INTERFACE ] surface potential
q
along with,
1
F = [Ei BULK EF ]
q
S =

Reference taken at the bulk!


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Condition for Threshold Voltage


Surface potential that gives a concentration at the Si/SiO2 interface that is
the same as the concentration in the bulk.

s = 2 F
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Condition for Threshold Voltage

p BULK = ni e

(Ei BULK EF )
kT

= NA

(EF Ei BULK )

and n BULK = ni e

kT N A
ln
for a p-type semiconductor

q ni
F =
kT ln N D for a n-type semiconductor
q n
i

kT

= ND

29

Example Calculation
Find the Fermi potential in the body of the n-channel transistor assuming that
the channel doping concentration is 1015 cm-3. Assume the room temperature
intrinsic carrier concentration is given by 1.45e10 cm-3.
We know by definition that the channel is p doped because it is an nFET.

N A = 1015 cm 3
Solving for the Fermi potential gives the following:

F =

kT
N
ln( A )
q
ni

(1.38e 23 J/K)(300 K)
1015 cm-3
F =
ln(
)
-3
1.6e 19C
1.45e10cm

F = 0.2885V

Example Calculation
For the previous example how much band bending do we need to have to
reach the threshold condition? More specifically what is the surface potential
at threshold?
We know the threshold condition is set when the surface potential is
twice the Fermi potential in the body of the transistor.

s = 2 F
From the previous example we can know that the Fermi potential in the body is:

F = 0.2885V

s = 2(0.2885) = 0.577 V

What is the GATE voltage that


gives this surface potential!
s = 2 F

Surface Potential and Gate Voltage


Relationship
VG=oxide+S
Potential drop across
oxide
Potential drop across the
bulk (which is surface
potential)

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What about voltage drop across the


oxide?
VG=oxide+S

Q=CV

oxide

QB ZL
=
C ox ZL

M(etal)
O(xide)

- - - - - - - - - - - - - - - - - - -

Z = transistor width
L = transistor length

Depletion region is formed first!


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What is the relationship between surface


potential and gate voltage!
(Note that this assumes FREE inversion charge is much less than FIXED charge in channel.)

VG = s + oxide
Remember this is the surface
potential!

C ox

oxide
K SiO2 o
=
x ox

Q=CV

QB qN AW
=
=
Cox
Cox

M(etal)
O(xide)

- - - - - - - - - - - - - - - - - - -

xox

W=

2K S o s
qN A

This is an expression for the


width of the depletion region!
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Example Calculation
What is the width of the depletion region when the surface potential is at the
threshold condition? Assume the doping in the channel is 1015 cm-3 Assume that
the KSiO2= 3.9, KS = 11.9, and o = 8.85e-14 F/cm.

W=

2K S o s
qN A

From the previous example we can know that the surface potential at threshold is:

s = 2(0.2885) = 0.577 V
The width of the depletion region at threshold is given by:

W =

2 * 11.9 * 8.85e 14 * 0.577


1.6e 19 * 1015

W = 8.715e 5 cm = 0.8715 microns

What is the relationship between


surface potential and gate voltage!

37

What is the relationship between surface


potential and gate voltage!
2qN A K s o s
VG = s +
xxoox
K SiO2 o
VG

Threshold voltage!!!

= 2 F

2qN A K s o 2 F
= VT = 2 F +
xxoox
K SiO2 o

2kT N A
2 F =
ln
q
ni

p-type

38

Example Calculation
Calculate the threshold voltage for an nFET. Assume the doping in the channel is
1015 cm-3 Assume that the KSiO2= 3.9, KS = 11.9, and o = 8.85e-14 F/cm. Assume
180nm technology specifications that have been outlined in previous graphs.
We have already calculated the Fermi potential for this doping to be:

F = 0.2885V
The estimation of the threshold voltage for this case is:

2qN A K s o 2 F
VT = 2 F +
x ox
K SiO2 o
2(1.6e 19)(1015 )(11.8)(8.85e 14)2(0.2885)
VT = 2(0.2885) +
5e 7[cm]
(3.9)(8.85e 14)

VT = 0.576 + 0.02011 = 0.596[V ]

Threshold Voltage Expressions for nFET and pFET

VT = 2 F +

S
C ox

2qN A
(2 F ) (for n - channel devices)
S

VT = 2 F

S
C ox

2qN D
( 2 F ) (for p - channel devices)
S

where,
C ox =

ox
xox

is the oxide capacitance per unit area

S = K S o

ox = K SiO2 o

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Qualitative Description MOSFET


Current

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MOS Transistor
Qualitative Description

Electron flow from Source to Drain is controlled by the Gate voltage.


n-channel MOSFET =
nFET or nMOS
transistor

Change
conductivity of
channel region

Control by the GATE voltage is achieved by modulating the CONDUCTIVITY of


the semiconductor region just below the gate.
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N-channel MOS Transistor


Qualitative Description

MOSFETs WONT WORK


IN ACCUMULATION!
VGS < 0
(accumulation)
The source to drain path consists of two back to back diodes.
One of these diodes is always reverse biased regardless of the
drain voltage (I.E. VDS) polarity holes wont flow!

P-type

N-channel MOS Transistor


Qualitative Description

0<VGS <VT
(depletion  CUTOFF)
There is a deficit of electrons and holes making the channel very
highly resistive. => No Drain current can flow.

High due
to Depletion

For ANY value of VDS:


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N-channel MOS Transistor


Qualitative Description
VDS = 0
VGS > VT

An induced n- type region, an inversion layer, forms in the channel and


electrically connects the source and drain.

Inversion layer (n-type)

P-type
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N-channel MOS Transistor


Qualitative Description
Small positive VDS
VGS > VT(continued):
The induced n- type region allows current to flow between the source and drain.
The induced channel acts like a simple resistor. Thus, this current, ID, depends
linearly on the DRAIN voltage VD. This mode of operation is called the linear or
triode* region.

Inversion layer (n-type)

P-type
46

N-channel MOS Transistor


Qualitative Description
Small positive VDS
VGS > VT(continued):

Drain current verses drain voltage when in the linear or triode* region.

Linear region

47

N-channel MOS Transistor


Qualitative Description
Reduced electron concentration in the
Inversion layer near the drain

VGS > VT

P-type

Leads to current
starting to roll off
for larger VDS.

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N-channel MOS Transistor


Qualitative Description
Channel Conductivity starts to pinch off near the drain!

Saturation region
Linear Region

This occurs when


VG - VD = VT

IDsat

VDsat = saturation voltage = VGS-VT

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Channel changes as we increase VDS!


(Assume VG is greater than the threshold voltage)

VDS = 0

VDS < VD,SAT

VDS =VD,SAT

VDS > VD,SAT

MOS Transistor
Qualitative Description
Finally,
ID-VDS curves for various VGS:

VDsat depends on VG
51

Quantitative Current Model!

52

Effective Surface Mobility

Surface scattering REDUCES Mobility!

BULK VALUE

n = 1350

Average Surface VALUE

n = 200
53

Quick Estimation

Inversion Charge Estimation


QI = Cox (VGS VT )
Below threshold applied voltage produces BULK charge NOT free charge!

QI = Cox (VGS VT )

L
I=

Charge in Channel
time to move charge out of channel

C ox (VGS VT )ZL
I=
t

L
vd =
= E field
t

Z
I = C ox (VGS VT )VDS
L

L2
t =
Vdd

E field

Vdd

Zeroth Order Capacitor Current Model

IDS

Saturation region
Linear region

I Cox

Z
(VGS VT )VDS
L

I Cox

VDS = VGS - VT

Z
(VGS VT )2
L

VDS
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Is there a better model?

58

Observation: Inversion Charge is not


always UNIFORM in Channel
VDS = 0

VDS < VD,SAT

VDS =VD,SAT

Inversion Charge is not Uniform!

Source

MOS Capacitor

QN Cox VGS VT

for VGS VT

Neglect the depletion region charge

Drain

MOS Transistor

QN Cox VGS VT

for VGS VT

60

First Order Square Law Model LINEAR REGION


Z n
ID =
L
Z n
ID =
L

= VDS

= VDS

= 0

= 0

QN d
Cox (VG VT )d

Z nCox
VDS
ID =
(VGS VT )VDS

L
2

0 VDS VDsat

and VGS VT

This is known as the square law describing the Current-Voltage


characteristics in the Linear or Triode region.

61

First Order Square Law Model SATURATION REGION

For VDS>VDsat

I D = I Dsat

Z nCox
VDsat
=
(VGS VT )VDsat

L
2

VDsat VDS

But,

QN (y = L) Cox VGS VT VDsat = 0


or
VGS VT = VDsat
Thus,

I D = I Dsat =

Z nCox
2

V
(
)
GS
T

2L

VDsat VDS
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MOS Transistor I-V Derivation


2

Z nCox
VDS
ID =
V

V
V

(
)
GS
T
DS
L
2
0 VDS VDsat and VGS VT

I D = I Dsat =

Z nCox
2
VGS VT )
(

2L

VDsat VDS

V Dsat = VGS VT
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Example Calculation
Calculate the current through the MOSFET assuming that the threshold voltage is
0.6V and the rest of the parameters correspond to 180nm technology. Assume that
the VGS = VDD and VDS = VDD/2. Also assume that the surface mobility is 200 cm2/Vs,
and the transistor width is 10x the transistor length.
First we must consider the whether the device is in cutoff, linear region, or saturation.

VGS > VT

1.8 is greater than 0.6 therefore NOT in cutoff!

VD,SAT = VGS VT = 1.8 0.6 = 1.2V

VDS = 0.9 is less than VD,SAT = linear region!

Now we can use the appropriate formula!


2

Z nCox
VDS
ID =
(VGS VT )VDS
L
2
0 VDS VDsat and VGS VT

(0.9) 2
I D = 10 * 200 * 6.903e 7(1.8 0.6)0.9

I D = 9.319e 4[ A] = 0.9319mA

Example Calculation
Calculate the current through the MOSFET assuming that the threshold voltage is
0.6V and the rest of the parameters correspond to 180nm technology. Assume that
the VGS = VDD and VDS = 0.8*VDD. Also assume that the surface mobility is 200
cm2/Vs, and the transistor width is 10x the transistor length.
First we must consider the whether the device is in cutoff, linear region, or saturation.

VGS > VT

1.8 is greater than 0.6 therefore NOT in cutoff!

VD,SAT = VGS VT = 1.8 0.6 = 1.2V

VDS = 0.8*1.8 = 1.44 is greater than


VD,SAT = saturation region!

Now we can use the appropriate formula!


I D = I Dsat =

Z n Cox
2
VGS VT )
(

2L

VDsat VDS

I D = 10 * 0.5* 200 * 6.903e 7 (1.8 0.6)

I D = 9.940e 4[ A] = 0.9940[mA]

Example Calculation
Calculate the current through the MOSFET assuming that the threshold voltage is
0.6V and the rest of the parameters correspond to 180nm technology. Assume that
the VGS = 0.1 V and VDS = 0.8*VDD. Also assume that the surface mobility is 200
cm2/Vs, and the transistor width is 10x the transistor length.
First we must consider the whether the device is in cutoff, linear region, or saturation.

VGS > VT

0.18 is less than 0.6 therefore in cutoff!

ID 0
A more accurate answer is that that there is leakage! Notice dependence below!

I D,sub = I x (1 e

VDS
kT / q

(VGS VT )

)e

= I x (1 e

VDS
kT / q

VT
)e S

VGS =0

S = subthreshold slope

Ix= parameter that is proportional to device width (Z)

Subthreshold Leakage Currents


A more accurate answer is that that there is leakage! Notice dependence below!

I D,sub = I x (1 e

VDS
kT / q

(VGS VT )

)e

= I x (1 e

VDS
kT / q

VT
)e S

VGS =0

S = subthreshold slope

exponential dependence on threshold voltage

Ix= parameter that is proportional to device width (Z)

Conclusion
Subthreshold current Z
Subthreshold current e

VT
S

Channel Length Modulation Effect


For VDS > Vdsat = VGS-VTn, pinch-off region grows by L !

As VDS grows, the potential across


channel stays as (VGS-VTn)
All excess voltage is across pinch off
region
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Channel Length Modulation Effect


Channel Length Modulation

I D = I Dsat

Z nCox
2
=
(VGS VT ) (1 + VDS )

2L

Channel Length Modulation Parameter

VDsat VDS

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Current Equations
NMOS
Regardless of
Mode

K n = K n'

PMOS

W
W
W
W
= n C ox
(Note : W = Z in Pierret) K p = K p'
= p Cox
L
L
L
L

(Note: W = Z in Pierret)

Cutoff

i DS = 0
Linear
iDS

Z n Cox
vDS
=
(vGS VTN )vDS

L
2
vGS VTN vDS 0

Saturation
iDS =

VT for
Enhancement
Mode

for vGS VTN

Z nCox
(vGS VTN )2 (1 + vDS )

2L
for vDS vGS VTN 0

VTN > 0

iSD = 0

iSD

iSD =

for vSG VTP

Z nCox
vSD
=
vSG VTP )vSD
(

L
2
vSG + VTP vSD 0

Z pCox

(v V )2 (1 + v )
SG
TP
SD

2L
for vSD vSG + VTP 0

VTP < 0

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