Quantity modelling
Presented at the COMON 2nd International Training Course on Compact Modelling, June 28-29, 2012
Tarragona, Spain
Dec. 2003
Jun. 2004
Sep. 2004
0.0.1
0.0.2
0.0.3
Mar. 2005
May 2005
Jul. 2005
0.0.5
0.0.6
0.0.7
Jan. 2006
0.0.8
May 2006
0.0.9
Sept. 2006
0.0.10
Mar. 2007
0.0.11
Jun. 2007
0.0.12
Nov. 2007
Apr. 2008
0.0.13
0.0.14
Apr. 2009
Mar. 2011
0.0.15
0.0.16
Feb. 2011
1.0.0
First public version of simulator- features include more than 100 different circuit components,
DC analysis, AC analysis (including noise analysis and noise distribution analysis), Sparameter analysis (including noise simulation), transient analysis, Harmonic Balance
analysis (including noise simulation), system simulation, parameter sweep and optimization
of analogue circuits, digital simulation with ICARUS Verilog,PCB layout using KiCAD,
numerical data processing using Octave, RF transmission line calculation (coaxial, microstrip,
coupled microstrip, coplanar line, stripline, twisted pair rectangular wavequide etc.,
filter synthesis (LC ladder, stepped-impedance, microstrip, active filters etc., attenuator
synthesis, and GPIB control.
Mar. 2011
1.1.0
Added VHDL digital simulation with GHDL plus numerous bug fixes.
Jun. 2011
1.2.0
Nov. 2011
1.3.0
Feb. 2012
1.3.1
April 2012
1.3.2
Added compiled C++ and Verilog-A device and circuit models using MinGW and ADMS,
more bug fixes and small improvements. Released QucsStudio-light: QucsStudio without
Octave and model Compiler.
Verilog-A: new syntax for highlighting, $given() function, preprocessor flag 'insideQucsStudio',
better parameter extraction in Verilog-A files, port names in Verilog-A symbols. Linear branches
in Verilog-A. Added stoh() function. Windowing for time2freq() function. HB now allows
Frequency sweeps. Many small improvements plus bug fixes.
Added functions length(), arcsin() and arccos() in equations. Added export filter for Xfig3.2
format. Added system simulation icon to simulation group. Added German translation for text
editor. Many small improvements plus bug fixes.
DC
Circuit
encoding
SPICE
2g6
and
3f5
NETLIST
AC
TRAN
Qucs
Schematic
diagram
S-parameter*
Data processing
Emitter follower
subcircuit
Voltage gain
Input resistance
Output resistance
Macromodel body
Macromodel symbol
Closed loop
amplifier
with x10 gain
VBP=
j f/f0
1 f / f 0 2 j /Q f / f 0
f 0=
1
1
=
2 R 3 C 1 2 R4 C 3
R
1
Q= 1 6
3
R7
+
Compact device modelling and circuit macromodelling tools
Hand crafted
C++ models
Component based
Component based
circuit macromodels
subcircuit models
Radio frequency equation
Verilog-A compact
defined device (RFEDD)
device models
models
Generate equation
defined models from
physical equations
Modify model
CHANGES
NEEDED
Interactive
testing
Display
results
Further testing to
confirm model
performance
OK
Verilog-A
code
generation
Compile Verilog-A
code to C++ and
link model with main
body of simulator
code
STOP
10
EDDtwoterminalbranchcomponentsarecharacterizedbytheexpressionsgiveninthefollowing
equations: I = I V and g =dI / dV; Q=Q V , I
and c=dQ /dV =dQ V / dV dQ I / dV =dQ V /dV dQ I / dIg
11
5nkT
q
13
14
15
High quality models are an essential prerequisite for accurate circuit simulation
of established and emerging technologies.
In contrast to hand-coded C, the Verilog-A hardware description language provides a
highly expressive standardized language which embodies features for the automatic
generation of partial derivatives.
Once written, Verilog-A model descriptions are normally compiled to C or C++ code,
and linked to the main code of circuit simulator.
Traditional macromodeling adopts a different approach where a subcircuit is used
to represent model connectivity. The body of the subcircuit being assembled from
predefined components and user defined subcircuits, whose parameters are normally
numerical quantities rather than non-linear algebraic equations.
Macromodeling supports both functional modelling and interactive testing without the
need for code compilation and linking.
The next few slides present a unified modelling approach for constructing of compact
semiconductor device models and circuit macromodels which retains the best features
of interactive subcircuit macromodeling while promoting a straight forward procedure
for the generation of high performance Verilog-A model code. The presented technique
is called QUANTITY modelling.
16
In (a) current Iname is a non-linear function of the voltages applied to the EDD terminals
connected to branches two to eight. NOTE: EDD branches with current set at zero act as
high impedance voltage probes.
In (b) charge Q1 represents the stored charge in branch 1. Changes in Q1 over a period of time
result in a change in the current flowing in branch one.
The listed Verilog-A code fragments clearly identify the strong relationship between the EDD
equation defined quantity block structure and the corresponding Verilog-A code.
The above EDD structures represent the simplest quantity elements. Other combinations
with different numbers of current or charge equations and voltage probes are possible.
17
Equivalence between
Qucs/QucsStudio
standard components
and Verilog-A code
blocks.
18
Qucs/QucsStudio use a
noise voltage generator
of the form given by the
following equation to
generate noise signals:
VPSD f =
U
,
ac f e
19
Although the current and charge EDD blocks shown in the previous slide are presented
as separate items the Qucs/QucsStudio equation-defined quantity modelling technique
naturally proceeds in a top-down fashion rather than the conventional bottom-up design
process.
The following diagram illustrates the three principle stages in the construction of a
Qucs/QucsStudio equation-defined quantity model.
20
Starting with a set of equations that characterize the physical properties of a device,
or the functionality of a circuit, a subcircuit schematic symbol is drawn with signal
connection pins and a default parameter list attached.
The next step in the model development sequence involves drawing a second schematic
composed of EDD current and charge equation-defined blocks which represent the body
of a model, including currents, charges, resistance, voltage controlled currents, current to
voltage conversion blocks and noise generators.
Interactive testing of the model follows, allowing a full evaluation of a model function.
On satisfactory completion of the testing phase the Verilog-A code for a Qucs
equation-defined quantity model is generated by inspection of the model symbol and the
body schematic, simultaneously entering the Verilog-A code for each item in the various
sections indicated as comments in the Verilog-A template shown on the previous slide.
21
22
I n =V n
Where subscript n is the EDD branch number in the
range 1 to 8.
23
24
25
26
27
28
Generating Verilog-A code: Qucs equation defined devices via Verilog-A code fragments
to a Verilog-A standardised template
Equation-defined device
model
Model symbol
pin names
Verilog-A
code
fragments
29
Compact
Compact
Semiconductor
Semiconductor
device or circuit
Device or circuit
physical
macromodels
equations
Pin1
Pout1
Equation-defined
device model
or circuit
macromodel
Symbol
Poutn
:
Pinn
Subcircuit
symbol
Verilog-A
fragments
Poutn
C++
File XXX.va
C++ Compiled
model
Pin1
Pout1
Verilog-A
model
code
[Template
structure]
File XXX.va.cpp
File XXX.dll
MinGW tools
ADMS
Pinn
Subcircuit body
30
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Schematic symbol, default parameter list and equivalent
circuit of an npn bipolar phototransistor
Light bus
31
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Phototransistor model parameters
Name
BF
BR
Is
Nf
Nr
Var
Vaf
Mje
Vje
Cje
Mjc
Vjc
Cjc
Tr
Tf
Ikf
Ikr
Rc
Re
Rb
Kf
Ffe
Af
Responsivity
Symbol
f
r
Is
Nf
Nr
Var
Vaf
Mje
Vje
Cje
Mjc
Vjc
Cjc
Tr
Tf
Ikf
Ikr
Rc
Re
Rb
Kf
Ffe
Af
Responsivity
Description
Forward beta
Reverse beta
Saturation current
Forward emission coefficient
Reverse emission coefficient
Reverse Early voltage
Forward Early voltage
Base-emitter exponential factor
Base-emitter built-in potential
Base-emitter zero-bias depletion capacitance
Base-collector exponential factor
Base-collector built-in potential
Base-colector zero-bias depletion capacitance
Ideal reverse transit time
Ideal forward transit time
High current corner for forward beta
High current corner for reverse beta
Collector series resistance
Emitter series resistance
Base series resistance
Flicker noise coefficient
Flicker noise frequency exponent
Flicker noise exponent
Responsivity at peak wavelength
Unit
P0
P0
P1
P1
%/nm
P2
P2
P3
P3
P4
P4
A
V
V
V
F
V
F
s
s
A
A
A/W
Default
100
0.1
1e-10
1
1
100
100
0.33
0.75
1p
0.33
0.75
1p
100n
0.1n
0.5
0.5
2
1
100
1e-12
1
1
1.5
2.6122x103
-1.4893x101
%/nm2 3.0332x10-2
%/nm3 -2.5708x10-5
%/nm4 7.6923x10-9
32
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Bipolar phototransistor model equations
DC I/V characteristics
[
[
]
]
IEC= Is exp
IEC
V BI , CI
1 IDC 2= r GMINV BI , CI
Nrvt 300
ICC=Is exp
V BI , EI
1
Nfvt 300
CBC=
Capacitance
dQ BI , CI
=
dV BI , CI
=2 MjcCjc
CBE=
q1
1 14q2
2
V BI , CI
Vjc
Mjc
Tr
dIEC
dV BI , CI
V BI , CI
dQ BI , EI
=
dV BI , EI
q1=1
Cjc
Cje
V BI , EI
Vje
Mje
Tr
ICC
GMINV BI , EI
f
V BI , CI V BI , EI
Vaf
Var
ICC IEC
KT
q2=
vt T =
Ikf
Ikr
q
[ ICCIEC ]
2MjcV BI , CI
dIEC
1 Mjc Tr
Vjc
dV BI , CI
=2 MjeCje
Photocurrent
ICT =
IDE 2=
dICC
dV BI , EI
Vjc
2
V BI , CI >=
V BI , EI
Vjc
2
Vje
2
2MjeV BI , EI
Vje
1Mje + Tr dICC
V BI , EI >=
Vje
2
dV BI , EI
Iopt=GpbcPopt
Gpbc =
RelSensitivityRe sponsivity
f 100
RelSensitivity =P0P1P22P33P4 4
Noise
4KT
f
Rc
8KT
iRban 2=
f
Rb
iRcn 2=
4KT
f
Re
8KT
iRbbn2 =
f
Rb
i Ren2=
iICTsn 2=2qICf
2
ibsn =2qIBf
ibfn 2= Kf
IB Af
f
f Ffe
Where K is the Boltzmann constant, T is the temperature in Kelvin, q is the electron charge, GMIN is a small
admittance in parallel with the device junctions, fisthenoisefrequencybandwidthinHzandisthelight
wavelengthinnm.Othersymbolsandnodenamesaredefinedinthepreviousslides.
33
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 1 the basic npn transistor model
Large signal DC model
Generate symbol
Equation defined device
34
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 2 DC simulation tests
35
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 3 Adding capacitance to the phototransistor model
Charge equations
V BI ,CI
Q BI , CI
CBCdV =TrIEC2
[ {
[
[ {
V BI , CI
CjcVjc
= TrIEC
1 1
1Mjc
Vjc
V BI , EI
Q BI , EI
V BI , CI
Cjc Mjc
1Mjc V BI , CI
Vjc
Mjc
CBEdV
=TfICC2
= TfICC
} ]
1 Mjc
V BI , CI <=
V BI , EI
Cje Mje
1Mje V BI , EI
Vje
MjE
V BI , EI
CjeVje
1 1
1Mje
Vje
V BI , CI
} ]
1Mje
Vjc
2
V BI , EI
V BI , EI <=
Vjc
2
Vje
2
Vje
2
EDD blocks
36
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 4 simulating capacitive effects
AC gain
37
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
RelSensitivity =P 0P 1 P22 P 33 P 44
Where P 0=2.6122e3, P 1 =1.4893e1, P2 =3.0332e-2, P 3 =2.5708e-5, P 4 =7.69e-9
EDD light
bus model
38
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 6 simulating photoelectric effects
Phototransistor output
Phototransistor responsivity
characteristics
characteristics
39
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 7 adding noise to the phototransistor model
Qucs noise voltage source
ibsn= 2qIB A/ Hz
VPSD f =
U
acf e
Af
Kf
ibfn=
f Ffe
A/ Hz
iICTsn= 2qIC A/ Hz
Noise parameters
40
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 8 simulating phototransistor noise
Variable light power
Variable wavelength
41
Buildingacompactsemiconductormodelofannpnbipolarphototransistor
Construction: stage 9 producing a distribution standard model
Model
Generate Verilog-A
code
Store in Qucs
library
`include "disciplines.vams"
`include "constants.vams"
module phototransistor (Collector, Base, Emitter, Power, Wavelength);
inout Collector, Base, Emitter, Power, Wavelength;
electrical Collector, Base, Emitter, Power, Wavelength;
// Definition of internal local nodes
electrical CI, BI, BI2, EI;
// Parameter values and description text
`define attr(txt) (*txt*)
parameter real Bf=100 from [1:inf] `attr(info="forward beta");
parameter real Br=0.1 from [1e-6:inf] `attr(info="reverse beta");
:
parameter real P3=-2.5708e-5 from[-inf:inf]
`attr(info="relative selectivity polynomial coefficient" );
parameter real P4=7.6923e-9 from[-inf:inf]
`attr(info="relative selectivity polynomial coefficient" );
// Definition of internal variables and quantities
real VT, con1, con2, con3, con4, con5, con6, con7, con8, con9, con10, TwoQ, FourKT,
GMIN;
real ICC, IEC, q1, q2, IB, IC, IE, Q1, RelSensitivity;
// Quantities
analog begin
// Module initialisation code
@(initial_model)
begin
VT = `P_K*300/`P_Q; con1=1/(Nf*VT); con2=1/(Nr*VT); con3=1-Mje; // VT = vt(300)
con4=1-Mjc, con5=pow(2, Mje); con6=pow(2, Mjc); con7=Rb/2; con8=2/Rb;
con9=1/Rc; con10=1/Re; TwoQ=2*`P_Q; GMIN=1e-12;
// TwoQ = 2*q
FourKT=4*`P_K*$temperature;
// FourKT = 4*K*T
end;
// Model quantity equations and current contributions
ICC=Is*(limexp(V(BI,EI)*con1)-1); IEC=Is*(limexp(V(BI,CI)*con2)-1);
q1=1+V(BI,CI)/Vaf + V(BI,EI)/Var; q2=(ICC/Ikf) + (IEC/Ikr); IB=V(BI2,BI)*con8;
IC=V(Collector,CI)*con9; IE=V(EI,Emitter)*con10; I(Collector,CI) <+ IC;
I(Base,BI2) <+ V(Base, BI2)*con8; I(BI2, BI) <+ IB; I(EI, Emitter) <+ IE;
I(BI,CI) <+ (IEC/Br) + GMIN*V(BI,CI); I(BI,EI) <+ (ICC/Bf) + GMIN*V(BI,EI);
I(CI,EI) <+ (ICC-IEC)/(1e-20+(q1/2)*(1+sqrt(1+4*q2)));
Q1=(V(BI,CI) >Vjc/2) ? Tr*IEC+Cjc*con6*(Mjc*V(BI,CI)*V(BI,CI)/Vjc+con4*V(BI,CI))
: Tr*IEC+Cjc*((Vjc/con4)*(1-pow((1-V(BI,CI)/Vjc),con4)));
I(BI,CI) <+ ddt(Q1);
Q1=(V(BI,EI) >Vje/2) ? Tf*ICC+Cje*con5*(Mje*V(BI,EI)*V(BI,EI)/Vje+con3*V(BI,EI))
: Tf*ICC+Cje*((Vje/con3)*(1-pow((1-V(BI,EI)/Vje),con3)));
I(BI,EI) <+ ddt(Q1);
RelSensitivity = P0+P1*V(Wavelength)+P2*pow(V(Wavelength),2)
+P3*pow(V(Wavelength),3)+P4*pow(V(Wavelength),4);
I(CI,BI2) <+ ( (Responsivity*RelSensitivity)/(Bf*100) )*V(Power);
// Noise contributions
I(Collector,CI) <+ white_noise(FourKT*con9, "thermal");
I(Base,BI2)
<+ white_noise(FourKT*con8, "thermal");
I(BI2,BI)
<+ white_noise(FourKT*con8, "thermal");
I(EI,Emitter)
<+ white_noise(FourKT*con10, "thermal");
I(CI,EI)
<+ white_noise(TwoQ*IC, "shot");
I(BI,EI)
<+ white_noise(TwoQ*IB, "shot");
I(BI,EI)
<+ flicker_noise(Kf*pow(IB, Af), Ffe, "flicker");
end
endmodule
Phototransistor.va
file
42
Recent trends in compact device modelling suggest that there is a growing interest in
equation-defined device techniques and Verilog-A among the device modelling community
Current releases of the popular GPL Qucs/QucsStudio circuit simulators, the freely available
LinearTechnology LTspiceIV circuit simulator and the open source Modelica Consortium
OpenModelica simulation environment all include equation-defined features for compact
semiconductor device modelling
A primary aim of compact equation-defined device modelling is the generation of efficient
high-level hardware description language models that support a wide range of circuit
simulation domains, including DC, AC, transient, S-parameter, AC and time domain noise,
plus harmonic balance analysis, which can be translated to Verilog-A easily
A second equally important aim is a high level of portability for equation-defined device
models across circuit simulation platforms
Equation-defined device models based on a simple template structure encourage the
development of readable and accurate simulation models
An extension of equation-defined model parameters allows model functionality to be
selected by users, reducing the number of arithmetic computations which in turn
decreases simulation times
Production versions of equation-defined device models are easily translated to Verilog-A
or the Modelica simulation language prior to compiling to C++ and merging with the
control and analysis C++ code sections of a simulator
43
AcompactsemiconductormodeltemplateforQucs/QucsStudio,SPICEandModelica
Template
Qucs
LTspice
Verilog-A
Header
Model
Initialisation
Code
Eqn:EqnX param=yy
.param = {yy}
Modelica
model name
Interface pin descriptions
parameter type name=yy
end
Functional
body of
Model
EDD
VCVS
CCVS
VCCS
CCCS
C
R
Current contributions
Noise contributions
[Voltage and current
noise generators]
.Def.End
B
H
E
G
C
R
Current contributions
Current contributions
Noise contributions
[Diode noise generators]
Noise contributions
.ends
endmodule
Simulation
Capabilities
DC
.OP
AC
.DC
TRAN
.TRAN
S parameter analysis
.TEMP
Noise (freq and time domains) .TF
HB (single input signal)
.STEP
Parameter sweep
.noise (freq domain)
Digital (VHDL, Verilog)
.FOUR
Optimisation
Digital (mixed-mode)
Compact
Modelling
Tools
1. Interactive subckts
2. ADMS Verilog-A
compiler
Interactive subckts
Equation
R
G
C
Controlled sources
Current contributions
Interface node current
and voltage equations
endname
Transient
Verilog-A to C/C++
compiler
Modelica to C/C++
compiler
NOTE: Mathematical expressions require a full range of operators and functions (similar to Verilog-A)
plus some form of if then else statement [for example, a ? b : c or if(a, b, c) syntax]
44
SpecificationforanextendedSPICEsemiconductordiodemodel
Format
User Selection
switches
[0=off, 1=on]
Physical parameters
Operating region
or
property
BVSWITCH
CdepSWITCH
CdiffSWITCH
AcnoiseSWITCH
Non-linear DC I-V
characteristics
Reverse breakdown
Depletion capacitance
Diffusion capacitance
Small signal AC noise
IrecovSWITCH
TAU
SWSH
SWF
ScaleR
ScaleSH
ScaleF
Reverse recovery
characteristics
Large signal time
domain noise
SPICE
EXTENDED
MODEL
QucsequationdefineddeviceequivalentcircuitfortheSPICE
semiconductordiodemodel
Model
Function
Control
Parameters
Shot noise
1/f noise
BVSWITCH
CdepSWITCH
CdiffSWITCH
ACnoiseSWITCH
Noise free
resistor
Q1=Qdep
Q2=Qdiff
Id
Breakdown
Id
Equation EqnX blocks contain variable initialisation equations and constants. Variable
expressions are converted into numerical values before a simulation starts.
46
2. Reverse
breakdown
[ BVSWITCH = 1 ]
3. Capacitance
[CdepSWITCH=1, CdiffSWITCH=0]
[CdepSWITCH=1, CdiffSWITCH=1]
[CdepSWITCH=0, CdiffSWITCH=1]
47
SPICEequationdefineddeviceequivalentcircuitforthebasic
semiconductordiodemodel
SPICE test code
.subckt ModDiodeSlide8 1 2 BVSWITCH=0 CDEPSWITCH = 0 CDIFFSWITCH = 0 ACSWITCH=0
Vid 2 0 dc 0.6
+
IRECSWITCH=0 AREA=1.0 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
Vm 2 22 dc 0
+
TNOM=26.85 EG=1.16 BV=100 IBV=1e-30 CJ0=1p VJ=1 M=0.5
Rs 22 3 1
+
TT=1n TAU=100e-9 AF=1 KF=1e-16 RS=0.01
X1 3 0 ModDiode BVSWITCH=1 CDEPSWITCH=0 CDIFFSWITCH=0 AREA=1 N=1 XTI=2.0
*
+ ISat=1e-14 TEMP=26.85 TNOM=26.85 BV=4.5 IBV=1e-3 CJ0=1p VJ=1 M=0.5 TT=1n
.param CJ0T2 = {CJ0*AREA}
.op
.param ISEFF = {ISat*AREA}
.dc Vid -4.95 1 0.01
.param T1 = {TNOM+273.15}
.end
.param T2 = {TEMP+273.15}
.param EGT1 = {EG-7.02e-4*T1*T1/(1108+T1)}
.param EGT2 = {EG-7.02e-4*T2*T2/(1108+T2)}
Variable expressions
.param P7 = 1-M
.param P6 = {CJ0T2*VJ/P7}
.param P11 = {M/(2*VJ)}
.param PK = 1.3806503e-23
Constants
.param PQ = 1.602176472e-19
.param VTT2 = {Pk*T2/PQ}
.param VJT2 = {(T2*VJ/T1)-2*VTT2*(LN(T2/T1)**1.5)-((T2*EGT1/T1)-EGT2)}
.param IST2 = {ISEFF*((T2/T1)**(XTI/N))*EXP((-EGT1/VTT2)*(1-T2/T1))}
.param K2 = {1/(N*VTT2)}
.param K5 = {N*VTT2}
.param IBVEFF = {IBV*AREA}
.param IDBV = {-IST2*(exp(-BV*K2)-1.0)}
.param BVEFF = {if(IBVEFF/(2*IDBV), BV-K5*ln(IBVEFF/IDBV), BV)}
.param GMIN = 1e-12
.param CDEPPARAM = {if(CDEPSWITCH, 1, 0)}
.param CDIFFPARAM = {if(CDIFFSWITCH, 1, 0)}
*
RS 1 n5 {RS}
* Diode I-V characteristics
B1 n5 n1 I = IST2*(exp(V(n5, n1)*K2)-1.0)+GMIN*V(n5, n1)
Vsense n1 2 DC 0
B2 1 2 I = if( {BVSWITCH}, -IST2*(exp( -( BVEFF+V(n5, n1) )*K2)-1.0+BVEFF*K2), 0 )
* Depletion capacitance
Cd 1 2 Q = CDEPPARAM*(if(x+0.501, CJ0T2*(x+P11*x*x), P6*(1-(1-x/VJT2)**P7) ))
* diffusion capacitance
Cdiff 1 2 Q = CDIFFPARAM*TT*(IST2*(exp(V(n5,N1)*K2)-1.0))
* Diode shot and 1/f noise
F1 0 n2 Vsense 1
Vid (V)
Lnoise n2 n3 1000
cnoise n3 n4 1000
If..then..else statement
Free versions of SPICE:
Vnoise n4 0 dc 0
f n5 n1 Vnoise {if(ACSWITCH, 1, 0)}
LTspice , ngspice, SPICEOPUS
Dn n3 0 Dnoise
.model Dnoise D(Is=ISat N=N AF=Af KF=KF)
NO
C expressed as charge Q
.ends
Function selection
standardisation of extended
features!
48
Qucsnonlinearmodelofasteprecoverydiode*
Q3 represents Cdep
49
Qucstestcircuitforasteprecoverydiode
50
SPICEnonlinearmodelofasteprecoverydiode
*SPICE Interpretive compact semiconductor diode model.
*
Based on modular compact device structure.
*
.subckt ModDiodeSlide10 1 2 BVSWITCH=0 CDEPSWITCH = 0 CDIFFSWITCH = 0
+
IRECSWITCH=0 AREA=1.0 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
+
TNOM=26.85 EG=1.16 BV=100 IBV=1e-30 CJ0=1p VJ=1 M=0.5
+
TT=1n TAU=100e-9 AF=1 KF=1e-16 RS=0.01
*
.param CJ0T2 = {CJ0*AREA}
RS 1 n5 {RS}
.param ISEFF = {ISat*AREA}
B1 n5 n1 I = IST2*(exp(V(n5, n1)*K2)-1.0)+GMIN*V(n5, n1)
.param T1 = {TEMP+273.15}
Vsense n1 2 DC 0
.param T2 = {TNOM+273.15}
B2 n5 n1 I = if( {BVSWITCH}, -IST2*(exp( -( BVEFF+V(n5, n1) )*K2)-1.0+BVEFF*K2), 0 )
.param EGT1 = {EG-7.02e-4*T1*T1/(1108+T1)}
* Depletion capacitance
.param EGT2 = {EG-7.02e-4*T2*T2/(1108+T2)}
Cd n5 n1 Q = CDEPPARAM*(if(x+0.501, CJ0T2*(x+P11*x*x), P6*(1-(1-x/VJT2)**P7) ))
.param P7 = 1-M
* diffusion capacitance
.param P6 = {CJ0T2*VJ/P7}
Cdiff n5 n1 Q = CDIFFPARAM*TT*(IST2*(exp(V(n5,N1)*K2)-1.0))
.param P11 = {M/(2*VJ)}
CQ3 n5 n1 Q = IrecSWITCH*if(x+0.5 <= 0.5, CJ0*x, 0)
.param PK = 1.3806503e-23
CQ4 n5 n1 Q = IrecSWITCH*if((x+0.5 > 0.5) & (x+0.5 <= FCP+0.5), C1*(x+C2)**2-C3, 0)
.param PQ = 1.602176472e-19
CQ5 n5 n1 Q = IrecSWITCH*if(x+0.5 > FCP+0.5, CF*x-C4, 0)
.param VTT2 = {Pk*T2/PQ}
.ends
.param VJT2 = {(T2*VJ/T1)-2*VTT2*(LN(T2/T1)**1.5)-((T2*EGT1/T1)-EGT2)}
*
.param IST2 = {ISEFF*((T2/T1)**(XTI/N))*EXP((-EGT1/VTT2)*(1-T2/T1))}
Vtran 2 0 dc 0 pulse(0.9 -5 0.2n 0.001n 0.001n 400n 800n)
.param K2 = {1/(N*VTT2)}
Vm 2 3 dc 0
.param K5 = {N*VTT2}
X1 3 0 ModDiodeSlide10 BVSWITCH=0 CDEPSWITCH=1 CDIFFSWITCH=1
.param IBVEFF = {IBV*AREA}
+
IRECSWITCH=1 AREA=1 N=1 XTI=3.0 ISat=1e-14 TEMP=26.85
.param IDBV = {-IST2*(exp(-BV*K2)-1.0)}
+
TNOM=26.85 EG=1.16 BV=4.5 IBV=1e-3 CJ0=1p VJ=1 M=0.5
.param BVEFF = {if(IBVEFF/(2*IDBV), BV-K5*ln(IBVEFF/IDBV), BV)}
+
TT=1e-9 TAU=10e-9 AF=1 KF=1e-16 RS=1
.param GMIN = 1e-12
.op
.param CDEPPARAM = {(1-IrecSWITCH)*if(CDEPSWITCH, 1, 0)}
.tran 0.0001n 5n
.param CDIFFPARAM = {(1-IrecSWITCH)*if(CDIFFSWITCH, 1, 0)}
.end
.param FCP
= {VJ}
.param CF
= {TAU/RS}
.param CM
= {CF-CJ0}
.param C1
= {CF-CJ0/2*FCP}
.param C2
= {(CJ0*FCP)/CM}
.param C3
= {(CJ0*CJ0*FCP)/(2*CM)}
.param C4
= {CM*FCP/2}
*
51
52
Diode I and
dQ/dt terms
Diode step
recovery I
Diode small
signal I noise
// Contributions
I(PA,AN) <+ V(PA,AN)/RS;
Id = IST2*(limexp(V(AN,CA)*K2)-1.0)+GMIN*V(AN,CA);
I(AN,CA) <+ Id;
if (CdepPARAM == 1)
if (V(AN,CA) >= 0.0) I(AN,CA) <+ ddt(CJ0T2*(V(AN,CA)+P11*V(AN,CA)*V(AN,CA)));
else I(AN,CA) <+ ddt(P6*(1-pow(1-V(AN,CA)/VJT2, P7)));
else I(AN,CA) <+ 0.0;
if ( BVSWITCH == 1)
if (V(AN,CA) < -BV) I(AN,CA) <+ -IST2*(limexp(-(BVEFF+V(AN,CA))*K2-1+BVEFF*K2));
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (CdiffPARAM == 1) I(AN,CA) <+ ddt(TT*Id); else I(AN,CA) <+ 0.0;
if ( BVSWITCH == 1)
if (V(AN,CA) == -BV) I(CA,AN) <+ IBV; else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (IRECSWITCH == 1)
if (V(AN,CA) <=0.0) I(AN,CA) <+ ddt(CJ0*V(AN,CA)); else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (IRECSWITCH == 1)
if ((V(AN,CA) > 0.0) && (V(AN,CA) < FCP)) I(AN,CA) <+ ddt(C1*pow(V(AN,CA)+C2, 2)-C3);
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if ( IRECSWITCH == 1)
if (V(AN,CA) >= FCP) I(AN,CA) <+ ddt(CF*V(AN,CA)-C4);
else I(AN,CA) <+ 0.0;
else I(AN,CA) <+ 0.0;
if (ACSWITCH == 1) begin
I(PA,AN) <+ white_noise((4*PK)/RS,"thermal");
I(AN,CA) <+ white_noise(2*PQ*Id, "shot");
I(AN,CA) <+ flicker_noise(KF*pow(Id,AF), 1, "flicker");
end
end
Endmodule
53
Device parameters
Equivalent to limexp
Model
equations
54
54
55
MESFET Symbol
and parameters
MESFET subcircuit body
56
DC
AC
57
Harmonic Balance
Post-simulation
data processing
control file
FFT
Octave plot of
Vout amplitude
spectra against
frequency
58
Summary
1. Qucs and QucsStudio are freely available circuit simulators distributed as open
source software under the GNU General Public Licence (GPL).
2. This presentation has attempted to outline the history and the fundamental features
of the packages, the available equation-defined components, built in modelling
aids, analysis types and post-simulation data analysis and visualisation capabilities.
3. The presentation also introduced a number of basic approaches to circuit simulation
with Qucs and QucsStudio.
4. A series of slides also showed how the compact semiconductor modelling and circuit
macromodeling features implemented in the current QucsStudio release can be
used to develop equation-defined component models of established and emerging
technology devices.
5. A turn-key approach to compact device modelling using the Verilog-A hardware
description language was introduced and the proposed modelling system
demonstrated via the development of a MESFET RF device simulation model.
Qucs and QucsStudio are freely available under the open source General Public Licence
Download from:
Qucs version 0.0.16
http://qucs.sourceforge.net
QucsStudio version 1.3.2 http://mydarc.de/DD6UM/QucsStudio/qucsstudio.html
QucsStudio-1.3.2_light.zip {without Octave and model compiler}]
59
References
Brinson M. and Jahn S., Interactive compact device modelling using Qucs equation defined devices,
International Journal of Numerical Modelling: Electrical Networks, Devices and Fields, 21(5) pp. 335-349,
September/October 2008. DOI : 10.1002/jnm.676.
Brinson M. and Jahn S., Qucs: A GPL software package for circuit simulation, compact device modelling and
circuit macromodelling from DC to RF and Beyond, International Journal of Numerical Modelling: Electrical
Networks, Devices and Fields, 22(4) pp. 297-319, July/August 2009. DOI : 10.1002/jnm.702.
Brinson M. and Jahn S., Compact macromodelling of operational amplifiers with equation defined devices,
International Journal of Electronics, 96(2), pp. 109-122, February 2009, DOI:10.1080/00207210802580288, ISSN :
0020-7217.
Brinson M. and Jahn S., Modelling of high-frequency inductance with Qucs non-linear radio frequency
equation-defined devices, International Journal of Electronics, 96(3), March 2009,
DOI:10.1080/00207210802640603, ISSN : 0020-7217.
Brinson M.E., Jahn S. and Nabijou H., Z Domain delay subcircuits and compact Verilog-A macromodels for
mixed-mode sampled data circuit simulation, Test Technology Technical Council (TTTC) of the IEEE Computer
Society, Radioelectronics & Informatics Journal, Vol. 45, No. 2, pp. 14-20, April/June 2009. ISSN 1563-0064.
Brinson M.E. and Nabijou H., Adaptive subcircuits and compact Verilog-A macromodels as integrated design
and analysis blocks in Qucs circuit simulation,International Journal of Electronics, Vol. 98 (5), pp. 631-645, May
2011. DOI: 10.1080/00207217.2011.562452.
Brinson M.E., Jahn S. and Nabijou H., A tabular source approach to modelling and simulating device and circuit
noise in the time domain, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol
26(6), pp. 555-567, November/December 2011. DOI: 10.1002/jnm801.
Brinson M. and Jahn S., Compact device modelling for established and emerging technologies with the Qucs
GPL circuit simulator, Mixed design of Integrated Circuits and Systems (MIXDES) 2009, Proceedings of
the 16 International Conference, pp. 39-44, Lodz, Poland, June 2009. ISBN 978-1-4244-4798-5. INSPEC
Accession Number: 10928855. Available from: http://ieeexplore.org .
60
References
Brinson M.E., Jahn S. and Nabijou H., A hybrid Verilog-A and equation-defined subcircuit approach to MOS
switched current analog cell modeling and simulation in the transient and large signal AC domains, Mixed
design of Integrated Circuits and Systems (MIXDES) 2010, Proceedings of the 17 International Conference, pp.
3-48, Wroclaw, Poland, June 2010.ISBN 978-1-4244-7011-2, INSPEC Accession Number: 11487844. Available
from:http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5551306
Brinson M.E., Jahn S. and Nabijou H., Adaptive EPFL-EKV long and short channel MOS device models for
Qucs, SPICE and Modelica circuit simulation, Mixed design of Integrated Circuits and Systems (MIXDES)
2011, Proceedings of the 18 International Conference, pp. 65-70, Gliwice, Poland, June 2011. ISBN 978-1-45770304-1. INSPEC Accession Number: 12219696. Available fro
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6016035
Jahn S., Brinson M.E., Margraf M., Parruitte H., Ardouin B., Nenzi P., and Lemaitre L., GNU simulators
supporting Verilog-A compact model standardization, MOS-AK International Meeting, Premstaetten,
Germany, March 2007. Available from:
http://www.mos-ak.org/premstaetten/papers/MOS-AK_QUCS_ngspice_ADMS.pdf
Brinson M. and Jahn S., Building device models and circuit macromodels with the Qucs GPL simulator : A
demonstration, Presentation to the European Network on Compact Modelling (COMON), Frankfurt(O), Germany,
2 April 2009. Available from:
http://www.mos-ak.org/frankfurt_o/papers/M_Brinson_Qucs_COMON_April_2_2009_final.pdf
Brinson M., Jahn S. and Cullinan M., Advances in compact semiconductor device modelling and circuit
macromodelling with the Qucs GPL circuit simulator, MOS-AK International Meeting, Frankfurt(O), Germany,
3 April 2009. Available from:
http://www.mos-ak.org/frankfurt_o/papers/P_7_Brinson_MOS-AK_April_2009_final.pdf
Brinson M.E., Jahn S. and Nabijou H., Qucs, SPICE and Modelica equation-defined modelling techniques for
the construction of compact device models based on a common model template structure, MOS-AK/GSA
International workshop on the frontiers of compact modeling for advanced analog/RF applications, Universit
Pierre et Marie Curie, Paris, April 2011. Available from:
http://www.mos-ak.org/paris/papers/P06_Brinson_MOS-AK_Paris.pdf
61
References
Brinson M.E.and Nabijou H., Adaptive EPFL-EKV long and short channel MOS device models for Qucs,
SPICE and Modelica circuit simulation, Mixed design of Integrated Circuits and Systems (MIXDES) 2011,
Proceedings of the 18 International Conference, pp. 65-70, Gliwice, Poland, June 2011.ISBN 978-1-4577-0804-1,
INSPEC Accession Number: 12219696. Available from http://ieeexplore.org.
Brinson M.E.and Margraf M., Verilog-A compact semiconductor device modelling and circuit
macromodelling with the QucsStudio-ADMS Turn-Key modelling system , Mixed design of Integrated
Circuits and Systems (MIXDES) 2012, Proceedings of the 19 International Conference, pp. 65-70, Warsaw,
Poland, May 2011.ISBN 978-83-62954-43-8, INSPEC Accession Number: 12219696. Available from
http://ieeexplore.org
Brinson M.E. From Qucs to QucsStudio: An international project to develop a freely available GU Public
Licence circuit simulator with compact device modelling tools, data processing capabilities,
manufacturing features and an analogue/RF design environment for engineers, MOS-AK/GSA International
workshop on Device modeling for Microsystems, Jaypee Institute of Information Technology, Nodia, March 2012.
Available from: http://www.mos-ak.org/india/presentations/Brinson_MOS-AK_India12.pdf .
Brinson M.E., Jahn S. and Nabijou H., A hybrid Verilog-A and equation-defined subcircuit approach to MOS
switched current analog cell simulation, IETE Journal of research, Vol 58(3), pp. 177=185, May-June 2012.
NEW BOOK: Open Source/GNU CAD for Compact Modelling, Editors: Wladek Grabinski and Daniel
Tomaszewski. Publisher: Mark de Jongh [Mark.de.Jongh@springer.sbm.com], www.springer-sbm.com.
Chapter 5: M.E. Brinson, Schematic entry and circuit simulation with Qucs.
Chapter 6: M.E. Brinson, Qucs modelling and simulation of analogue/RF devices and circuits.
62