Combinational ATPG

VLSI Design Verification

and Testing

Let us now focus on how test vector patterns are generated

In the previous lectures we have seen:

the necessity to test VLSI systems, and related costs/benefit
analysis
how faults are modeled
how faults are simulated
how the quality of testing is measured

Summary of last courses

64

64

in order to completely exercise its functionality, we need 2129 input patterns,

generating 265 output patterns

using a 1GHz ATE, this takes 2.15x 1022 years, roughly

y
Carry-out

64

Carry-in

the adder has 129 inputs and 65 outputs

Sum

Computational burden of functionally testing a 64-bit adder

Functional test

16 stuck-at fault locations

to be repeated 64x for a 64-bit adder

Carry-in

A
B

Structural representation of a 1-bit full-adder

Carry-out

Sum

Structural test (1)

generation of
carry

generation of sum

thus, 1024 vectors are needed for a full structural test

using a 1GHz ATE, this takes 1.024 x 10-7 s

In practice:
a subset covering <75% faults is provided by the designer as functional
test-patterns
ATPG is applied to supplement and raise the coverage to >98% stuck-at
f lt coverage
fault

The functional and structural examples achieve the exact same fault coverage

the total structural fault list has 64 x 16 = 1024 faults

Computational burden of structurally testing a 64-bit adder (approximate !)

Structural test (2)

activate the fault, and cause its effects to propagate to a circuit primary
output
p

if the circuit output is different from what would be expected from a faultfree circuit, then the fault can be detected

detect redundant or unnecessary circuit logic

p
prove
whether one circuit implementation
p
matched another circuit
implementation

But also:

inject a fault into a circuit

Automatic Test-Pattern Generator (ATPG) algorithm:

ATPG

x1

Searched and Infeasible

x2

cj

x1
1

Unexplored

Present Assignment

An internal representation of explored, infeasible, tree is being kept in

memory

The automatic test pattern generation makes use of these search space
abstractions

ATPG

1 in true circuit, 0 in faulty circuit

0 in true circuit, 1 in faulty circuit

unknown value in either true or

faulty circuit

0 in both true and faulty circuit

1 in both true and faulty circuit

In order to proceed ATPG in one single pass of the algorithm, a high-order

algebra representing both the good and failing machine simultaneously is
presented

Roths 5-valued algebra

AND gate forward implication

table

three examples

A forward implication results when the inputs to a logic gate are sufficiently
labeled so that the output can be uniquely determined

Forward implication

backtracking backtracing

Used by the ATPG in the

justification
step,
as
backtracing procedure, where
given an output objective, the
input conditions are traced in a
backward pass

three examples

The backward implication is the unique determination of all gate inputs

when the gate output and some of the inputs are given

Backward implication

s-a-1
D
x

D-Frontier

Fault Cone

Fault cone set of hardware that can be reached while performing a forward
tracing, starting at the fault site
D-frontier
D
frontier set of gates closest to POs with D or D at the input and X at the
output

x
0

1
0

Fault cone and D-frontier

fault propagation

line justification internal signal assignments previously made to sensitize

or propagate are justified by setting PIs (primary inputs) of the circuit

2.

3.

Backtrack is then needed, where a previously made assignment is discarded,

and an alternate assignment selected

A conflict may arise when an assignment contradicts with a previously made

assignment
g

the fault effect is propagated to a PO (primary output)

fault sensitization a fault is activated by forcing the signal driving it to the

opposite value from the fault

1.

Preferred ATPG method, consisting of three steps

Path sensitization method

s-a-0
D
g

Step1:

assuming the second input s-a-0, fault activation requires that this
node be controlled to logic 1, thus causing a D downstream of the
fault

Path sensitization of this circuit will demonstrate conflict

conflict, and backtrack
backtrack.

Circuit example for path sensitization

(1)

s-a-0
D

D
c

all off-path
off path values must be non-controlling,
non controlling ii.e.
e g=1
g=1, f=0
indeed, D-bar shows up at the output

backtracing f=0 requires that both inputs of the OR gate be at logic 0

this creates a conflict since the nodes downstream of the fault should be at D
backtracking is needed

Step3: justification

Step2: fault propagation, decision path scenario is a-b-c-z

Circuit example for path sensitization

(2)

s-a-0
D

this solution must be abandoned as the fault does not propagate to a PO

the D-frontier is said to disappear

backtrack again
backtrack,

Step2: backtracking, we try simultaneous propagation through paths a-b-c-z

and ff-zz

Circuit example for path sensitization

(3)

s-a-0
1

D propagates through the first OR if the other input is set to logic 0

c=0, which allows successful propagation of D to z

a=1 causes c=0

this creates a conflict again
again,
backtracking is needed, again

Step3: justifying

Step2: backtracking, we try path f-z

Circuit example for path sensitization

(4)

g=0 causes c=0

no conflict remains, the vector is discovered as 010x

s-a-0

Step3: justifying

0
1
z

Circuit example for path sensitization

(5)

s-a-0

Z=D

remember that we do not have access to probe or control any of the

internal nodes while doing the test measurement

So, what have we achieved so far ?

E=x

C=0

B=1

A=0

Circuit example for path sensitization

(6)

Z=1 in the good machine, and

Z=0 in the failing machine

The test for the s-a-0 fault is vector ABCD=010x, and produces output

In conclusion

Circuit example for path sensitization

(7)

 however, a number of extra steps must be taken in order to

to have an algorithm that can be processed by a machine

The path sensitization method works fine

So, what do we do now ?