INTERFACING LABORATORY
Presentation Slides:
www.sathieshkumar.com/tutorials
Presented By,
Overview
1.
2.
3.
4.
5.
6.
7.
Set
if there
was
a carry during
addition or
borrow during
subtraction/comparison/rotation.
Stack pointer (SP): It is a 16-bit register, points to the top of the stack. This register is
always decremented/incremented by 2 during push and pop instructions.
Program counter (PC): It is a 16-bit register, points to the next instruction to be
executed.
10
11
12
AHEAD:
//Opcodes
MVI C,00
//0E 00
//C <=00
LDA 8150
//3A 50 81
MOV B,A
//47
//B <= A
LDA 8151
//3A 51 81
ADD B
//80
//A <=A+B
JNC AHEAD
//D2 0E 80
INR C
//0C
STA 8152
//32 52 81
MOV A,C
//79
//A <=C
STA 8153
//32 53 81
HLT
//76
//Program End
AHEAD:
//Opcodes
LHLD 8050
//2A 50 80
XCHG
//EB
LHLD 8052
//2A 52 80
MVI C,00
//0E 00
DAD D
//19
//HL <= HL+DE (If SUM > 16 bits, CARRY flag is set)
JNC AHEAD
//D2 0E 80
INR C
//0C
SHLD 8054
//22 54 80
MOV A,C
//79
// A <=C
STA 8056
//32 56 80
HLT
//76
//End of Program
// EXAMPLE-> A645+9B23=014168
// STORE-> 8050=45,8051=A6,8052=23,8053=9B
// Answer-> C054=68,C055=41,C056=01
# ORG 8050
# DB 45H,A6H,23H,9BH
14
AHEAD:
//Opcodes
MVI C,00
//0E 00
LDA 8150
//3A 50 81
// A <=8150
MOV B,A
//47
// B <=A
LDA 8151
//3A 51 81
// A <=8151
SUB B
//90
// A <= A-B
JNC AHEAD
//D2 10 80
CMA
//2F
INR A
//3C
INR C
//0C
STA 8152
//32 52 81
MOV A,C
//79
// A <= C
STA 8153
//32 53 81
HLT
//76
// End of Program
//95H-35H=60H(DIFFERENCE) BORROW=00H
# ORG 8150
# DB 65H,95H
15
AHEAD:
//Opcodes
MVI C,00
//0E 00
LHLD 8150
//2A 50 81
XCHG
//EB
// D <=H, E <=L
LHLD 8152
//2A 52 81
MOV A,E
//7B
// A <= E
SUB L
//95
// A <= A-L
STA 8154
//32 54 81
MOV A,D
//7A
// A <= D
SBB H
//9C
STA 8155
//32 55 81
JNC AHEAD
//D2 19 80
INR C
//0C
CMA
//2F
INR A
//3C
MOV A,C
//79
// A <= C (CARRY)
STA 8156
//32 56 81
HLT
//76
// End of Program
16
LOOP2:
LOOP1:
MVI D,00
//16 00
// D <= 00
LDA 8150
//3A 50 81
MOV B,A
//47
// B <= A
LDA 8151
//3A 51 81
MOV C,A
//4F
// C <= A
MVI A,00
//3E 00
ADD B
//80
// A <= A+B
JNC LOOP1
//D2 11 80
INR D
//14
// D <= D+1
DCR C
//0D
// C <= C-1
JNZ LOOP2
//C2 0C 80
STA 8152
//32 52 81
MOV A,D
//7A
// A <= D
STA 8153
//32 53 81
HLT
//76
// End of Program
# ORG 8150H
# DB FFH,FFH
17
LOOP2:
LOOP1:
LDA 8150
//3A 50 81
MOV B,A
//47
// B <= A
LDA 8151
//3A 51 81
MVI C,00
//0E 00
CMP B
//B8
JC LOOP1
//DA12 80
SUB B
//90
// A <= A-B
INR C
//0C
// C <= C+1
JMP LOOP2
//C3 09 80
STA 8152
//32 52 81
MOV A,C
//79
// A <= C
STA 8153
//32 53 81
HLT
//76
// End of Program
// if A>B => C=0, Z=0 & S=0; A<B => C=1 & S=1; A=B => Z=0 & S=0
# ORG 8150H
//08(DIVIDEND-8151)/03(DIVISOR-8150)= QUOTIENT=02(8153) REMAINDER=02(8152)
# DB 03H,08H
18
W:
X:
Y:
MVI D,05
LXI H,C020
// HL <= C020
MVI C,05
// C <= 05 (Counter)
MOV A,M
INX H
// HL <= HL+1
MOV B,M
CMP B
// if A>B => C=0, Z=0 & S=0; A<B => C=1 & S=1; A=B => Z=0 & S=0
JC Y
MOV M,A
// M <= A
DCX H
// HL <= HL-1
MOV M,B
// M <= B
INX H
// HL <= HL+1
DCR C
// C <= C-1
JNZ X
DCR D
// D <= D-1
JNZ W
HLT
// End of Program
SWAPPING
19
W:
X:
Y:
MVI D,05
LXI H,C020
// HL <= C020
MVI C,05
// C <= 05 (Counter)
MOV A,M
INX H
// HL <= HL+1
MOV B,M
CMP B
// if A>B => C=0, Z=0 & S=0; A<B => C=1 & S=1; A=B => Z=0 & S=0
JNC Y
MOV M,A
// M <= A
DCX H
// HL <= HL-1
MOV M,B
// M <= B
INX H
// HL <= HL+1
DCR C
// C <= C-1
JNZ X
DCR D
// D <= D-1
JNZ W
HLT
// End of Program
SWAPPING
20
REPEAT:
SKIP:
MVI C,05
LXI H,C020
// HL <= C020
MOV A,M
INX H
// HL <= HL+1
DCR C
// C <= C-1
CMP M
// if A>M => C=0, Z=0 & S=0; A<M => C=1 & S=1; A=M => Z=0 & S=0
JC SKIP
MOV A,M
// A <= M
INX H
// HL <= HL+1
DCR C
// C <= C-1
JNZ REPEAT
STA C050
HLT
// End of Program
21
REPEAT:
SKIP:
MVI C,05
LXI H,C020
// HL <= C020
MVI A,00
CMP M
// if A>M => C=0, Z=0 & S=0; A<M => C=1 & S=1; A=M => Z=0 & S=0
JNC SKIP
MOV A,M
// A <= M
INX H
// HL <= HL+1
DCR C
// C <= C-1
JNZ REPEAT
STA C050
HLT
// End of Program
22
REPEAT:
SKIP:
LDA 8150
MOV D,A
// D <= A
LXI H,8151
MVI A,00
MVI C,00
MOV B,M
// B <= M
INX H
// HL <= HL+1
ADD B
// A <= A+B
JNC SKIP
INR C
// C <= C+1
DCR D
// D <= D-1
JNZ REPEAT
STA 8161
MOV A,C
// A <= C
STA 8162
HLT
// End of Program
# ORG 8150
# DB 05H,01H,FFH,A0H,89H,54H
23
X:
MVI C,09
LXI H,C050
MOV A,M
// A <= M
INX H
// HL <= HL+1
MOV B,M
// B <= M
INX H
// HL <= HL+1
ADD B
// A <= A+B
DAA
// Content of A is changed from binary to 4-bit BCD digits. if lower or higher order 4-bits is greater
than 9, then the instruction adds 06 to lower or higher order 4-bits
MOV M,A
// M <= A
DCX H
// HL <= HL-1
DCR C
// C <= C-1
JNZ X
RST 1
# ORG C050
# DB 01H,01H
24
LOOP1:
LOOP2:
GO:
LXI H,8100
// HL <= 8100
MOV C,M
// C <= M
MOV E,M
// E <= M
DCR E
// E <= E-1
INX H
// HL <= HL+1
DCR C
// C <= C-1
MOV M,C
// M <= C
JNZ LOOP1
LXI H,8100
// HL <= 8100
MOV A,M
// A <= M
INX H
// HL <= HL+1
MOV B,M
// B <= M
MOV C,A
// C <= A
MVI A,00
ADD B
// A <= A+B
DCR C
// C <= C-1
JNZ GO
MOV M,A
// M <= A
DCR E
// E <= E-1
JNZ LOOP2
STA 8500
HLT
// End of Program
# ORG 8100H
# DB 05H
//RESULT(8500)=78H (DECIMAL 5!=120)
25
STA 8151
LDA 8150
MOV B,A
// B <= A
ANI 0F
MOV C,A
// C <= A
MOV A,B
// A <= B
ANI F0
RLC
// Accumulator content is rotated left by one bit position. D0 <= D7 and CARRY= D7
RLC
RLC
RLC
LOOP1:
CMP C
// if A>C => CARRY=0, Z=0 & S=0; A<C => CARRY=1 & S=1; A=C => Z=0 & S=0
JNZ LOOP1
MVI A,FF
// A <= FF
STA 8151
HLT
// End of Program
# ORG 8150H
# DB 98H
//RESULT(8151)=00H (NOT A PALINDROME NUMBER EX-98H)
//RESULT(8151)=FFH (PALINDROME NUMBER EX-BBH)
26
LOOP1:
LOOP2:
MVI C,01
// C <= 01
MVI E,01
// E <= 01
LDA 8500
SUB C
// A <= A-C
JZ LOOP2
INR C
// C <= C+1
INR C
// C <= C+1
INR E
// E <= E+1
JMP LOOP1
MOV A,E
// A <= E
STA 8502
HLT
// End of Program
# ORG 8500H
# DB 40H
//RESULT(8502)=08H
27
A0
PORT SELECTED
PORTA
PORTB
PORTC
Control Register
29
30
31
32
0x23
PORTA
0x20
PORTB
0x21
PORTC
0x22
Socket Connections
1
2
3
4
5
6
A
A
A B A B
Control Word
(Clockwise)
B
B
0 1 1 1
0x07
1 0 1 1
0x0B
1 1 0 1
0x0D
1 1 1 0
0x0E
+12 V
33
Control Word
(Clockwise)
0 0 1 1
0x03
1 0 0 1
0x09
1 1 0 0
0x0C
0 1 1 0
0x06
PA1
A
PA0
B
Control
Word
(Clockwise)
0x04
0x05
0x07
0x06
34
// PORTA=0x20H
35
MVI B,10H
LOOP2:
MVI A,FFH
LOOP1:
NOP
NOP
NOP
NOP
DCR A
JNZ LOOP1
DCR B
JNZ LOOP2
RET
36
// PORTA=0x20H
37
MVI B,10H
LOOP2:
MVI A,FFH
LOOP1:
NOP
NOP
NOP
NOP
DCR A
JNZ LOOP1
DCR B
JNZ LOOP2
RET
38
EAST
R1B
R1B
P2B
P2B
EG1
SG3
SG2
WY
WG1
WG2
P1C
R2C
WG3
P2A
P2A
R1A
R1A
WEST
SOUTH
SG1
SY
SR
NR
NY
NG2
NG3
WR
P1D
P1C R2C
ER
NG1
R2D
EG3
EY
R2D P1D
NORTH
EG2
39
B7
P1D
P2A
P1C
P2B
R2C
R1A
R2D
B0
R1B
A7
NR
&SR
ER &
WR
EY &
WY
NY &
SY
A0
NG3
NG2 EG2 & EG3 &
&SG1 & SG2 WG2 WG1
0- LED OFF
1- LED ON
X- Dont Care (0 or 1)
C7
X
C0
SG3 & EG1 &
NG1 WG3
40
R
P
R
R
4
R
R
P
R
R
R
R
R
41
LOOP:
MVI A,80H
//I/O Mode
OUT 23H
MVI A,0FH
// For pedestrian
OUT 21H
MVI A,4DH
OUT 20H
CALL DELAY
// Sequence delay
CALL AMBER
// Amber delay
MVI A,8BH
OUT 20H
CALL DELAY
CALL AMBER
MVI A,49H
OUT 20H
MVI A,01H
OUT 22H
CALL DELAY
42
OUT 22H
CALL AMBER
MVI A,89H
OUT 20H
MVI A,02H
OUT 22H
CALL DELAY
MVI A,00H
OUT 22H
MVI A,30H
OUT 20H
MVI C,04H
CALL DELAYSUB
MVI A,C0H
OUT 20H
MVI A, F0H
44
MVI A,39H
OUT 20H
MVI C,08H
CALL DELAYSUB
RET
DELAY SUBROUTINE:
MVI C,40H
CALL DELAYSUB
RET
45
L3:
MVI D,FFH
L2:
MVI A,FFH
L1:
NOP
DCR A
JNZ L1
DCR D
JNZ L2
MOV A,C
JZ OUT
DCR C
JNZ L3
OUT:
RET
46
I out
I ref
D7 D6 D5 D4 D3 D2 D1
D0
)
= I ref ( +
+
+
+
+
+
+
2
4
8 16 32 64 128 256
2mA
47
48
//I/O mode
OUT 23H
START:
MVI A,00H
OUT 20H
CALL DELAY
MVI A,FFH
OUT 20H
CALL DELAY
JMP START
DELAY:
MVI B,05H
LOOP1:
MVI C,FFH
LOOP2:
DCR C
//Delay Subroutine
JNZ LOOP2
DCR B
JNZ LOOP1
RET
49
//I/O mode
OUT 23H
START:
MVI A,00H
LOOP1:
OUT 20H
INR A
JNZ LOOP1
JMP START
50
1
1
=
= 606kHz
1.1RC 1.110k 150 pF
1
t = = 1.65 s
f
f =
51
Vref/2 (V)
Vin (V)
Not connected
0 to 5
5/256=19.53
2.0
0 to 4
4/256=15.62
1.5
0 to 3
3/256=11.71
1.28
0 to 2.56
2.56/256=10
When Vref/2 is not connected (open), Vref/2 is measured at 2.5 V for Vcc=5V
Step Size (Resolution) is the smallest change that can be discerned by an ADC
52
OUT 23H
MVI A,FFH
//Start of Conversion
OUT 22H
MVI A,00H
OUT 22H
MVI A,FFH
OUT 22H
CALL DELAY
IN 20H
RST 1
53
MVI A,FFH
L2:
NOP
NOP
DCR A
JNZ L2
DCR B
JNZ L1
RET
54
SUMMARY
8085 MICROPROCESSOR
55