EC2308 MICROPROCESSOR AND MICROCONTROLLER LAB

Ex. No: 1

16 BIT ARITHMETIC OPERATIONS

a) ADDITION
ALGORITHM:

I.
II.
III.
IV.
V.
VI.
VII.
VIII.
IX.
X.

Initialize the SI register to input data memory location

Initialize the DI register to output data memory location
Initialize the CL register to zero for carry
Get the 1st data into accumulator.
Add the accumulator with 2nd data
Check the carry flag, if not skip next line
Increment carry(CL Reg)
Move the result from accumulator to memory.
Also store carry register
Halt

Program:
Address

Label

STORE:

Mnemonics

Machine Code

Comments

MOV SI, 2000H

MOV DI, 3000H
MOV CL, 00H
MOV AX, [SI]
ADD AX, [SI+2]
JNC STORE
INC CL
MOV [DI], AX
MOV [DI+2], CL
INT 3

OUTPUT VERIFIACTION:
INPUT
2000H
2001H
2002H
2003H
OUTPUT
3000H
3001H
3002H

DATA 1
34
12
78
56
AC
68
00

b) SUBTRACTION

DATA 2

DATA 2

ALGORITHM:

I.
II.
III.
IV.
V.
VI.
VII.
VIII.
IX.
X.
XI.

Initialize the SI register to input data memory location

Initialize the DI register to output data memory location
Initialize the CL register to zero for borrow
Get the 1st data into accumulator.
Subtract the accumulator with 2nd data
Check the carry flag, if not set skip next line
Increment carry(CL Reg)
2s Compliment Accumalator
Move the result from accumulator to memory.
Also store carry register
Halt

Program:
Address

Label

STORE:

Mnemonics

Machine Code

Comments

MOV SI, 2000H

MOV DI, 3000H
MOV CL, 00H
MOV AX, [SI]
SUB AX, [SI+2]
JNC STORE
INC CL
NEG AX
MOV [DI], AX
MOV [DI+2], CL
INT 3

OUTPUT VERIFIACTION:
INPUT
2000H
2001H
2002H
2003H
OUTPUT
3000H
3001H
3002H

DATA 1
88
44
33
22
55
22
00

C) MULTIPLICATION
ALGORITHM:

DATA 2

DATA 2

I.
II.
III.
IV.
V.
VI.

GET MULTIPLIER INTO ACCUMULATOR FROM MEMORY

GET MULTIPLICAND INTO BX REGISTER
MULTIPLY AX AND BX
STORE LOWER ORDER WORD FORM ACCUMULATOR INTO MEMORY
STORE HIGHER ORDER WORD FROM DX INTO MEMORY
HALT

Program:
Address

Label

Mnemonics

MOV
MOV
MUL
MOV
MOV
INT 3

Machine Code

Comments

AX, [2000H]
BX, [2002H]
BX
[3000], AX
[3002], DX

OUTPUT VERIFIACTION:
INPUT
2000H
2001H
2002H
2003H
OUTPUT
3000H
3001H
3002H
3003H

DATA 1

DATA 2

0A
00
0A
00
64
00
00
00

D)DIVISION

I.
II.
III.
IV.
V.
VI.

GET DIVIDEND INTO ACCUMULATOR FROM MEMORY

GET DIVISOR INTO BX REGISTER
DIVIDE AX BY BX
STORE QUOTIENT FORM ACCUMULATOR INTO MEMORY
STORE REMAINDER FROM DX INTO MEMORY
HALT

Program:

DATA 2

Address

Label

Mnemonics

MOV
MOV
DIV
MOV
MOV
INT 3

Machine Code

Comments

AX, [2000H]
BX, [2002H]
BX
[3000], AX
[3002], DX

OUTPUT VERIFIACTION:
INPUT
2000H
2001H
2002H
2003H
OUTPUT
3000H
3001H
3002H
3003H

Ex.No: 2
a)

DATA 1

DATA 2

68
00
0A
00
0A
00
04
00

Searching & Sorting

Largest/Smallest No. in an array

Algorithm:
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.

Load starting address of array in to SI reg.

Load length of array in CL reg.
Get the 1st element into Accumulator
Update SI and CL registers
Compare Accumulator with next element
Check carry flag, if not set skip next line
Swap accumulator with SI reg.
Decrement counter

DATA 2

ix.
x.
xi.

If not zero, goto step iv.

Else, store result.
Halt

Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV SI, 2000H

MOV DI, 3000H
MOV CL, [SI]
NEXT:

INC SI
MOV AL, [SI]
DEC CL
INC SI
CMP AL, [SI]
JNB SKIP/ JB SKIP
MOV AL, [SI]

SKIP:

DEC CL
JNZ NEXT
MOV [DI], AL
INT 3

OUTPUT VERIFIACTION:
INPUT

DATA 1

2000H(COUNT)

05

2001H

AA

2002H

BB

2003H

CC

2004H

55

2005H

77

DATA 2

DATA 2

OUTPUT
3000H

LARGEST : CC
SMALLEST: 55

b)

To Search for a BYTE in an array.

Algorithm:
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.
xi.
xii.
xiii.

Load starting address of array in to SI reg. and initialize DI reg for result.
Load the byte to be searched in DL reg. & initialize BH reg for position as 01
Get the 1st element into Accumulator
AGAIN : Compare Accumulator with DL reg
Check zero flag, if set goto AVAIL
Update SI and Increment BL
Get next element into Accumulator and compare with EOA
If not zero, goto AGAIN.
Initialize CX reg to zero
Store result for Not Available and goto END
AVAIL: Get word for available in to BL reg.
Store position, address and status of serach.
END: Halt

Program:
Address

Label

Mnemonics

MOV SI, 2000H

MOV DI, 3000H
MOV DL, [DI]
MOV BH, 01
MOV AL, [SI]
AGAIN:

CMP AL, DL
JZ AVAIL

Machine Code

Comments

INC SI
INC BL
MOV AL, [SI]
CMP AL, E0
JNZ AGAIN
NOTAVL

MOV CX, 0000H

MOV [DI+1], CX
MOV [DI+3], CX
JMP END

AVAIL:

MOV BL, FF
MOV [DI+1], BX
MOV [DI+3], SI

END:

INT 3

OUTPUT VERIFIACTION:
INPUT

DATA 1

3000H(BYTE)

05

2000H

AA

2001H

BB

2002H

CC

2003H

55

2004H

77

DATA 2

DATA 2

2018H

05

2032H

EO

OUTPUT

c)

3000H

05

3001H

FF

3002H

19

3003H

18

3004H

20

Ascending/Descending order
Algorithm:
i.
Load SI reg with pointer to array
ii.
Load array length to CL & CH for two counters (CL for repetitions & CH for comparisons)
iii.
REPEAT : Get an element into accumulator
iv.
NEXT: Compare with next element
v.
Check carry flag, if set goto SKIP
vi.
Swap elements of array
vii.
SKIP: Decrement CH and if not zero go to NEXT
viii. Decrement CL , if not zero go to REPEAT
ix.
Halt
Program:

Address

Label

Mnemonics

Machine Code

Comments

MOV SI, 1500H

MOV CL, [SI]
DEC CL
REPEAT:

MOV SI, 1500H

MOV CH, [SI]
DEC CH
INC SI

NEXT:

MOV AL, [SI]

INC SI
CMP AL, [SI]
JC SKIP/JNC SKIP
XCHG AL, [SI]
XCHG AL, [SI - 1]

SKIP:

DEC CH
JNZ NEXT
DEC CL
JNZ REPEAT
INT 3

OUTPUT VERIFIACTION:
INPUT

DATA 1

1500(COUNT)

07

1501

AA

1502

BB

1503

CC

1504

55

1505

77

1506

11

1507

99

DATA 2

DATA 2

OUTPUT

1501

11

1502

55

1503

77

1504

99

1505

AA

1506

BB

1507

CC

EX.NO: 3

STRING MANUPULATION

a) Block Transfer
Algorithm:
i.
ii.
iii.
iv.
v.
vi.

Initialize DS & ES registers

Load source and destination locations to index regs.
Load block size in counter reg.
Clear Direction flag for Auto- incrementing mode
Copy contents from source to destination address until counter becomes zero.
Halt.

Program:
Address

Label

Mnemonics

Machine Code

Comments

TRANSFER
:

MOV AX, 0000H

MOV DS, AX
MOV ES, AX
MOV SI, 2001H
MOV DI, 3000H
MOV CX ,[2000H]
CLD
MOVSB
LOOP TRANSFER
INT 3

OUTPUT VERIFIACTION:
INPUT
2000H (Block
Size)
2001H
2002H
2003H
2004H
2005H
OUTPUT
3000H
3001H
3002H
3003H
3004H

DATA 1

DATA 2

DATA 2

05
12
34
56
78
9A
12
34
56
78
9A

b) Table search
Algorithm:
i.
Initialize BX reg with table size
ii.
Get address of table and symbol in DI & SI reg.
iii.
Clear direction flag.
iv.
Load counter with 08(length)
v.
Compare bytes if successful goto FOUND
vi.
Point to the next symbol
vii.
Decrement BX, if not zero repeat the steps
viii. Show not found
ix.
FOUND: Show found status.
x.
Halt
Program:
Address

Label

Mnemonics

Machine Code

Comments

LOOP1

NOTFOUND:
FOUND:
END:

MOV BX, Table Size

LES DI, [3000H]
MOV DX, DI
LDS SI, [2000H]
CLD
MOV CX , 08
REPE CMPSB
JE FOUND
ADD DX, 0020H
MOV DI, DX
MOV SI, [SI+8]
DEC BX
JNE LOOP1
MOV AL, 00H
MOV [3000H], AL
JMP END
MOV AH, FFH
MOV [3000H], AH
INT 3

OUTPUT VERIFIACTION:
INPUT
3000H
3001H
3002H
3003

00
30
00
00

2000H
2001H
2002H
2003H

00
12
00
00

Note: The table has to be loaded from memory location 3000H & the search string in 1200H.
Table size can be any 16 bit number
c) Code Conversion
Algorithm
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.

Initialize BX reg with address of translation table

Load source and destination address in SI & DI reg.
Clear direction flag
Load counter with length
Get first element into AL , check whether the input is valid
If invalid go to end
Else translate code from table
Store code
Loop until counter becomes zero
Halt
Program:

Address

Label

Mnemonics

Machine Code

Comments

MOV BX, 1200H

MOV SI, 2000H
MOV DI, 3000H
CLD
MOV CX , Length
CONVERT: LODSB
CMP AL, 09H
JA INVALID
XLAT
STOSB
LOOP CONVERT
INT 3
INVALID:
MOV AL, 00
MOV [DI], AL
INT 3
OUTPUT VERIFIACTION:
INPUT
2000H
(DECIMAL
DIGIT)
2001
OUTPUT
3000H
3001H

DATA 1

DATA 2

DATA 2

03
05
4F
6D

CONVERSION TABLE: LOAD FROM Memory Address: 1200H

BCD
digit

7
segment
code

3F

06

5B

4F

66

6D

7D

07

7F

6F

d) Find & Replace

Algorithm:

i.
ii.
iii.
iv.
v.
vi.
vii.

viii.
ix.

Initialize DS & ES registers

Load destination index regs. With address of string
Load counter reg.
Load AL with the string to be found
Clear Direction flag for Auto- incrementing mode
Scan for the string
If found replace with the other string in AH
Continue until counter cleared
Halt

Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV AX, 0000H

MOV DS, AX
MOV ES, AX
MOV AL, [2001H]
MOV DI, 3000H
MOV CX ,[2000H]
CLD
REPNZ SCASB
JNZ DONE
MOV AH, [2002H]
MOV [DI 1], AH
JMP LOOP1
INT 3

LOOP1:

DONE:

OUTPUT VERIFIACTION:
INPUT
2000H
(COUNT)
2001H
2002H

DATA 1

DATA 2

DATA 2

05
CC
AA

3000H
3001H
3002H
3003H
3004H
OUTPUT

11
CC
22
CC
33

3000H
3001H
3002H
3003H
3004H

11
AA
22
AA
33

Ex.No: 4

ADC & DAC

a) DAC Interfacing
Square wave:
i.
Initialize 8255 by sending Control Word to Control Reg.
ii.
Get High into accumulator; send to DAC through output port
iii.
Call delay sub routine
iv.
Get Low into accumulator; send to DAC through output port
v.
Continue cycle
Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV DX,FF56H
MOV AL,80H
OUT DX,AL
MOV DX,FF52H

8255 Control Reg address

Control word to put ports as output ports
Send to control reg

MOV AL,FFH
OUT DX,AL
CALL DELAY

High into acc.

Send to DAC through output port

MOV AL,00H

Low value into acc.

OUT DX,AL

Send to DAC through output port

CALL DELAY

Call delay routine

JMP START

Continue cycle

DELAY:

MOV CX,07FFH

Delay count

CONT:

NOP

Wait state

START:

Port B address

Call delay routine

NOP
DEC CX

Decrement count

JNZ CONT

If not zero continue

RET

Else return to main program

OUTPUT VERIFICATION: (Plot the Wave form in Graph.)

Count value
07HH

Amplitude

(V)

2V

Time period (ms)

0.4 ms

Stair case wave:

Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV DX, FF56H

MOV AL,80H
OUT DX,AL
MOV DX, FF52H
START:

MOV AL, 00H

OUT DX, AL
CALL DELAY
ADD AL, 55H
OUT DX, AL
CALL DELAY
ADD AL, 55H
OUT DX, AL
CALL DELAY
ADD AL, 55H
OUT DX, AL
CALL DELAY
CALL DELAY
SUB AL, 55H
OUT DX, AL
CALL DELAY
SUB AL, 55H
OUT DX, AL
CALL DELAY
SUB AL, 55H
OUT DX, AL
CALL DELAY
JMP START

DELAY:

MOV CX, 0AFFH

CONT:

NOP
NOP
DEC CX
JNZ CONT
RET

b) ADC
Algorithm:
i.

Initialize 8255 by sending control word to control reg.

ii.

Initialize measurement and get input to ADC

iii.

Close measurement.

iv.

Call delay.

v.

Read the digital output

vi.

Halt

Procedure:
i.

Connect ADC interfacing Kit with VIK-86 Kit through bus

ii.

Connect power supply to ADC kit

iii.

Load program

iv.

Set input voltage by Adjusting POT resister in ADC Kit and measure using Multimeter.

v.

Execute program and read the digital output from the VIK 86 kit.

Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV

DX, FF56H

8255 Control reg address

MOV

AL, 90H

OUT

DX, AL

Control Word for initializing ports as I/P

ports
Send to control reg

MOV

DX, FF54H

Port C address

MOV

AL, FFH

Disable signal for ADC

OUT

DX, AL

Send to ADC port

MOV

AL, 00

SOC signal for ADC

OUT

DX, AL

Send to ADC port

MOV

AL, FFH

Close measurement signal

OUT

DX, AL

Send to ADC

CALL DELAY

Call delay routine

CALL DELAY
MOV
IN

DX, FF50H
AL, DX

INT

Port A address
Read Port A which has Output of ADC

Break point

DELAY:

MOV CX, 0FFFH

Delay count

CONT:

NOP

Wait state

NOP
DEC CX

Decrement count

JNZ CONT

If not zero continue

RET

Else return to main program

OUTPUT VERIFICATION:
Analog Input (V)

Digital Output

5V

FFH

2.5 V

7AH

Ex. No: 5
Transmitter:

PARALLEL COMMUNICATION

Algorithm:
i.

Initialize the 8255 with output ports by sending control word

ii.

Send the clear signal to receiver

iii.

Get the Byte to be transmitted into Accumulator

iv.

Send it to output port

v.

Send the Enable signal and close communication

vi.

Halt

Program:

Address

Label

Mnemonics

Machine Code

MOV

DX, FF26H

MOV

AL,82H

OUT

DX,AL

MOV

DX, FF24H

Port C for Clear signal

MOV

AL,00H

Clear signal

OUT

DX,AL

Send clear signal

MOV

DX, FF20H

MOV AL,55H(Byte)

Control Word for Initializing

ports as O/P
Load control word

Port A Output port for

transmitting Byte
55H byte to be transmitted

OUT

DX,AL

MOV

DX, FF24H

Port C for Enable signal

MOV

AL, FFH

Enable signal

OUT

DX,AL

Send Enable signal

INT 3
Receiver:
Algorithm:
i.

Comments
8255 Control Reg

Initialize 8255 with input ports by setting control reg.

Transmit byte

Break point

ii.

Read & Check for Clear signal from Transmitter

iii.

Check and wait for Enable signal

iv.

Read input port

v.

Show the data

vi.

Halt
Program:

Address

Label

CHECK:

Mnemonics

MOV

DX,FF26H

MOV

AL,99H

OUT

DX,AL

MOV

DX,FF24H

Machine Code

Comments
Control Reg. of 8255
Control word for initializing ports as
I/P
Port C for Enable signal

IN AL,DX

Read Port C

JZ

Go back and wait for Enable

CHECK

MOV

DX,FF20H

Port A input data

IN AL,DX

Read data form transmitter

INT 3H

Break Point

Procedure:
i.

Connect two VIK 86 kits using data cable

ii.

Load Transmitter program in One kit and Receiver in the other kit

iii.

Execute Receiver and then Transmitter and again Reciver.

iv.

AL in Receiver will show the Byte Transmitted

Ex.No: 6
8279:
Keyboard Interfacing:

INTERFACING 8279, 8259 & 8253

Algorithm:
i.

Initialize 8279 with control word to define in 8 bit 8 character display

ii.

Initialize clock pre scalar for frequency division

iii.

Load display write inhibit word

iv.

Read FIFO RAM status if empty wait

v.

Else read Data code from input port and suppress unwanted bits(b7&b6)

vi.

Break point

Address

Label

Mnemonics

Wait:

MOV

AL,12h

MOV

DX,FF52h

OUT

DX,AL

MOV

AL,3Eh

OUT

DX,AL

MOV

AL,A0h

OUT

DX,AL

IN

IN

for frequency division

display/write inhibit

read status of 8279

FIFO empty?

Wait

If Yes loop back to wait

DX,FF50h

Data register

AL,DX

AND
INT

8279 control port

AL,07h

MOV

Comments

Control word to define 8279 in 8

bit 8 character display

AL,DX

AND
JZ

Machine Code

Read Code from data port

AL,3Fh

Suppress bits 7&6

Break point

Scan codes for Keyboard:

Row/Column

24

23

22

21

1c

1b

1a

19

14

13

12

10

0c

0b

0a

09

Display interfacing:
Algorithm:
i.

Initialize 8279 with control word to define in 8 bit 8 character display

ii.

Initialize clock pre scalar for frequency division

iii.

Load display write inhibit word and count for clearing display

iv.

Clear all display and load BX reg with address of table

v.

Get the input code from table and send to display through output port

vi.

Break point

Program:
Address

Label

Clear:

Mnemonics
MOV
AL,12h

Machine Code

Comments
Control word to define 8279 in 8 bit
8 character display

MOV

DX,FF52h

OUT

DX,AL

Load to control reg

MOV

AL,3Eh

for frequency division

OUT

DX,AL

send to control reg

MOV

AL,A0h

OUT

DX,AL

display/write inhibit
send to control reg

MOV

AH,08h

Count of 8 for clearing dis.

MOV

DX,0FF50h

data register address

MOV

AL,00h

data =0

OUT

DX,AL

DEC

AH

JNZ

Clear

MOV
MOV

DX,FF50h
CL,06

8279 control port

decrement loop count

Clear up to AH= 00
Data reg
Count for digits

MOV

BX,2000h

Input display code address in BX

MOV

AL,[BX]

Read the input code

OUT

DX, AL

Back:

INC

BX

DEC

CL

JNZ

Send to output port for display

Update BX & CL reg

Loop back

Back

Note: Input data from 2000H

DIGIT

7
SEGMENT FC
CODE

60

BA F2

66

D6 DE

70

FE

76

7E CE 9C EA 9E

8259:
a) Return Interrupt number
Algorithm:
i.

Load Initialization Control Word 1 (ICW1) into control reg

ii.

Load Initialization Control Word 2 (ICW2) into data reg.

F
1E

iii.

Load Initialization Control Word 4 (ICW4) into data reg.

iv.

Load Operation Control Word (OCW) into control reg.

v.

Point to control reg

vi.

Set interrupt enable flag

vii.

Wait for interrupt to happen

viii.

ISR: Read interrupt number and break point

Program:
Address

Label
MOV

Mnemonics
DX, FF50h

MOV

AL, 1Fh

OUT

DX,AL

MOV

DX, FF52h

MOV

AL, 10h

OUT

DX,AL

MOV

DX, FF52h

MOV

AL, 03h

OUT

DX,AL

MOV

DX, FF52h

MOV

AL, 80h

OUT

DX,AL

MOV

DX, FF50h

JMP

Comments
ICW1

ICW2

ICW4

OCW1

Enable interrupt

STI
WAIT:

Machine Code

WAIT

(ISR to be loaded in
vector location of

Wait for interrupt

interrupt)
2000H

Read data reg.

IN AL,DX

Break point

INT 3

Interrupt Vector table:

Interrupt No

Vector location

Segment Address (CS)

Effective Address (IP)

IRQ0

0040H

0000H

2000H

IRQ1

0044H

0000H

2000H

IRQ2

0048H

0000H

2000H

IRQ3

004CH

0000H

2000H

IRQ4

0050H

0000H

2000H

IRQ5

0054H

0000H

2000H

IRQ6

0058H

0000H

2000H

IRQ7

005CH

0000H

2000H

OUTPUT: AL will contain the Interrupt value (The respective bit will be set with respect to interrupt No.)
IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

01

02

04

08

10

20

40

80

b) Program to do addition, subtraction and multiplication

Address

Label

Mnemonics

Machine Code

Comments

IRQ0:

MOV AX. Data1

MOV BX, data2
ADD AX, BX
IRET

IRQ1:
MOV AX. Data1
MOV BX, data2
SUB AX, BX
IRET
IRQ2:
MOV AX. Data1
MOV BX, data2
MUL BX
IRET

Interrupt vector table:

Interrupt No

Vector location

Segment Address (CS)

Effective Address (IP)

IRQ0

0040H

0000H

2000H

IRQ1

0044H

0000H

3000H

IRQ2

0048H

0000H

4000H

8253:

Algorithm:

i.

Load division factor as count in CX reg.

ii.

Select the counter reg by sending appropriate data to control reg.

iii.

Get lower order count in to AL and send to selected counter reg

iv.

Get higher order count in to AL and send to selected counter reg.

v.

Wait and terminate.

Program:
Address

Label

Mnemonics

Machine Code

Comments

MOV

AX,0050H

MOV

CX,AX

MOV

AL,36H

MOV

DX, FF56H

OUT

DX,AL

MOV

AL,CL

Count Lsb

MOV

DX, FF50H

Counter 0 Reg

OUT

DX,AL

MOV

AL,CH

OUT

DX,AL

Counter0 Is Selected
Control Reg

Count Msb

NOP
INT

Division Factor

3H

Ex.No: 7
SERIAL COMMUNICATION

Transmitter:

Algorithm:
i.
ii.
iii.
iv.
v.
vi.

Load division factor in AX and Byte to be transmitted in BL

Call the sub routine BAUDINIT.
TXLOOP: Get the Byte to be transmited into AL
Call the Subroutine TXBYTE
Jump to TXLOOP
Breakpoint.

TXBYTE:
i. Call delay routine
ii. Save the byte to another Reg from AL
iii. Load status reg address
iv. Read status word of 8251 and check ready bit(B0)
v. If zero continue checking
vi. Load mode reg address and get the Byte into AL
vii. Transmit the Byte
viii. Return to main program
BAUDINIT:
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.
DELAY:
i.
ii.
iii.
iv.
v.

Save division factor as count in CX reg.

Select the counter reg by sending appropriate data to control reg.
Get lower order count in to AL and send to selected counter reg
Get higher order count in to AL and send to selected counter reg.
Wait and get status reg Address of 8251
Send 3 Dummy mode Words to 8251
Get Reset word and send to 8251
Get mode word and Send mode word
Wait and send Enable Transmitter signal
Wait and Return to Main program

Push BX in to stack
Load Count in to Stack
Wait and Decrement count
If count not zero then continue
Else Pop Bx form stack and return to main Program

Mode word Register: FF50H

Status word Register: FF52H
Timer Address(Counter0): FF00H

Program:

Address

Label

Mnemonics

Machine Code

Comments

TXLOOP:

MOV

AX,0050H

Division Factor For Baud Count

MOV

BL,42H

Byte To Be Tx In BL Reg 'B'

CALL BAUDINIT

AX Contain Timer Count

MOV

BL - Contain The Byte To Be Tx.

AL,BL

CALL TXBYTE

TXBYTE:

LOOOP:

JMP

TXLOOP

INT

CALL DELAY
MOV

BL,AL

Save the byte

MOV

DX,FF52H

Status Reg

IN

AL,DX

AND
JZ

AL,01H
LOOOP

check the ready bit

If not ready go back to check

Restore the byte to al

MOV

AL,BL

MOV

DX,FF50H

MODE REG

OUT

DX,AL

TX THE BYTE

RET

BAUDINIT:

Get the status word

RETURN

MOV

CX,AX

Save The Count In CX

MOV

AL,36H

Counter0 is selected

MOV

DX,FF06H

(TIMADR+6H) Control Reg

OUT

DX,AL

MOV

AL,CL

Count LSB

MOV

DX,FF00H

COUNTER 0 REG

OUT

DX,AL

MOV

AL,CH

OUT

DX,AL

NOP

Count MSB

Wait

NOP
MOV

DX,FF52H

Status Register

MOV

AL,00H

Dummy Mode Word

OUT

DX,AL

OUT

DX,AL

OUT

DX,AL

MOV

AL,40H

OUT

DX,AL

Reset Word

CALL DELAY
MOV

AL,4EH

OUT

DX,AL

(01 00 11 10) ONE STOPBIT,NO

PARITY,8BITS CHAR TXC/16 BAUD

NOP
NOP
MOV

AL,27H

OUT

DX,AL

ENABLE TX

NOP
NOP
RET
DELAY:

PUSH BX
MOV BX,04FFH

D1:

NOP
NOP
DEC BX
JNZ D1
POP BX
RET

Receiver:
Algorithm:

Delay Routine

i.
ii.
iii.
iv.
RXBYTE:

Load division factor in AX

Call the sub routine BAUDINIT.
Call the Subroutine RXBYTE
Breakpoint.

i. Load Status Reg.Address of 8251

ii. CHECK: Read status word
iii. If receiver buffer empty then go back to CHECK
iv. Get Mode Register Address and Read the Byte
v. Return to main program
Program:

Address

Label

Mnemonics
MOV

AX,0050H

CALL BAUDINIT

Machine Code

Comments
Division Factor For Baud Count
AX Contain Timer Count

CALL RXBYTE
INT

RXBYTE:

MOV
IN

CHECK :

DX,FF52H
AL,DX

AND
JZ
MOV

BAUDINIT:

AL,02H
CHECK
DX,FF50H

Status Reg
Get the status word
check the Receiver Buffer bit

If not ready go back to check

MODE REG

IN DX,AL

Read the BYTE

RET

RETURN

MOV

CX,AX

Save The Count In CX

MOV

AL,036H

Counter0 is selected

MOV

DX,FF06H

(TIMADR+6H) Control Reg

OUT

DX,AL

MOV

AL,CL

MOV

DX,FF00H

OUT

DX,AL

MOV

AL,CH

Count LSB
COUNTER 0 REG

Count MSB

OUT

DX,AL

NOP

Wait

NOP
MOV

DX,FF52H

Status Register

MOV

AL,00H

Dummy Mode Word

OUT

DX,AL

OUT

DX,AL

OUT

DX,AL

MOV

AL,40H

OUT

DX,AL

Reset Word

CALL DELAY
MOV

AL,4EH

OUT

DX,AL

(01 00 11 10) ONE STOPBIT,NO

PARITY,8BITS CHAR TXC/16 BAUD

NOP
NOP
MOV

AL,27H

OUT

DX,AL

ENABLE TX

NOP
NOP
RET
DELAY:

PUSH BX
MOV BX,04FFH

D1:

NOP
NOP
DEC BX
JNZ D1
POP BX
RET

Procedure:
i.

Connect two VIK 86 kits using Serial cable

Delay Routine

ii.

Load Transmitter program in One kit and Receiver in the other kit

iii.

Execute Receiver and then Transmitter and again Receiver.

iv.

AL in Receiver will show the Byte Transmitted

Ex.No: 08
STEPPER MOTOR & DC MOTOR CONTROL

Stepper Motor
Algorithm:
Load control port address of 8255
Get Control word to initialize 8255 ports as Output ports
Send to control reg
Load 8255 Port C Address
STEP: Get initial phase position, Send to port C; Call delay routine
Get 2nd phase position, Send to port C; Call delay routine
Get 3rd phase position, Send to port C; Call delay routine
Get Final phase position, Send to port C; Call delay routine
Go back to STEP

Program:
Address

Label

STEP:

Mnemonics

Machine Code

Comments

MOV

DX, FF26H

8255 Control Reg Address

MOV

AL,80H

Control word for output ports

OUT

DX,AL

Send to control reg

MOV

DX, FF20H

Port C Address

MOV

AL,PH1

Initial Phase position

OUT

DX,AL

CALL DELAY
MOV

AL,PH2

OUT

DX,AL

2nd phase position

CALL DELAY
MOV

AL,PH3

OUT

DX,AL

3rd phase Position

CALL DELAY
MOV

AL,PH4

OUT

DX,AL

4th Phase position

CALL DELAY

DELAY:
DEL0:
DEL1:

JMP STEP

Go back to continue step

MOV

BX,0010H

Count 1

MOV

AX,00FFH

Count 2

NOP
NOP
NOP
NOP
DEC

AX

JNZ

DEL1

DEC

BX

JNZ

DEL0

Loop until AX & BX= 0

Return to program

RET

Procedure:
i) Connect Stepper motor interface with VIK-86 through data bus and connect motor with interface.
ii) Give power supply to interface kit
iii) Load program and execute to run motor
iv) Change delay Count to control Speed
v) Change phase sequence to change direction of rotation.
Phase sequence:
Direction of rotation

PH1

PH2

PH3

PH4

Clock Wise

A0H

E0H

C0H

80H

Anti Clock Wise

80H

C0H

E0H

A0H

DC Motor:

Algorithm:
i.

Load control Reg address of 8255

ii.

Get control word so as to program 8255 ports as O/P port & send to control reg

iii.

Send the start pulse to ZCD

iv.

Call delay high routine

v.

Send stop pulse to ZCD

vi.

Call delaylow

vii.

Continue cycle

Program:
Address

Label

CONT:

Mnemonics

Machine Code

Comments

MOV DX , FF26H

8255 Control Reg Address

MOV AL ,80H

Control word for output ports

OUT DX ,AL

Send to control reg

MOV AL ,01H

Start Pulse

MOV DX , FF20H

Port C Address

OUT DX ,AL
CALL DELAYHIGH
MOV AL,00H

Stop Pulse

OUT DX,AL
CALL DELAYLOW
JMP CONT

Continue Cycle

DELAYHIGH:

MOV AH,01H

Motor Speed Count ( 01 TO FF )

LOOP1:

NOP
NOP
NOP
DEC AH
JNZ

LOOP1

RET

DELAYLOW:
LOOP2:

MOV AL,01H

NOP
NOP
DEC AL
JNZ LOOP2
RET

Procedure:
i) Connect DC motor interface with VIK-86 through data bus and connect DC motor with interface.
ii) Give power supply to interface kit
iii) Load program and execute to run motor
iv) Change delay Count to control Speed

Ex.no: 10

PROGRAMMING 8051 INTERRUPTS & TIMER

a) Timer
Aim:
To program 8051 internal Timer0 to generate square waves of duty cycle 50% and 66% and output that
using IO pin P1. 2.
Algorithm:
i.
Initialize TMOD SFR for Timer0 on Mode 1 timer. ( 16 bit).
ii.
Load Count values to TL0 & TH0.
iii.
Toggle IO pin. (P1.2)
iv.
Call delay
v.
Continue cycle
Delay: start Timer
Moniter timer0 flag(TF0) until it rolls over.
Stop timer
Clear flag and return.
Program: 50% DUTY CYCLE ( Ton = Toff=D)
Address

Label

HERE:

DELAY:
CHECK:

Mnemonics

Machine Code

Comments

MOV P1, #00

Make P1 output port

MOV

TMOD, #10

Timer1 mode 1 (16 bit counter)

MOV

TL1, #F2H

Low byte

MOV

TH1, #FFH

High byte

CPL

P1.2

Toggle P1.2 pin

ACALL DALAY

Call delay routine

SJMP

Continue cycle by loading TH & TL

HERE

SETB TR1

Start timer 0
Check TF1 flag until it sets

JNB TF1 , CHECK

CLR TR1

Stop Timer &

CLR TF1

clear the flag

RET

Return to program.

SFR ADDRESSES : TMOD 89; TL1- 8B; TH1- 8D; TR1-8E; TF1 - 8F.
TL0- 8A; TH0- 8C; TR0- 8C; TF0 - 8D.
Program: 66% DUTY CYCLE ( Ton = 2D &Toff = D)

Address

Label

HERE:

Mnemonics

Machine Code

Comments

MOV P1, #00

Make P1 output port

MOV

TMOD, #10

Timer1 mode 1 (16 bit counter)

MOV

TL1, #F2H

Low byte

MOV

TH1, #FFH

High byte

SETB

P1.2

ACALL DALAY

High P1.2 pin

Call delay routine

ACALL DALAY
CLR P1.2 (Any pin in P1)

Low P1.2 pin

Call delay routine

ACALL DALAY
SJMP
DELAY:
CHECK:

HERE

Continue cycle by loading TH & TL

SETB TR1

Start timer 0

JNB TF1 , CHECK

Check TF1 flag until it sets

CLR TR1
CLR TF1

Stop Timer &

clear the flag
Return to program.

RET

CALCULATIONS:

XTAL = 10 MHz
Timer frequency, f = 10 /12 = 0.833 MHz
Time period , T = 1/0.833 = 1.2 s.
Delay, D = Count T
Count = FFFF FFF2 = 0Dh(13) + 1( for Roll over)
Now, D = 14 1.2 s = 16.8 s for 1 delay.
For 50 % duty cycle: T = Ton + T off = 2D = 33.6 s & Frequency of square wave, f = 1/T = 297.6 kHz
For 66 % duty cycle: T = Ton + T off = 3D = 54.9 s & Frequency of square wave, f = 1/T = 182.1 kHz

b) Interrupt Programming
Aim: To toggle P1.5 every second.
Address

Label

Mnemonics
MOV

TMOD, #10

001B:

TIMER1
ISR

Comments
Timer1 mode 1

MOV IE, #88

Enable Timer1 Interrupt

MOV R0, #13

Count for 1 second delay

MOV

TL1, #00H

Count value

MOV

TH1, #00H

Count value

SETB TR1
HERE:

Machine Code

SJMP

Start timer1

HERE

DJNZ R0, BACK

Check R0
Toggle IO pin

CPL

P1.5
Reload register value

MOV R0, #13

MOV

TL1, #00H

MOV

TH1, #00H

RETI

Reload count values

Return from interrupt

EX.NO: 11

COMMUNICATIONS BETWEEN 8051 KITS

Aim:
To establish communication between two 8051 Kits.
Serial Communication:
Transmitter:
Address

Label

CHECK:

Mnemonics

Machine Code

Comments

MOV

IE, #00

Disable interrupts

MOV

TMOD, #20

Timer1 in mode2

MOV

TH1, #F5H

Count for 2400 baud rate

MOV SCON, #40

Setting serial mode1

SETB TR1

Start timer1

MOV SBUF, # DATA

Byte to be transmitted serially

JNB TI , CHECK

Check for all the bits to be transmitted

CLR T1

Clear transmit interrupt flag

LCALL 00BB

Break point.

Receiver:
Address

Label

Mnemonics

Comments

IE, #00

Disable interrupts

MOV

TMOD, #20

Timer1 in mode2

MOV

TH1, #F5H

Count for 2400 baud rate

MOV SCON, #50

SETB TR1
CLR RI
CHECK:

Machine Code

MOV

JNB

RI , CHECK

MOV A, SBUF

Setting serial mode1 with receiver

enabled
Start timer1
Clear RI for reception
Check for all bits of character
Move into acculator.

LCALL 00BB

Break point.

Parallel Communication:
Transmitter:
Address

Label

Mnemonics
MOV

A, #80

MOV

DPTR, #4003

MOVX

Comments

Machine Code

Comments

@DPTR, A

MOV

DPTR, #4000

MOV

A, #DATA

MOVX

Machine Code

@DPTR, A

NOP
NOP
LCALL 00BB

Receiver:
Address

Label

Mnemonics
MOV

A, #90

MOV

DPTR, #4003

MOVX
MOV
MOVX

@DPTR, A
DPTR, #4000
A, @DPTR

LCALL 00BB

Ex.No: 09

8051 BASIC PROGRAMMING

Aim:
To program 8051 using its Arithmetic and Logical and Bit Manipulation instructions.
a) Arithmetic operations

Address

Label

Mnemonics
MOV

DPTR, #8500

MOVX A, @DPTR
MOV

B, A

MOV R0, A
INC DPTR
MOVX

A, @DPTR

MOV R1, A
ADD A, B
INC DPTR
MOVX @DPTR, A
MOV R2, A
MOV A, R1
SUBB A, B
INC DPTR
MOVX @DPTR, A
MOV R3, A
MOV B, R2
MUL AB
INC DPTR
MOVX @DPTR, A
MOV A, R2
MOV B, R3

Machine Code

Comments

DIV AB
INC DPTR
MOVX @DPTR, A
LCALL 00BB

Input: M8500 - a
M8501 - b
Output: M8502 : sum (a+b)
M8503: difference (a-b)
M8504: Product ((a+b)(a-b))
M8505: Quotient ((a+b)/(a-b))

b) 32 bit subtraction
Address

Label

Mnemonics
CLR C
MOV

A, 43

SUBB A, 53
MOV 63, A
MOV

A, 42

SUBB A, 52
MOV 62, A
MOV

A, 41

SUBB A, 51
MOV 61, A
MOV

A, 40

SUBB A, 50
MOV 60, A
LCALL 00BB

Input: I40 to 43 data 1

I50 to 53 data 2
Output: I60 to 63 - difference

Machine Code

Comments

C) Fibonacci series
Address

Label

Mnemonics
MOV

R0, 60

MOV R1, #01

MOV R2, #01
MOV A, #00
MOV DPTR, # 9000
CJNE R0, #00, BEGIN
LJMP EXIT
BEGIN:

MOVX @DPTR, A
INC DPTR

RPT:

MOV R2, A
ADD A, R1
MOV 01, 02
MOVX @DPTR, A
INC DPTR
DJNZ R0, RPT

EXIT:

LCALL 00BB

INPUT: I60 COUNT

OUTPUT: M9000 00
M9001 01
M9002 01
M9003 02 &

so on

Machine Code

Comments