Memory PDF

ELE-863 VLSI Systems
Semiconductor Memory
Fei Yuan, Ph.D, P.Eng.

Department of Electrical & Computer Engineering
Ryerson University
c 2009
Copyright
Copyright (c) F. Yuan 2009
(1)
OUTLINE
Memory Architecture
Read-Only Memory (ROM)
Static Random-Access Memory (SRAM)
Dynamic Random-Access Memory (DRAM)
(2)
MEMORY ARCHITECTURE
2-Dimensional Memory Architecture
Ak
2L-k
Memory cell
Row
decoder
(Wordline
selection)
L-1
Bit lines
Word lines
Sense amplifier
A0
A k-1
Column decoder
Input/Output
Figure 1: 2-dimensional Memory.
Used for memories of small size.

Row decoder generates word line signals. Column decoder generates
bit line signals.
Word Lines are short. Bit Lines are long. As a result, word lines
have small capacitances and bit lines have large capacitances.
(3)
MEMORY ARCHITECTURE (condd)

3-Dimensional Memory Architecture
Ak
2L-k
Row
decoder
(Wordline
selection)
Ak
Memory cell
L-1
2L-k
Row
decoder
(Wordline
selection)
L-1
Bit lines
Word lines
0
k-1
Memory cell
L-1
Bit lines
Word lines
Sense amplifier
A
Column decoder
2L-k
Row
decoder
(Wordline
selection)
Bit lines
Word lines
k-1
Ak
Memory cell
L-1
Sense amplifier
A
Column decoder
2L-k
Row
decoder
(Wordline
selection)
Bit lines
Word lines
Sense amplifier
Ak
Memory cell
Sense amplifier
A
Column decoder
k-1
Block decoder
Column decoder
k-1
Block decoder
Global data bus
Figure 2: 2-dimensional Memory.
Used for memories of large size.

Block decoders generate block selection signals. Row decoders
generate word line signals. Column decoders generate bit line
signals.
Block lines/Word lines are short and have small capacitances. Bit
lines are long and have large capacitances.
(4)
ROM
Functionality of ROM cells
Provide 1 or 0 to the bit line when the power is present and a word
line is accessed
ROM Cells
Diode Cells
Bit Line
Word Line
D
Figure 3: ROM - Diode cells.
Without the diode, Bit line voltage is always LOW O is stored.

With the diode, when Word Line = Logic-1, Bit line voltage is
HIGH 1 is stored.
No isolation between word and bit lines when Word Line=Logic-1.
Static power dissipation when Word Line is asserted.
(5)
ROM (contd)
BJT Cells
VDD
Bit Line
Word Line
Figure 4: ROM - BJT cells.
Fast response due to the large collector current of BJTs to charge

the Bit Line when Word Line=1.
No isolation between Word and Bit lines. Complex routing due to
the need for VDD in each memory cell.
(6)
ROM (contd)
MOS Cells
Bit Line
Word Line
Figure 5: ROM - MOS cells.
Complete isolation between Word Line and Bit Line by the gate
oxide.
No static power consumption.
Only GND is needed in each memory cell.
Bit lines are pre-charged to VDD. Note that pre-charge pMOS
transistors must be weak configured (small width).
(7)
ROM (contd)
Word [0]
Word [1]
Word [2]
Word [3]
CBit
Bit [0]
CBit
Bit [1]
CBit
Bit [2]
CBit
Bit [3]
Figure 6: 4x4 ROM.
Due to the large capacitance of bit lines, all bit lines are pre-charged
to Logic-1 by pseudo-nMOS logic prior to a read operation.
CLK
WORD [n]
BIT [n]
Pre-charge
Data available
Figure 7: Operation of ROM.
(8)
ROM (contd)
Metal-1
Poly
Word [0]
n+ diffusion
Word [1]
Word [2]
Word [3]
Bit [0] Bit [1] Bit [2] Bit [3]
Figure 8: Layout of 4x4 ROM.
Word lines are implemented using poly as their length is short.

GND lines are implemented using n+ diffusion and shared between
neighboring cells. The downsides (i): large resistances,(ii) large
parasitic capacitances.
Bit lines are implemented using metal interconnects to minimize
both parasitic capacitance and resistance of the lines.
(9)
SRAM
Introduction
A SRAM cell uses a cross-coupled inverter to retain the stored data
indefinitely as long as a sufficient power supply voltage is present.
To eliminate the effect of common-mode noise, particularly those in
VDD and GN D, fully differential configuration is used. There are
TWO bit lines for each bit. Bit signal is the difference between the
voltages of two bit lines. Logic state is represented by the polarity
of the differential voltage.
Because of the large parasitic capacitances of bit lines, the time
needed to charge the bit lines is significant. To avoid this difficulty,
the bit lines are pre-charged using pseudo-nMOS prior to the read
operation of the cell.
Word access transistors are nMOS to minimize chip area and
minimize speed.
Word Line
Bit Line
C Bit
Bit Line
C Bit
Figure 9: SRAM cells.
(10)
SRAM (contd)
Resistive-Load SRAM cell
Word Line
Bit Line
C Bit
Bit Line
C Bit
Figure 10: Resistive SRAM cells.
Static power consumption exists.

Large resistance is needed to minimize static power consumption
Slow response due to large time constant.
(11)
SRAM - Cell Configurations (contd)

Full CMOS SRAM cell
Word Line
Bit Line
C Bit
Bit Line
C Bit
Figure 11: MOSFET SRAM cell.
Lowest static power consumption (leakage current of pn-junctions

and sub-threshold conduction)
superior swing speed
Large noise margin : VOL = 0 and VOH = VDD .
.
(12)
SRAM Cells - Read Operation
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
Figure 12: MOSFET SRAM cell - read operation.
The two bit lines are pre-charged to logic-1 by pseudo-nMOS logic.

Word line signal is asserted (Word Line=Logic-1).
If a 0 is stored in the cell (VCcell =Logic-0), then the charge stored
in CBit will be shared between CBit and Ccell VBit drops slightly
because CBit Ccell . VCcell remains unchanged a small
differential voltage (V = VBit VBit 100mV) across the two bit
lines will be generated.
If a 1 is stored in the cell (VCcell = Loigc 1), one can also show a
small differential voltage (VBit VBit 100mV) is generated
across the two bit lines.
There exists a one-to-one mapping between the data stored in the
cell and the polarity of the differential voltage cross the bit lines.
This small voltage difference will be amplified by a sense amplifier
to full swing.
(13)
SRAM Cells - Write Operation
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
Figure 13: MOSFET SRAM cell - write operation.
The bit lines are brought to Logic-1 or Logic-0 by the write

circuitry.
Word line signal is asserted (Word line=Logic-1).
If the cell stored a 1, and a 0 is to be written into the cell,
VBit = Loigc 0 and VBit = Loigc 1. The charge stored in Ccell
will be shared between CBit and Ccell Because CBit Ccell , Ccell
will be discharged to Logic-0 and Ccell will be charged to Logic-1
0 is written into the cell.
If the cell stored a 0, and a 1 is to be written into the cell,
VBit = Loigc 1 and VBit = Loigc 0. The charge stored in CBit
will be shared between CBit and Ccell Ccell will be charged up to
Logic-1 1 is written into the cell.
(14)
SRAM (contd)
Design of SRAM Cells
Objectives
Determine W/L of the transistors in SRAM cells.
Constraints
Constraints in Read Operation - a read operation must not destroy
the stored information in the cell.
Constraints in Write Operation - the cell must allow the
modification of the stored information.
(15)
SRAM (contd)
Design of SRAM cells - Read Operation
Assume a 0 is stored in the cell (VA = Logic 0), the read
operation will increase the voltage at node A. The voltage at node
A during the read operation must not exceed the threshold voltage
of the right inverter (M2,6).
Bit lines are pre-charged. VCbit = VCbit = 1. When Word
line=Logic-1, M3 and M4 are ON.
VCBit remains unchanged while VCBit drops slightly node A is
charged. If VA exceeds the threshold voltage of the right inverter,
then VB = 0 the stored data are destroyed VA must not
exceed the threshold voltage of the right inverter. A similar
requirement applies to VB as well.
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
Figure 14: MOSFET SRAM cell - read operation.
(16)
SRAM (contd)
Because initially VCBit = VDD , VA = 0, Vds,3 is large M3 is in
saturation. Equating the current of M3 and M1 (Note M1 is in the
triode because Vds,1 = VOL is small)
Ids,3 =
kn3
kn3
(Vgs,3 Vtn )2 =
(VDD VA Vtn )2 ,
2
2
(1)
(2)
Ids,1 = kn1
"
1 2
1
(Vgs,1 Vtn )Vds,1 Vds,1
= kn1 (VDD Vtn )VA VA2 . (3)
2
2
(4)
#
"
W
where kn = n Cox
L.
From Ids,3 = Ids,1

kn3
1
(VDD VA Vtn )2 = kn1 (VDD Vtn )VA VA2 .
2
2
"
(5)
or in the form
(VDD Vtn )VA 21 VA2
(W/L)3
=
.
(VDD VA Vtn )2
(W/L)1
(6)
(17)
SRAM (contd)
Design of SRAM cells - Read Operation (contd)
To prevent the stored data from being destroyed, VA must not
exceed the threshold voltage of M2 , which is Vtn . In the limiting
case where VA = Vtn , we have
(W/L)3
2(VDD 1.5Vtn)Vtn
.
=
(W/L)1
(VDD 2Vtn)2
(7)
The symmetrical operation of the cell requires that

(W/L)4
2(VDD 1.5Vtn)Vtn
=
.
(W/L)2
(VDD 2Vtn)2
(8)
(18)
SRAM (contd)
Design of SRAM cells - Write Operation
Assume a 1 is stored in the cell (VA =Logic-1) and a 0 is to be
written in the cell.
Initially M1 is OFF. M2 is ON, M5 is ON and M6 is OFF. Bit line
is forced to Logic-0 by the write circuitry. Because VCBit = VDD and
M4 is ON, voltage at node B will increase slightly as CBit will
discharge slightly through M2 and M4. Also, VA will decrease.
To toggle the stored data, VA must be decreased from Logic-1 to the
level below the threshold voltage of M2 so that M2 will turn from
ON to OFF. Because Vd3 = 0, Vs3 = VDD , Vds,3 is large M3 is in
saturation.
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
Figure 15: MOSFET SRAM cell - write operation.
(19)
SRAM (contd)
M5 is in triode at the start of the write operation because
Vsd,3 = Vtn .
Ids,5
!2
1
W
= p Cox
)5(VDD 0 |Vtp |
2
L
(9)
(10)
Ids,3 =
W
p Cox
( )3
"
1
(VDD Vtn )Vtn Vtn2 .
2
#
(11)
(12)
Equating Ids,5 and Ids,3

(W/L)5
2n (VDD 1.5Vtn)Vtn
.
=
(W/L)3
(VDD |Vtp |)2
(13)
The same constraint applies to M4 and M6

(W/L)6
2n (VDD 1.5Vtn)Vtn
=
.
(W/L)4
(VDD |Vtp |)2
(14)
(20)
SRAM (contd)
SRAM - Write Circuitry
Force the voltage of the bit lines to either Logic-1 or Logic-0,
depending upon the data to be written into the cell. The transistor
controlled by the column decoder eliminates the static power
consumption when the bit is not selected.
Equalization transistor to ensure

that both bit lines are pre-charged
to the same voltage level
Word Line
C Bit
C Bit
Bit Line
WB
Bit Line
M1
M2
WB
Data
From Column
decoder
Figure 16: Write circuitry for SRAM.
Table 1: Write operation of SRAM.

W
0
0
0
Data
1
0
X
WB
1
0
0
WB
0
1
0
Remarks
M1=OFF, M2=ON, write 1
M1=ON, M2=OFF, write 0
M1=OFF, M2=OFF
(21)
SRAM (contd)
Sense Amplifiers
Introduction
The main function of sense amplifies is to amplify the small
differential voltage generated between the two bit lines during a
read operation. A sense amplifier is a differential input single-ended
output voltage amplifier.
Current-Mirror Sense Amplifier
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
CLK
Figure 17: Current-mirror sense amplifier.
The sense amplifier amplifies the differential voltage input and

converts it into a single-ended voltage output.
(22)
SRAM (contd)
Cross-Coupled nMOS Sense Amplifier
Cross-coupled nMOS pair form positive feedback to amplify the
differential input voltage. Note that because the voltage of the two
bit lines are nearly the same, the cross-coupled nMOS transistors
are all in saturation, ensuring a rapid transition.
Word Line
M5
Bit Line
M3 A
M1
C Bit
M6
Bit Line
B
M4
M2
C Bit
CLK
Figure 18: Cross-coupled nMOS sense amplifier.
(23)
SRAM (contd)
Complete SRAM
Word Line
C Bit
C Bit
Bit Line
Bit Line
CLK
CLK
W
WB
M1
M2
WB
Data
From Column
decoder
Figure 19: Complete SRAM.
(24)
DRAM
Four-Transistor DRAM Cell
Data are stored as the charge of the capacitances Cgs1 and Cgs2.
Due to the leakage of reverse biased pn-junctions, periodic
refreshing is required to retain the data. DRAM requires additional
peripheral circuitry for scheduling and performing the periodic data
refresh operation.
Too many transistors are needed and two bit lines a low degree
of integration
.
Word Line
Bit Line
Bit Line
C Bit
C Bit
Figure 20: 4-transistor DRAM cell.
(25)
DRAM (contd)
Three-Transistor DRAM Cell
First widely used DRAM cell.
Data are stored in Cgs2. M1 is the write access transistor, M2 is he
storage transistor, and M3 is the read access transistor.
Read Select
M1
M2
M3
C gs2
Write Select
C2
C1
Data In
Data Out
Figure 21: 3-transistor DRAM cell
Write operation - Assume 1 is to be written to the cell. Cbit is

charged to VDD . Write Select is asserted and M1 is ON Cgs2 is
charged by Cbit (note CbitCgs2).
Read operation - Assume 1 is stored in the cell and M2 is ON.
Cbit and Cbit are pre-charged to VDD . Read Select is asserted and M3
is ON Cbit is discharged via M2 Vdataout =Logic-0. The
charge of Cbit is not affected by the read operation.
In either READ or WRITE operations, the cell does not dissipate
static power. The cell can not be read and written at the same time.
(26)
DRAM (contd)
One-Transistor DRAM Cell
Data are stored in the explicit storage capacitor (30-100 pF). Only
one Read/Write Select line.
Read/Write Select
Explicit storage
capacitor
(30-100pF)
C1
C2
Bit line
Figure 22: 1-transistor DRAM cell
Write operation
Assume 1 is to be written to the cell. Bit line is set to Logic-1
(VDD ) by write circuitry. Read/Write Select is asserted by row
address decoder Storage transistor is ON and C1 is charged.
(27)
DRAM (contd)
Read operation
Bit line is pre-charged to an immediate voltage (VDD /2).
Read/Write Select is asserted. Storage transistor is ON the
charge stored in C1 and C2 is shared.
C1 Vc1 + C2Vc2 = (C1 + C2)Vc ,
(15)
where Vc1 and Vc2 are the voltages of C1 and C2 before the storage
transistor is ON, and Vc is the common voltage after the transistor
is ON. From which we arrive at
Vc =
C1
C2
Vc1 +
Vc2 .
C1 + C2
C1 + C2
(16)
Because Vc2 = VDD /2, the change of the voltage of the bit line
C1
C2 VDD
Vc1 +
C1 + C2
C1 + C2 2
C1
VDD
=
(Vc1
).
C1 + C2
2
Vbit = Vc Vc2 =
(17)
Because C1C2, we have Vbit100 mV (C1/C2 = 10 50).
(28)
DRAM (contd)
Example 1
If Vc1 = 0 (0 is stored in the cell), C1 = C2/10, and VDD = 3.3V
C1 VDD
= 150mV.
C1 + C2 2
(18)
C2 VDD
= 1.65V.
C1 + C2 2
(19)
Vc1 =
Vc =
Vc1 is charged from 0 to 1.65V.
Example 2
If Vc1 = VDD VT = 3.3 0.5 = 2.8V (1 is stored in the cell).
Vbit =
Vc =
C1 2.8 1.65
115mV.
C1 + C2
=
(20)
C2 VDD
C1
Vc1 +
= 1.93V.
C1 + C2
C1 + C2 2
(21)
Read operation is destructive. A write back operation is needed

each time the cell is read.
(29)
DRAM (contd)
DRAM - Read Circuitry
PC
DS
M1
R1
DS
MB
M128
R128
CD
C128=C
M256
R256
Y
C/2
C/2
C1=C
M129
R129
CD
PC
PC
C129=C
MR
ML
C256=C
CS
Reference cell
Reference cell
Figure 23: DRAM read circuitry
Consider a 256-cell per column DRAM. The sense amplifier is

placed in the center of the bit line. To create differential signal, two
reference cells are inserted. Each of the two bit lines has one
reference cell. CD and CD are the capacitances of the half of the bit
line. MB is used to ensure VCD = VCD during pre-charge (PC) phase.
If one of the 256 word R/W is set to Logic-1 by row address
decoder (For example, let R128 = 1). At the same time, the
reference on the other side is selected (DS = 1) the voltage of
the half bit line (Line D) will increase slightly due to charge
sharing between C128 and CD (VD = VDD /2, VC128 = VDD VT
before charge sharing). The voltage of the other half bit line
will decrease slightly due to charge sharing between CD
(Line D)
and CY (VY = 0, VD = VDD /2 before sharing).
Column select (CS)=1 sense amplifier is activated and
VD = VD VD is amplified. Because VD > VD , MR is ON and ML
is OFF VD = 1 and VD = 0 VC128 = 1.C128 is read and
refreshed simultaneously !
(30)
References
J. Rabaey, Digital Integrated Circuits - A Design Perspective,
Prentice-Hall, 1996.
S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design, 3rd ed., McGraw-Hill, 2003.
K. Martin, Digital Integrated Circuit Design, Oxford University
Press, 2000.
J. Kou and J. Lou, Low-Power CMOS VLSI Circuits, Prentice-Hall,
1999.
(31)

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ELE-863 VLSI Systems

Fei Yuan, Ph.D, P.Eng.

Copyright (c) F. Yuan 2009

Copyright (c) F. Yuan 2009

Figure 1: 2-dimensional Memory.

Used for memories of small size.

Copyright (c) F. Yuan 2009

MEMORY ARCHITECTURE (condd)

Global data bus

Figure 2: 2-dimensional Memory.

Used for memories of large size.

Copyright (c) F. Yuan 2009

Figure 3: ROM - Diode cells.

Without the diode, Bit line voltage is always LOW O is stored.

Copyright (c) F. Yuan 2009

Figure 4: ROM - BJT cells.

Fast response due to the large collector current of BJTs to charge

Copyright (c) F. Yuan 2009

Figure 5: ROM - MOS cells.

Copyright (c) F. Yuan 2009

Figure 6: 4x4 ROM.

Figure 7: Operation of ROM.

Copyright (c) F. Yuan 2009

Figure 8: Layout of 4x4 ROM.

Word lines are implemented using poly as their length is short.

Copyright (c) F. Yuan 2009

Figure 9: SRAM cells.

Copyright (c) F. Yuan 2009

Figure 10: Resistive SRAM cells.

Static power consumption exists.

Copyright (c) F. Yuan 2009

SRAM - Cell Configurations (contd)

Figure 11: MOSFET SRAM cell.

Lowest static power consumption (leakage current of pn-junctions

Copyright (c) F. Yuan 2009

SRAM Cells - Read Operation

Figure 12: MOSFET SRAM cell - read operation.

The two bit lines are pre-charged to logic-1 by pseudo-nMOS logic.

Copyright (c) F. Yuan 2009

SRAM Cells - Write Operation

Figure 13: MOSFET SRAM cell - write operation.

The bit lines are brought to Logic-1 or Logic-0 by the write

Copyright (c) F. Yuan 2009

Copyright (c) F. Yuan 2009

Figure 14: MOSFET SRAM cell - read operation.

Copyright (c) F. Yuan 2009

From Ids,3 = Ids,1

Copyright (c) F. Yuan 2009

The symmetrical operation of the cell requires that

Copyright (c) F. Yuan 2009

Figure 15: MOSFET SRAM cell - write operation.

Copyright (c) F. Yuan 2009

Equating Ids,5 and Ids,3

The same constraint applies to M4 and M6

Copyright (c) F. Yuan 2009

Equalization transistor to ensure

Figure 16: Write circuitry for SRAM.

Table 1: Write operation of SRAM.

Copyright (c) F. Yuan 2009

Current-Mirror Sense Amplifier

Figure 17: Current-mirror sense amplifier.

The sense amplifier amplifies the differential voltage input and