EC6201:BasicsofVLSI

Dr.RamaKomaragiri

CourseOrganizational
Instructor:Dr.RamaKomaragiri
Office:208,ECBlockI
Email:rama@nitc.ac.in
OfficeHours:walkin/onappointment
Venue:ELHC301

Schedule
DAY
MON
TUE
WED
THU
FRI

8.00
9.00
1

9.00
10.00
2

10.15
11.15
3

11.15
12.15
4

1.00
2.00
5

2.00
3.00
6

3.00
4.00
7

4.00
5.00
8

5.00
6.00
9

E+

A+

F+

G+

E@

C+

G@

H+

B+

D+

Only38lecturehoursareavailableoutof42hours.
ExtrahalfanouroneveryTuesdaystarting11th August2014
Asyourlabrunstill5:00PM,classstartsat5:15pmonMonandTue
4Creditcourse3T+1L,mean42lecturesand2hoursoflabeveryweek

LabSchedule
DAY
MON
TUE
WED
THU
FRI

8.00
9.00

9.00
10.00

10.15
11.15

11.15
12.15

12.15
1.15

2.00
3.00

3.00
4.00

4.00
5.00

5.00
6.00

EC61:Pslot
EC62:Tslot

PA

UA

PB

QA

QB

R
RA

RB

SA

SB

T
TA

TB

EducationalObjectives
1. Tointroducestudentstobasicconceptsofdigital
VLSIcircuitdesignusingsimplerVLSItechnology
2. Todeveloptheabilitytodesignbothcombinational
andsequentialdigitallogiccircuits
3. Tointroducevariousstagesindesignandsimulation
ofCMOSLogiccircuit,formparameterextractionto
layoutandparasiticextraction
4. Toarticulatetechnicalreport(throughlaboratory
component)

CourseOutcomes
Astudentwhosuccessfullyfulfillsthecourserequirementswillhave
demonstrated:
1. UnderstandandcalculatevariousparametersofaMOSFET
2. UnderstandeffectsofscalingtheoryofMOSFEToncircuit
performance
3. AnabilitytodesignTransistorLevelCMOSLogiccircuitfora
givenfunctionality
4. Anabilitytoestimateandcomputethepowerconsumptionofa
VLSIcircuit.
5. Anabilitytoestimateanddrawtimingcharacteristics
6. DesignaCMOSinverterforgiventimingand/ornoisemargins
7. LearntoAnalyzeGateFunctionandTimingCharacteristicsofa
multiinputCMOSLogicgates

CourseOutcomes
8. AnabilitytoanalyzeVLSIcircuittimingusingLogicalEffort
analysis.
9. Tounderstandandapplyvarioustechniquestoreducedelay
ofgate
10. AnabilitytodesignstaticCMOSanddynamicclockedCMOS
circuits.
11. DrawlayoutofaCMOScircuit
12. Anabilitytounderstandandexplaintheroleofparasitic
elementsinaCMOSdigital
13. Understandvariouslogicdesignstylesandcomparethem
withstaticCMOSlogicdesign
14. UnderstandingandanalyzeworkingofSRAMcellandDRAM
cell

CourseOutcomes
Astudentwhosuccessfullyfulfillsthecourserequirementswill
havedemonstrated:
ForLaboratorycomponent:
1. AnabilitytoextractMOSFETparametersthroughsimulations
2. AnabilitytodesignandsimulateofCMOScircuit
3. Understandeffectofprocesscircuitperformance
4. Prelayoutandpostlayoutsimulationsandparasiticextraction
5. DrawalayoutofaCMOScircuit,andanalyzethecircuittiming
usingasimulator
6. SimulatestaticCMOSanddynamicclockedCMOScircuits
7. Abilitytosummarizevariousfindings
8. Abilityarticulateatechnicalreport

EvaluationandGrading

Asthecoursehastheoryandlabcomponents,thetotalevaluationisfor80%
fortheoryand20%forlab.
TheoryEvaluation:
Assignment:15(takehome,quiz,project)
MidSemesterExamination:2mids for15and20marks
3Credits
EndSemesterExamination:50marks
Totalwillbescaleddownto80%
LabEvaluation:
Total9experimentseachwithaweightageof100marks
Projectwithaweightageof100marks(grouporindividual)
1 Credit
Totalwillbescaleddownto20%

EvaluationandGrading
GradingPolicy:
Passingminimumabsolute(min.40marks)
MinimumrequirementforSgradeis85.
Allothergradesarerelative
Note:
1)Allcommunicationregardingassignments,lecturenotesetc.willbe
electronic
2)Dependingupontheworkload,thetheoryassignmentmarks(eitherin
partialorinfull)canbeanextraproject.Thisisattheinstructorsdiscretion
andwillbeannouncedintheclass.

Syllabus

Test1Syllabus

Syllabus
Test2Syllabus

Syllabus

TextBooksandOtherResources
TextBooks:
1.SungMoKang&YusufLeblebici,CMOSDigitalIntegratedCircuits Analysis&
Design,MGH,ThirdEd.,2003.
2.JanMRabaey,DigitalIntegratedCircuits ADesignPerspective,PrenticeHall,2nd
Ed.,2005.
3.DavidA.Hodges,HoraceG.Jackson,andResve A.Saleh,AnalysisandDesignof
DigitalIntegratedCircuits,3rd Ed.,McGrawHill,2004
4.R.J.Baker,H.W.Li,andD.E.Boyce,CMOScircuitdesign,layout,andsimulation,
WileyIEEEPress,2007.
5.ChristopherSaintandJudySaint,IClayoutbasics:Apracticalguide,McGrawHill
Professional,2001.

TextBooksandOtherResources
FurtherReading:
Apartfromthestandardtextbooks,itissuggestedtogothroughthe(atleastone
ofthe)textbookstolearnfurther:
1)DigitalIntegratedCircuits:http://as.wiley.com/WileyCDA/WileyTitle/productCd
0471108057.html
2)CMOS:CircuitDesign,Layout,andSimulation,Revised,2ndEdition,
http://www.wiley.com/WileyCDA/WileyTitle/productCd0470881321.html
3)MOSFETModelsforSPICESimulation:IncludingBSIM3v3andBSIM4
http://as.wiley.com/WileyCDA/WileyTitle/productCd0471396974,subjectCd
EE60.html

ListofExperiments
ExperimentI:
1. SimulationofinputandoutputcharacteristicsofNMOSFETand
PMOSFETandParameterextraction
1.
2.
3.

Subthresholdslope,Thresholdvoltage,DIBL,gm,gd,Bodybiaseffect
Effectofdrainbiasonleakagecurrentandsubthresholdslope
(leavingtoyourlearningandefforts)

ExperimentII:
1. SimulatepMOSFETcharacteristics(inputandoutputfamilyof
characteristicsalongwithimportantFETparameters).
Constraint:Onecanuseonlypositivesupplyvoltages.
2. Todrawtheinputcharacteristicsandoutputcharacteristicsof
annMOSFETandpMOSFETinQ1andinonegraph.
TheaimoftheseexperimentsistogiveabasicunderstandingofvariousMOSFETandtheir
characteristics

ListofExperiments
ExperimentIII:

1. Simulationofaresistiveloadinverterandfindingthe
characteristics.
1.
2.
3.
4.
5.
6.
7.

VTC
Raisetime
Falltime
Power
Noisemargin
..
Whatiseffectofresistanceonraisetimeandnoisemargins

2. Replacetheresistiveloadwithapseudoloadordeviceanda
comparisonstudy
ExperimentIV

1. SimulationofasymmetricCMOSinverteranditscharacteristics
2. CorneranalysisofaCMOSinverter
3. EffectoftemperatureonperformanceofaCMOSinverterand
effectofcorners(considersamecornersasinexperimentIV)

ListofExperiments
ExperimentV:
1. SimulationofaasymmetricCMOSinverteranditscharacteristics
2. CorneranalysisofaCMOSinverter(samecornersasin
experimentIV)
ExperimentVI:
1. Designofaringoscillator/bufferanditscharacteristics
2. Applyinglogicalefforttothedesignin(1)andacomparison
betweenthedesigns
ExperimentVII:
1. Simulationofamultiinputgate(numberofinputsisgreaterthan
six)
2. Applicationoflogicalefforttoreducethedelay

ListofExperiments
ExperimentVIII:
1. Applicationofvarioustechniques(inputreordering,Euler'spath,
progressivesizing)toreducegatedelay
ExperimentIX:
1. LayoutofaCMOSinverterandcomparisonwithprelayoutand
postlayoutsimulations
ExperimentX:
1. Simulationofasequentialdigitallogiccircuitandcomparison
betweenprelayoutandpostlayoutsimulations
ExperimentXI:
1. Projectofyourchoice

Softwaretools
Cadence
Trainingarrangedonafternoonof7th and8th of
August2015

Report
Reportisduewithinoneweekaftercompletionofthe
experiment
Evenifsubsequentweekisaholidayforyourlab,report
needstobesubmittedwithinoneweek.
Exceptions:Experimentsdonebeforetest1andtest2week

Lengthofreport:limitedtofourpagesinclusiveofall
graphs,theory/reasons/explanationetc.
Evaluationoftheexperiment
50marksforyourdesigncalculationsandexperimentation
50marksforreport(inclusiveofqualityofthereport,
explanations,observations)

ReportSubmission
Reportmustcontainnamesofthegroupmembersand
rollnumbers
Namethereportinthefollowingformat(without
quotes):
EC6201_Expt.#_EC6X_ABCDEF
Here#:Experimentnumber
X:1 forEDT,2 forVLSI
ABC,DEF:arelastthreedigitsofyourrollnumbers(includeforall
teammembers)

Submityourreport(asasoftcopy)to
rama@nitc.ac.in,ranjith_p120097ec@nitc.ac.in,
kannan@nitc.ac.in
KeepallofyourteammembersinCCfieldofthemail
Makesurethatyourreportcanbeeditedbyus

Wherelecturematerialisuploaded
http://www.eduserver.nitc.ac.in/

Userid:guest
Pwd:EC6201ms_15