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EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

Experiment Date: 21 July 2015


Submitted Date: 04 July 2015
Name: GUNISETTY RAVI TEJA
M.Tech-VLSI DESIGN
15MVD0001

TITLE: STUDY OF CMOS INVERTER CHARACTERISTICS


OBJECTIVES:
1. To study the DC Characteristics of CMOS Inverter
2. To calculate the noise margin for the symmetric inverter
3. To measure the delay between the input and the output.
4. To compute Power consumption for the inverter

TOOL: Cadence virtuoso 6.1


CIRCUIT DIAGRAM & PROCEDURE:
Circuit - 1 for CMOS DC Response:

EXPERIMENT-2

i)

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

Calculation of width of PMOS transistor in Inverter circuit:


For Symmetric CMOS inverter the threshold point Vm should be at centre i.e. (0.75, 0.75).
We have
/Wn = K n/ K p
Kp is found out to be 118.34uA/V2
Kn is found out to be 286 uA/V2 from previous experiment.
From the above given expression we obtain the value of Wp to be 290nm.

For DC characteristics of CMOS inverter the parameters are


Selected NMOS transistor: - gpdk090_nmos1v
NMOS Width:-120nm

NMOS Length:-100nm

Selected PMOS transistor: - gpdk090_pmos1v


PMOS Width:-290nm

PMOS Length:-100nm

Circuit- 2 for CMOS Transient Response:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

For Transient characteristics the parameters are


Selected NMOS transistor: - gpdk090_nmos1v
NMOS Width:-120nm

NMOS Length:-100nm

Selected PMOS transistor: - gpdk090_pmos1v


PMOS Width:-290nm
PMOS Length:-100nm
For VPULSEVoltage1=0V
Voltage2=1.5V
Rise time = 2ps
Pulse width=10ns
Period=20ns
Delay time = 0ns; Fall time=2ps

Circuit-3 for CMOS Transient Response with 20fF load:

15MVD0001

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

i)
Go to Outputs save allenable all pubRun transient
ii)
Go to Browseropen resultspsf files click on power
The characteristics of the transistors remain same as the above but this circuit has an extra capacitive load

Circuit-4 for CMOS Transient Response with 50fF load:

EXPERIMENT-2

i)
ii)

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

Go to Outputs save allenable all pubRun transient


Go to Browseropen resultspsf files click on power

The characteristics of the transistors remain same as the above but this circuit has an extra capacitive load
of 50fF.

RESULTS:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

a) For CMOS DC response:

From the above graph we note that the threshold point for the given specification of the
transistor is 735.392mV
VOH : 1.5V
VOL :1mV

Parametric analysis for different widths of PMOS transistor:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

For PMOS widths of 270nm, 315nm, 350nm we have observed the shift in threshold voltage of
CMOS inverter.

For Noise Margin:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

The derivative of the Voltage transfer curve is taken and points where the gain is -1 is noted
down for VIH and VIL values.

VIH :944.882mV
VIL : 578.868mV
Noise margin = min(NMH , NML)
NMH = VOH VIH = 0.555118
NML = VIL VOL = 0.578868
Hence noise margin is 0.555118V

b) For CMOS transient analysis:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

The spikes obtained in the graph are as a result of the rise time delay in input and fall time delay in the
output. The delays can be seen in the below graph.

The delays observed from transient analysis of a CMOS inverter without any load capacitance
are:

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

tphl = 4.427 ps
tplh = 3.475ps
t PHL+ t PLH
tp =
2

= 3.951ps

The propogation delay is observed to be 3.951 ps


c) AVERAGE POWER CALCULATIONS:
Power calculation Graph for no load

The average power consumed by the cmos when no load is connected is 187.6 nW

Power calculation Graph for the capacitive load of 20fF

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

The average power consumed by the cmos inverter when 20pF load is connected is 2.479 uW.
Power calculation Graph for the capacitive load of 50fF

The average power consumed by the cmos inverter when 50pF load is connected is 5.911 uW.

CONCLUSION:
1. If the width of the PMOS is increased the transfer characteristics would shift towards right.
2. The threshold point obtained is 735.392mV for PMOS width of 290nm.

EXPERIMENT-2

STUDY OF CMOS INVERTER CHARACTERISTICS

15MVD0001

3. The propagation delay obtained is 3.951ps and we can observe that tplh< tphl.
4. The average power dissipated by a CMOS inverter increases as we increase the load capacitance.
5. Average power consumed by a CMOS inverter
a) Without load capacitance:187.6 nW
b) With 20fF load capacitance:
2.479 uW
c) With 50fF load capacitance:
5.911 uW

REFERENCES:
1. Design of analog CMOS integrated circuits- Behzad Razavi.
2. Digital integrated circuits(A design perspective)- Jan M. Rabaey