Organizaci
on del Computador I
El PIC 16F84A
Descripci
on
Harvard
20 MHz
1024 words
68 Bytes
64 Bytes
4
2 (A,B)
35
Encapsulado
SSOP
1
20
RA1
RA3
19
RA0
RA4/T0CKI
18
OSC1/CLKIN
MCLR
VSS
17
OSC2/CLKOUT
16
VDD
15
14
VDD
RB7
PIC16F84A
RA2
VSS
RB0/INT
RB1
13
RB6
RB2
12
RB5
RB3
10
11
RB4
Table 1-1 details the pinout of the device with descriptions and details for each pin.
13
Program Counter
FLASH
Program
Memory
8 Level Stack
(13-bit)
1K x 14
Program
Bus
14
RAM
File Registers
68 x 8
EEDATA
RAM Addr
EEPROM
Data Memory
64 x 8
EEADR
Addr Mux
Instruction Register
Direct Addr
TMR0
Indirect
Addr
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
Timer
I/O Ports
Instruction
Decode &
Control
Oscillator
Start-up Timer
Power-on
Reset
RA3:RA0
Timing
Generation
Watchdog
Timer
RB7:RB1
ALU
W reg
RB0/INT
OSC2/CLKOUT
OSC1/CLKIN
MCLR
VDD, VSS
Organizacion de la memoria
PIC16F84A
Memoria de Programa
FIGURE 2-1:
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
RESET Vector
0000h
0004h
User Memory
Space
Y ORGANIZATION
Memory Organization
1FFFh
PIC16F84Ade Datos
Memoria
2.2
2.2.1
FIGURE 2-2:
File Address
File Address
00h
Indirect addr.(1)
Indirect addr.(1)
80h
01h
TMR0
OPTION_REG
81h
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
07h
87h
08h
EEDATA
EECON1
88h
09h
EEADR
EECON2(1)
89h
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
8Ch
0Ch
68
General
Purpose
Registers
(SRAM)
Mapped
(accesses)
in Bank 0
4Fh
50h
CFh
D0h
7Fh
FFh
Bank 0
Bank 1
Seleccion de Bancos
Registro: W
Registro: STATUS
REGISTER 2-1:
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
DC
bit 7
bit 0
bit 7-6
Unimplemented: Maintain as 0
bit 5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
Legend:
DS35007B-page 8
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Puertos de Entrada/Salida
Los PICs tienen la caracterstica de que sus pines pueden ser todos
configurados de acuerdo a la necesidad de la aplicacion, es decir,
que los pines de un mismo puerto pueden ser usados como
entradas o como salidas.
Los PIC 16F84A cuentan con tres puertos de E/S.
Puerto A: Puerto bidireccional de 5 bits.
Puerto B: Puerto bidireccional de 8 bits.
Registros TRIS
PIC16F84A
Set de instrucciones
TABLE 7-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1 (2)
1
1 (2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
k
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
Configuracion Inicial
config CP OFF & XT OSC & WDT OFF & PWRTE OFF
OSC: Controla el modo de oscilaci
on que usara el PIC para
funcionar.
WDT: (Watchdog Timer) Es una capacidad del
microcontrolador de autorresetearse
PWRTE: Permite generar un retardo en la inicializacion del
PIC.
CP: Proteccion de c
odigo. Permite que el mismo no pueda ser
ledo por otra persona.
Declaracion de constantes
Declaracion de variables
Interrupciones
Registro: INTCON
2.3.3
INTCON REGISTER
Note:
REGISTER 2-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
2.3.2
OPTION REGISTER
Note:
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
6.9
Salvando
los registros
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
The code in Example 6-1 stores and restores the
STATUS and W registers values. The user defined
registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS
registers values.
EXAMPLE 6-1:
PUSH
ISR
POP
6.10
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
W_TEMP
STATUS,
W
STATUS_TEMP
MOVWF
STATUS
SWAPF
SWAPF
W_TEMP,
W_TEMP,
STATUS_TEMP,W
F
W
;
;
;
:
;
;
;
;
;
;
;
;
;
6.10.1
WDT PERIOD
MPLab
Descarga: www.microchip.com
MPLab
Ejemplo
Ejemplo