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Analog VLSI Circuit Design
Dr.Harikrishnan
Department of Electrical Engineering
e-mail: hrkhari@um.edu.my

MOS Large Signal Characteristic

Figure 1(b)

Figure 1(a)

The current, iD is generally given by :

1 2
W
i D = n C x ( v GS VT ) v DS v DS

2
L

(1)

In the realm of circuit design, it is more desirable to express the model equations in terms of
electrical rather than physical parameters. For this reason the drain current is often expressed
as :

i D = ( v GS VT ) v DS v DS
2

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(2)

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MOS Large Signal Characteristic (contd)

where the transconductance parameter is given in terms of physical parameters as :

= C ox

W
(A V2 )
L

There are various regions of operation of the MOS transistor based on the model of (2).
These regions of operation depend on the value of vGS-VT. If vGS-VT is zero or negative, then
the MOS device is in the cutoff region and (2) becomes :

i D = 0,

v GS VT 0

(3)

In this region, the channel acts like an open circuit.

Figure 2
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MOS Large Signal Characteristic (contd)

A plot of (2) with = 0 as a function of vDS is illustrated in Figure 2 for various values of vGS VT.
At the maximum of these curves the MOS transistor is said to saturate. The value of vDS at
which this occurs is called the saturation voltage and is given by :

v DS(sat ) = v GS VT

Thus, VDS(sat) defines the boundary between the remaining two regions of operation . If vDS is
less than vDS(sat), then the MOS transistor is in the nonsaturated region and (2) becomes :

i D = ( v GS VT ) v DS v DS ,
2

0 < v DS ( v GS VT )

The third region occurs when vDS is greater than vDS(sat) or vGS VT. At this point current iD
becomes independent of vDS. Therefore, vDS in (2) is replaced by vDS(sat) to get :

iD =

2
( v GS VT ) ,
2

0 < ( v GS VT ) v DS

equation above indicates that drain current remains constant once vDS is greater than vGS VT.
In reality this is not true as drain voltage increases, the channel length is reduced resulting in
increased current. This phenomenon is called channel length modulation.
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MOS Large Signal Characteristic (contd)

When channel length modulation is accounted for, iD is given by :

iD =

2
( v GS VT ) (1 + v DS ) ,
2

0 < ( v GS VT ) v DS

The output characteristic of the MOS transistor developed for the various region of operation is
normalized and given by :

Figure 3

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MOS Transistor Body Effect

In default it is always assumed the bulk and source are grounded, so that vB = vS = 0 held.
Often circuit consideration make this convenient arrangement impossible and vS vB must
be used.

Obviously the voltage vS vB must be such that the source-bulk junction is reverse biased
; otherwise a large current will flow inside the transistor. This current may damage the
device and in any case will impede its proper operation.

Thus in say in an nMOS transistor, the bulk must be biased to make it negative with
respect to both source and drain. The depletion region around the channel will become
wider if the reverse voltage between the bulk and the source is increased.

Since the voltage vG = VT is the gate voltage necessary to maintain the depletion region,
VT will increase in magnitude. The dependence of VT on the voltage vSB = vS vB can be
shown as :

VT = VT 0 +

2 P + v SB 2 P

(3a)

Here, VT0 is the threshold voltage for vSB = 0 and is a device constant given by :

=
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2 SqN imp
C x
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(3b)
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MOS Transistor Body Effect (contd)

In (3), S is the permittivity of silicon : S= 0KS, KS 11.7. Also, Nimp is the density of the impurity
ions in the bulk. For nMOS, Nimp = NA, the acceptor ion density; for pMOS, Nim= ND, the donor
ion density. Finally, P is a material constant of the bulk; value is around 0.3 V

Small Signal Representation

Figure 4(a)

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Small Signal Representation (contd)

Figure 4(b)
where :

i D
gm =
v GS
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g ds =

i D
v DS

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g mb =

i D
v SB
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Small Signal Representation (contd)

Here, gd is the incremental drain conductance, while gm and gmb are transconductance which
can be represented by voltage controlled current sources (VCCS). The values of gm, gmb and gd
can be found from iD and (3a) :
Assuming : k =

i D = k v GS VT 0 2 P + v SB + 2 P
gm =

) (1 + v
2

DS

i D
= 2k v GS VT0 2 P + v SB + 2 P (1 + v DS )
v GS

= 2 k (1 + v DS ) i D

g mb =
=

(4)

i D

= k v GS VT0 2 P + v SB + 2 P (1 + v DS )
vSB
2 P + v SB
g m 2
2 P + vSB

(5)

i D
gd =
= k v GS VT0 2 P + v SB + 2 P
v DS

=
iD
1 + v DS

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)
2

(6)
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Small Signal Representation (contd)

A good approximation , gm and gmb are proportional to

i D , while gd is proportional to iD.

MOS Branching Capacitance

The other important component of the complete small-signal model of the MOS are the
capacitors representing the incremental variations of stored charges with changing
electrode voltages. These play an important role in the high-frequency operation of
the device.

The intrinsic components of the terminal capacitances of the MOS devices (associated
with reverse-biased pn junctions, channel and depletion regions) are strongly dependent
on the region of operation, while the extrinsic components (due to layout parasitics,
overlapping regions, etc.) are relatively constant.

Assuming again that the transistor operates in the saturation region, it can be assumed
that the channel begins at the source and extends over two-thirds of the distance to the
drain. In this region of operation, the most important capacitance are the following :
Cgd

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Gate-to-Drain Capacitance. This is due to the overlap of the gate and the drain
diffusion. It is a thin-oxide capacitance and hence to a good approximation it can be
regarded as being voltage independent.

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Small Signal Representation (contd)

Gate-to-Source Capacitance. This capacitance has two components, Cgsov, the

gate-to-source thin oxide overlap capacitance and Cgs, the gate to channel
capacitance. The latter (in saturation region) is 2C x 3 where Cox is the total thin
oxide capacitance between the gate and the surface of the substrate. Cgs is nearly
voltage independent in the saturation region.

Csb

Source-to-Substrate Capacitance. This capacitance also has two components :

Csbpn, the pn junction capacitance between the source diffusion and the substrate,
and Csb, which can be estimated as two-thirds of the capacitance of the depletion
region under the channel. The overall capacitance Csb has a voltage dependence
which is similar to that of an abrupt pn junction.

Cdb

Drain-to-Substrate Capacitance. This is a pn junction capacitance and is thus

voltage dependent.

Cgb

Gate-to-Substrate Capacitance. This capacitance is usually small in the saturation

region; its value is around 0.1Cox

Cgs

Figure 5 illustrates the physical structure of an nMOS transistor and the locations of the
capacitances in the cutoff (Figure 5(a)), saturation (Figure 5(b)) and triode (Figure 5(c))
regions.

Table I lists the terminal capacitors of the nMOS device and their estimated values in the
three regions of operation. The notations used are those shown in Figure 5(a)-(c).

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nMOS Parasitic Capacitances

Figure 5(a)

Figure 5(c)

Figure 5(b)
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MOS Terminal Capacitances

Table I. Terminal Capacitances of a MOS in Three Main Regions
Capacitance

C gs
C gd
C gb
C sb
C db

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Cutoff

Saturation

Triode Region

WL ov C ox

WC ox L ov + L '
3

1
WC ox L ov + WL 'C ox
2

WL ov C ox

WL ov C ox

1
WC ox L ov + WL 'C ox
2

WL ov C ox

1
WL 'C ox C pn ( Vdb )
3
C ox + C pn ( Vcb )

A SC pn ( Vsb ) A SC pn ( Vsb ) + 2 WL 'C pn ( Vsb ) A SC pn ( Vsb ) + 1 WL 'C pn ( Vsb )

3
2
1
A d C pn ( Vdb )
A SC pn ( Vsb ) + WL 'C pn ( Vsb )
A d C pn ( Vdb )
2

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High Frequency Equivalent Circuit

Figure 6
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MOS Small Signal Construction

From the models of Figure 4(a) and Figure 6, a number of general statements can be made
about the desirable construction of a MOS :
a. For high ac gain, gm should be large. This will be the case, by (4), if k (nCoxW)/2L is
large. Thus the oxide should be thin to maximize Cox (which is the oxide capacitance per
unit area); also, W/L should be as large as possible. These measures, however, tend to
increase the size and thus the cost of the integrated circuit. Also, by (4), the quiescent
(bias) current iD should be as large as the allowable dc power dissipation permits.
b. As the negative sign in (5) indicates, the body effect reduces the gain. To minimize gmb, (5)
and (3b), we need large Cox, small Nimp (lightly doped substrate) and a large bias voltage
vSB for the source.
c. Ideally the MOS transistor in saturation should behave as a pure current source. Hence as
Figure 4(a) illustrates, rds should be large. By (6), this requires a small bias curent iD, a
large bias voltage vDS and a small . Since is introduced by channel length modulation, it
can be reduced by increasing L and also by increasing Nimp.

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MOS As Circuit Elements

Example 1
Calculate the incremental impedance
7(b).

v i seen at node A of the circuits shown in Figure 7(a) and

Figure 7(a)

Figure 7(b)

Example 2
Show that the transconductance gm in the saturation region is equal to the DC drain conductance in
the triode region (Assume : Vds<<Vgs-VT) for a given device and a fixed VG.

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MOS As Circuit Elements (contd)

Example 3
Using the definition

R = 1 ( i D v D ) , calculate the channel resistance of an nMOS transistor from :

a. i D = n C x

W
( v G VT ) v D
L

b. i D = n C x

W
vD
v

G
T

L
2

c. i D = k ( v G VT ) (1 + v D )
2

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vD

v G VT

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