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ConceptofSequentialLogic
LatchandFlipflops(FFs)
ShiftRegistersandApplication
Counters(Types,Application&
Design)
SequentialCircuitsDesign
(Statediagram,StateTable,KMap,
Circuit)

SequentialLogic/Circuits

SequencialvsCombinational
Outputofanycombinationallogiccircuitdepends
directlyontheinput
Generally,inasequentiallogiccircuit,theoutputis
dependentnotonlyontheinputbutalsoonthe
storedstate
Latchisusedforthetemporarystorageofadatabit
FFformthebasisformosttypesofsequentiallogic,
suchasregistersandcounters.
Also,twotypesoftimingcircuits(oneshotand555
timer)

Flipflop&Register

Latches
Edgetriggeredflipflops
Masterslaveflipflops
Flipflopoperatingcharacteristics
Flipflopapplications
Oneshots
The555timer

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Introduction
LatchesandFFsarethebasicsinglebitmemory
elementsusedtobuildsequentialcircuitwith
oneortwoinputs/outputs,designedusing
individuallogicgatesandfeedbackloops.
Latches:
Theoutputofalatchdependsonitscurrentinputsandon
itspreviousoutputanditschangeofstatecanhappenat
anytimewhenitsinputschange.

FFs:
Theoutputofaflipflopalsodependsoncurrentinputs
anditspreviousoutputbutthechangeofstateoccursat
specific times determined by a clock input

Latches

Introduction
Latches:
SRLatch
GateSRLatch
GateDLatch

FFs:
EdgeTriggeredFlipFlop(SR,JK,D)
AsynchronousInputs
MasterSlaveFlipFlop
FlipFlopOperatingCharacteristics
FlipFlopApplications
Oneshots&The555Timer

SR(SETRESET)Latch

Typeoftemporarystoragedevicethathastwostable
(bistable)states
Similartoflipfloptheoutputsareconnectedback
tooppositeinputs
Maindifferencefromflipflopisthemethodusedfor
changingtheirstate
SRlatch,Gated/EnabledSRlatchandGatedDlatch
Active-HIGH input S-R Latch

Active-LOW input S-R Latch

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LogicsymbolsfortheSRandSRlatch

NegativeORequivalentoftheNAND
gateSRlatch

TruthtableforanactiveLOWinput
SRlatch

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GatedSRLatch

AssumethatQisinitiallyLOW

AgateinputisaddedtotheSRlatchtomake
thelatchsynchronous.
Inorderforthesetandresetinputstochange
thelatch,thegateinputmustbeactive
(high/Enable).
1

Whenthegateinputislow,thelatchremainsin
theholdcondition.

Waveforms

AGatedSRlatch

GatedSRlatchwaveform:

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TruthTableforGatedSRLatch
S

Hold

Hold

Hold

hold

hold

set

reset

not allowed

GatedSRLatchQoutputwaveformiftheinputsareas
shown:

GatedDLatch(74LS75)

TheD(data)latchhasasingleinputthatisusedtoset
andtoresettheflipflop.
Whenthegateishigh,theQoutputwillfollowtheD
input.
Whenthegateislow,theQoutputwillhold.

GatedDLatch(74LS75)

Theoutputfollowstheinputwhenthegateishigh
butisinaholdwhenthegateislow.

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EdgetriggeredFlipflopLogic

ClockSignals&SynchronousSequentialCircuits

PositiveedgetriggeredandNegativeedgetriggered

Clock signal
0

Rising edges of
the clock
(Positive-edge
triggered)

Alltheaboveflipflopshavethetriggeringinputcalled
clock(CLK/C)

OperationofapositiveedgetriggeredSRflipflop

Falling edges
of the clock
(Negative-edge
triggered)

Clock Cycle
Time

Aclocksignalisaperiodicsquarewavethatindefinitely
switchesvaluesfrom0to1and1to0atfixed
intervals.

Example:

(d)S=1,R=1
isinvalidornot
allowed

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ApositiveedgetriggeredDflipflopformedwithanSRflipflop
andaninverter.

CLK/C

Q_________________

SET (stores a 1)

RESET (stores a 0)

TruthTableforJKFlipFlop

CLK

Q0

Q0

Hold

Reset

Set

Q0

Q0

Toggle (opposite state)

Example:

Transitionsillustratingthetoggleoperation
whenJ=1andK=1.

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EdgetriggeredJKflipflop
TheedgetriggeredJKwillonlyaccepttheJandinputs
duringtheactiveedgeoftheclock.

Asimplifiedlogicdiagramforapositiveedge
triggeredJKflipflop.

Thesmalltriangleontheclockinputindicatesthatthe
deviceisedgetriggered.
Abubbleontheclockinputindicatesthatthedevice
respondstothenegativeedge.nobubblewouldindicate
apositiveedgetriggereddevice.

Example:Positiveedgetriggered

Example:Negativeedgetriggered

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LogicsymbolforaJKflipflopwithactive
LOWpresetandclearinputs.

Edgetriggeredflipfloplogicsymbols(contd)
TheJKflipflophasatogglemodeofoperationwhenbothJand
KinputsareHIGH.TogglemeansthattheQoutputwillchange
statesoneachactiveclockedge.

Example:

BasiclogicdiagramforamasterslaveJK
flipflop.

J,KandCpareallsynchronousinputs.
Themasterslaveflipflopisconstructedwithtwolatches.
ThemasterlatchisloadedwiththeconditionoftheJKinputs
whiletheclockishigh.Whentheclockgoeslow,theslavetakeson
thestateofthemasterandthemasterislatched.
Themasterslaveisaleveltriggereddevice.
ThemasterslavecaninterpretunwantedsignalsontheJK
inputs.

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Pulsetriggered(masterslave)JKflip
floplogicsymbols.

FlipFlopApplications

TruthTableforMasterSlaveJKFlipFlop
J

CLK Q

Q0

Q0

Hold

Reset

Set

Q0

Q0

Toggle (opposite state)

Flipflopsusedinabasicregisterfor
paralleldatastorage.

ParallelDataStorage
FrequencyDivision
Counting

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JKflipflopasadivideby2device.Qisonehalfthe
frequencyofCLK.

Flipflopsusedtogenerateabinarycountsequence.Two
repetitions(00,01,10,11)areshown.

TwoJKflipflopsusedtodividetheclockfrequencyby4.QAisone
halfandQBisonefourththefrequencyofCLK.

FlipFlopOperatingCharacteristics
PropagationDelayTimes
SetupTime
HoldTime
MaximumClockFrequency
PulseWidth
PowerDissipation

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Thereareseveralotherparametersthatwillalsobelistedina
manufacturersdatasheet.
Maximumfrequency(Fmax)Themaximum
frequencyallowedattheclockinput.
Clockpulsewidth(LOW)[tW(L)]Theminimum
widththatisallowedattheclockinputduringthe
LOWlevel.
Clockpulsewidth(HIGH)[tW(H)]Theminimum
widththatisallowedattheclockinputduringthe
highlevel.

Comparisonofoperatingparametersfor4IC
familiesofflipflopofthesametype

Basicoperationofa555Timer

SetorResetpulsewidth(LOW)[tw(L)]The
minimumwidthoftheLOWpulseatthesetorreset
inputs.

FunctionalDiagramof555Timer

Threshold
ControlVoltage
Trigger
Discharge
Reset
Output

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555Timerasaoneshot

tw=1.1R1C1=1.1(2000)(1F)=2.2ms

Astableoperationof555Timer

tH=.7(R1+R2)C1=2.1mstL=.7R2C1=0.7ms

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