CSN221:COMPUTERARCHITECTURE

ANDMICROPROCESSORS
Computer Organization, CPU Structure and Functions

(Lecture - 5)

Dr.Sudip Roy
CourseWebsite:http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html
PiazzaSite:https://piazza.com/iitr.ac.in/fall2015/csn221

Datapath andControl:
Instruction
e.g.,ADDA,B,C
Operator/Control
Operand/Data

Datapath:
Memory,registers,adders,ALU,andcommunicationbuses
Eachstep(fetch,decode,execute,saveresult)requirescommunication(data
transfer)pathsbetweenmemory,registersandALU
Control:
Datapath foreachstepissetupbycontrolsignalsthatsetupdataflow
directionsoncommunicationbusesandselectALUandmemoryfunctions
Controlsignalsaregeneratedbyacontrolunitconsistingofoneormore
finitestatemachines
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Arithmetic&LogicUnit(ALU):
Doesallthecalculationsfortheprocessor
Everythingelseinthecomputeristheretoservicethisunit
Handlesintegers
Mayhandlefloatingpoint(real)numbers
MaybeseparateFPU(mathcoprocessor)
MaybeonchipseparateFPU(486DX+)
ALUInputs&Outputs:

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Whatdoesaprocessorwork?

Instructioncycle:
1. Fetchinstructions
2. Interpret(decode)instructions
3. Fetchdata
4. Process(Execute)data
5. Writedata
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Oncethecomputerhasbeenstarted
(bootstrapped)itcontinuallyexecutes
instructions(untilthecomputeris
stopped)
Differentinstructionstakedifferent
amountsoftimetoexecute(typically)
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ProgramCounter(PC):
Sometimescalledasinstructionpointer(IP)orinstructionaddressregister
(IAR)orinstructioncounter(IC)
Inmostprocessors,thePCisincrementedafterfetchinganinstruction,and
holdsthememoryaddressof(pointsto)thenextinstructionthatwouldbe
executed
Inaprocessorwherethisincrementprecedesthefetch,thePCpointstothe
currentinstructionbeingexecuted

Dr.SudipRoy

Example:InstructionExecution
MULT x,y,product
1. FetchtheinstructioncodefromMemory[PC]
2. Decodetheinstruction.Thisrevealsthatit'samultiplyinstruction,andthat
theoperandsarememorylocationsx,y,andproduct.
3. Fetchxandyfrommemory.
4. Multiplyxandy,storingtheresultinaCPUregister.
5. SavetheresultfromtheCPUtomemorylocationproduct.

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InstructionCycle:
Start

Acompleteinstructionconsistsof
operationcode
addressingmode

Fetch
Instruction

zeroormoreoperands
immediatelyavailabledata
(embeddedwithintheinstruction)
theaddresswherethedatacanbe
foundinmainmemory

Decode
Instruction

Fetch
Operand

Execute
Instruction

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InstructionSetArchitecture(ISA):
Softwaredesign

Hardwarecircuits

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InstructionSetArchitecture:SoftwareDesign
EachcomputerCPUmustbedesignedtoaccommodateandunderstand
instructionsaccordingtospecificformats.
Examples:
Allinstructionsmusthaveanoperationcodespecified
NOP

nooperation

TSTST

testandset

OpCode

Mostinstructionswillrequireone,ormore,operands
Thesemaybe(immediate)datatobeuseddirectly
or,addressesofmemorylocationswheredatawillbefound(including
theaddressofyetanotherlocation)
OpCode
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Operand(Address)
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InstructionSetArchitecture:SoftwareDesign
Sometimestheinstructionformatrequiresacode,calledtheMode,
thatspecifiesaparticularaddressingformattobedistinguishedfrom
otherpossibleformats
directaddressing
indirectaddressing
indexedaddressing
relativeaddressing
doublyindirectaddressing
etc.

OpCode

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Mode

Op.(Addr.)

Mode

Op.(Addr.)

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InstructionSetArchitecture:HardwareCircuits
Everythingthatthecomputercandoistheresultofdesigningandbuilding
devicestocarryouteachfunction nomagic!
Atthemostelementarylevelthedevicesarecalledlogicgates.
Therearemanypossiblegatetypes,eachperformaspecificBoolean
operation(e.g.AND,OR,NOT,NAND,NOR,XOR,XNOR)
ALLcircuits,henceallfunctions,aredefinedintermsofthebasicgates
WeapplyBooleanAlgebraandBooleanCalculusinordertodesigncircuits
andthenoptimizeourdesigns

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InstructionSetArchitecture:HardwareCircuits
Dataisrepresentedbyvarioustypesofsignals,includingelectrical,
magnetic,opticalandsoon.

Datamovesthroughthecomputeralongwiresthatformthevariousbus
networks(address,data,control)andwhichinterconnectthegates.
Combinationsofgatesarecalledintegratedcircuits(IC).

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InstructionSetArchitecture:CU(ControlUnit)
Thecontrolunitmustdecodeinstructions,setupforcommunicationwith
RAMaddressesandmanagethedatastoredinregisterandaccumulator
storages.
Eachsuch(CU)operationrequiresseparatecircuitrytoperformthe
specializedtasks.
Itisalsonecessaryforcomputerexpertstohaveknowledgeofthevarious
datarepresentationstobeusedonthemachineinordertodesign
componentsthathavethedesiredbehaviors.

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InstructionSetArchitecture:ALU
Allinstructionstogetherarecalledtheinstructionset
CISC complexinstructionsetcomputer
RISC reducedinstructionsetcomputer
EachALUinstructionrequiresaseparatecircuit,althoughsomeinstructions
mayincorporatethecircuitlogicofotherinstructions

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RISCvs.CISC:
MostcommonmicroprocessordesignssuchastheIntel80x86andMotorola
68KseriesfollowedtheCISCphilosophy.

Butrecentchangesinsoftwareandhardwaretechnologyhaveforcedare
examinationofCISCandmanymodernCISCprocessorsarehybrids,
implementingmanyRISCprinciples.

ThefirstRISCprojectscamefromIBM,Stanford,andUCBerkeleyinthelate
70sandearly80s.TheIBM801,StanfordMIPS,andBerkeleyRISC1and2
werealldesignedwithasimilarphilosophywhichhasbecomeknownasRISC.

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RISCvs.CISC:
CertaindesignfeatureshavebeencharacteristicofmostRISCprocessors:
onecycleexecutiontime:RISCprocessorshaveaCPI(clockperinstruction)of
onecycle.ThisisduetotheoptimizationofeachinstructionontheCPUanda
techniquecalledPIPELINING
pipelining:atechniquethatallowsforsimultaneousexecutionofparts,or
stages,ofinstructionstomoreefficientlyprocessinstructions;
largenumberofregisters:theRISCdesignphilosophygenerallyincorporatesa
largernumberofregisterstopreventinlargeamountsofinteractionswith
memory
CISCwasdevelopedtomakecompilerdevelopmentsimpler.Itshiftsmostofthe
burdenofgeneratingmachineinstructionstotheprocessor.Forexample,
insteadofhavingtomakeacompilerwritelongmachineinstructionsto
calculateasquareroot,aCISCprocessorwouldhaveabuiltinabilitytodothis.
E.g.PentiumisconsideredamodernCISCprocessor
Dr.SudipRoy

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RISCvs.CISC:
MostcommonmicroprocessordesignssuchastheIntel80x86andMotorola
68KseriesfollowedtheCISCphilosophy.
Butrecentchangesinsoftwareandhardwaretechnologyhaveforcedare
examinationofCISCandmanymodernCISCprocessorsarehybrids,
implementingmanyRISCprinciples.
CISC

RISC

Complex instructionsrequiremultiple
cycles

Reducedinstructionstake1cycle

Many instructionscanreferencememory

OnlyLoadandStoreinstructionscan
referencememory

Instructionsareexecuted oneatatime

Usespipeliningtoexecute instructions

Fewgeneral registers

Manygeneralregisters

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RISCvs.CISC:
CISC
EffectivelyrealizesoneparticularHighLevelLanguageComputerSystem
inHW recurringHWdevelopmentcostswhenchangeneeded
RISC
AllowseffectiverealizationofanyHighLevelLanguageComputerSystem
inSW recurringSWdevelopmentcostswhenchangeneeded
Hybridsolutions
RISCcore&CISCinterface
Stillhasspecificperformancetuning
OptimalISA
BetweenRISC&CISC
Few,carefullychosen,usefulcomplexinstructions
Stillhascomplexityhandlingproblems
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MemoryHierarchyinaComputer:

DuetosizeofDRAM
Duetocostandwiredelays(wiresonchipcostmuchless,andarefaster)

KeytoyourArchitecturalDesign:

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