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Centre for Neural Engineering, The University of Melbourne, 203 Bouverie Street, Carlton, Victoria 3053,
Australia
2
Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville, Victoria 3010,
Australia
(Received 27 March 2014; accepted 27 June 2014; published online 11 July 2014)
Graphene holds great promise for replacing conventional Si material in field effect transistors
(FETs) due to its high carrier mobility. Previously proposed graphene FETs either suffer from low
ON-state current resulting from constrained channel width or require complex fabrication processes
for edge-defecting or doping. Here, we propose an alternative graphene FET structure created on
intrinsic metallic armchair-edged graphene nanoribbons with uniform width, where the channel
region is made semiconducting by drilling a pore in the interior, and the two ends of the nanoribbon
act naturally as connecting electrodes. The proposed GNP-FETs have high ON-state currents due
to seamless atomic interface between the channel and electrodes and are able to be created with
arbitrarily wide ribbons. In addition, the performance of GNP-FETs can be tuned by varying pore
size and ribbon width. As a result, their performance and fabrication process are more predictable
and controllable in comparison to schemes based on edge-defects and doping. Using first-principle
transport calculations, we show that GNP-FETs can achieve competitive leakage current of
70 pA, subthreshold swing of 60 mV/decade, and significantly improved On/Off current ratios
C 2014 AIP Publishing LLC.
on the order of 105 as compared with other forms of graphene FETs. V
[http://dx.doi.org/10.1063/1.4889755]
I. INTRODUCTION
0021-8979/2014/116(2)/023709/4/$30.00
semiconducting armchair-edged GRs as channel and zigzagedged GRs as electrodes with angled-ribbons between,
resulting in a Z-shaped nanoribbon junction structure.12,13
This structure requires extremely narrow GRs to open a gap
wide enough for good switch-off and, therefore, suffers from restricted ON-state current. Other schemes of graphene FETs
introduce carefully designed edge defects or doping into zigzagedged GRs to create semiconducting channels. 11,14,15 These
designs bring in additional complexity into the fabrication process and uncertainty in the performance of resulting FETs.
Here, we propose an alternative graphene FET structure
that is created on intrinsic metallic armchair-edged GRs with
uniform width, where the channel region is made semiconducting by drilling a pore in the interior, and the two ends of
the nanoribbon act naturally as connecting electrodes. The
proposed GNP-FETs will be shown to have remarkable ONstate currents due to seamless atomic interface between the
channel and electrodes and the option of being created with
arbitrarily wide ribbons. In addition, the performance of
GNP-FETs can be tuned by varying pore size and ribbon
width. As a result, their performance and fabrication process
are more predictable and controllable than that of schemes
based on edge-defects and doping.
II. THE PROPOSED GNP-FETs
116, 023709-1
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FIG. 1. Geometry of the proposed GNP structure for FETs prior to passivation. M and Mp are numbers of hexatomic rings in length of the ribbon and
pore, respectively. N and Np are numbers of atoms in width of the ribbon
and pore, respectively. Shown in this figure are M 10 and N 17 (corresponding to a ribbon of length L 4.1 nm and width W 2.0 nm), and
Mp 4 and Np 7 (corresponding to a pore of length Lp 1.6 nm and
width Wp 0.7 nm).
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FIG. 4. Current vs. gate voltage of the GNP-FETs with different pore
lengths under a bias voltage of Vbias 20 mV. GNP parameters are M 14
(i.e., ribbon length L 5.8 nm), N 17 (i.e., ribbon width W 2.0 nm),
Np 7 (i.e., pore width Wp 0.7 nm), and Mp 3, 4, and 5 (i.e., pore
length Lp 1.1 nm, 1.6 nm and 2.0 nm), respectively.
FIG. 6. Current vs. gate voltage curves of the GNP-FETs with different ribbon widths under a bias voltage of Vbias 20 mV, where the pore size
(Lp 1.6 nm, Wp 0.7 nm) and ribbon length (L 5.8 nm) are kept constant. N 17, 29 and 41 corresponds to ribbon widths W 2.0 nm, 3.4 nm,
and 4.9 nm, respectively.
seamless atomic interface between the channel and electrodes in GNP-FETs. These results also indicate that increasing
the pore length leads to slight reduction of leakage current
and increase in ION/IOFF ratio. Fig. 5 plots the currents vs.
bias voltage curves under different gate voltages (Vg) for the
case Mp 4, where good Ohmic behaviour is observed for
relatively large gate voltages (0.30.5 V) and small bias
(<0.2 V).
We now study the situations when the same pore is created in increasingly wider ribbons. This is done by keeping
the pore size and ribbon length constant and setting N to 17,
29, and 41, respectively (corresponding to ribbon widths
2.0 nm, 3.4 nm, and 4.9 nm, respectively). Supplementary information Figs. S2, S4-S5 (Ref. 21) show the geometries of
these GNPs, and Fig. 6 shows the resulting current vs. gate
voltage curves. We see that increasing the ribbon width
raises ON-state current and, more significantly, OFF-current,
leading to performance degradation. The extracted SS and
ION/IOFF ratios for the three ribbon widths are [66.8 68.9
74.2] mV/decade and [1.701 0.056 0.013] 104, respectively. This effect can be understood by viewing the transmission spectrum of these GNPs, shown in the
supplementary information Fig. S6.21 There it can be seen
that bandgap decreases when ribbon width is increased. In
other words, the effectiveness of bandgap-opening of the
pore is reduced for wider ribbons.
Next, we demonstrate how the performance of wideribbon GNP-FETs can be improved by enlarging the pore. In
particular, we increase the pore width of the 4.9 nm wide
GNP-FET. Fig. 7 shows the current vs. gate voltage curves
for Np values 7, 19, and 31 (corresponding to pore widths
0.7 nm, 2.2 nm, and 3.7 nm). Supplementary information
Figs. S5, S7-S8 (Ref. 21) show the geometries of these
GNPs. It can be seen that enlarging the pore significantly
reduces the OFF-state current, leading to improved performance. The extracted SS and ION/IOFF ratios for the three pore
FIG. 5. Current vs. bias voltage curves of the GNP-FET with M 14 (i.e.,
ribbon length L 5.8 nm), N 17 (i.e., ribbon width W 2.0 nm), Mp 4
(i.e., pore length Lp 1.6 nm), and Np 7 (i.e., pore width Wp 0.7 nm).
FIG. 7. Current vs. gate voltage curves of the GNP-FETs with varying pore
width under a bias voltage of Vbias 20 mV, where the ribbon size
(L 5.8 nm, W 4.9 nm) and pore length (Lp 1.6 nm) are kept constant.
Np 7, 19 and 31 corresponds to pore widths Wp 0.7 nm, 2.2 nm, and
3.7 nm, respectively.
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023709-4
widths are [74.2 65.5 63.2] mV/decade and [0.013 0.21 18.6]
104, respectively. The transmission spectrum of these
GNPs, shown in the supplementary information Fig. S9,21
reveals that larger pores are more effective in bandgapopening. As can be seen from these results, as long as the
pore is adequately large, good OFF-state current and SS performances are achieved. In addition, the ION/IOFF ratio can
be made increasingly large by simultaneously widening the
ribbon and pore, which is a unique feature of GNP-FETs.
Finally, we evaluate the effects of graphene edge
defects. Three GNPs with vacancy defects are considered
where GNP_D1 has one broken pore-edge, GNP_D2 has two
broken pore-edges, and GNP_D3 has a circular pore.
Supplementary information Figs. S10-S1321 depict the geometries of these GNPs and their transmission spectra. There
it can be seen that all the three irregular pores are able to
open the bandgap. The defect-induced performance changes
can be observed in Fig. 8, where the current vs. gate voltage
curves of the corresponding GNP-FETs are shown. It can be
seen that, as compared to its perfect edge counterpart,
GNP_D1-FET has a deterioration of 15 mV/decade in SS
and an order of magnitude drop in ION/IOFF ratio due to
increased leakage current. While GNP_D2-FET and
GNP_D3-FET exhibit reasonably good SS and Ion/Ioff
ratios, the curves are no longer symmetric in respect to the
current minimum and there are low-slope regions where the
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