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# IEC

Fall 2015

Assignment #1
Topics: Differential Pairs, Active Loads, Small Signal Analysis
Due Date: Sept. 30, 2015
Problem 1: (Section 7.1) For the differential amplifier specified in problem
7.1 of Sedra and Smith, assume G2 has been grounded (0 V) and vG1 has
been adjusted to yield iD1 = 0.11 mA and iD2 = 0.09 mA.
(a) What are the corresponding values of vGS1, vGS2, vS , and vid? [vGS1 =
0.97 V, vGS2 = 0.94 V, vS = -0.94 V, vid = 0.03 V ]
(b) What is the differential voltage gain (vD2 vD1/vid)? [3.33 ]
Problem 2: (Section 7.1) Sedra and Smith: Chapter 7, problem 7.8. [VGS =
0.99 V, gm = 1.06 mA/V, vid = 0.27 V, Ibias = 800 A]
Problem 3: (Section 7.2) We would like to design an NMOS differential
amplifier that operates with a differential input voltage as high as vid =
0.2 V. To keep the gain characteristics reasonably linear, we need the
value under the square root in Equation (7.23) of Sedra and Smith to be
no smaller than 0.9. Finally, assume that nCox = 100 A/V2 and a gm of
3 mA/V is required.
(a) What overdrive voltage (VOV ) is required for the transistors? [0.316 V ]
(b) What current (I) should the pair be biased with? [0.95 mA]
(c) What W/L ratio should the transistors be sized with? [95 ]
(d) What differential gain results for RD = 5 k, neglecting channel length
modulation? [15 ]
(e) What is the differential output voltage corresponding to the maximum
differential input voltage? [3 V ]
Problem 4: (Section 7.2) Consider the differential pair shown in Fig. 7.4 of
Sedra and Smith, where vid is a small signal sine wave. The pair is biased
with I = 300
A, and nCox = 100 A/V2. A design error has resulted in a sizing mismatch
between the transistors, with (W/L)1 = 10 and (W/L)2 = 20. You may neglect
channel length modulation.
(a) What are the steady state bias currents for each transistor, ID1 and ID2?
[ID1 = 100 A, ID2 = 200 A]
(b) What is VOV for the two transistors? [0.447 V ]
(c) What is the differential gain (Ad) assuming RD = 5 k? [6.71 ]

## Problem 5: (Section 7.2) Sedra and Smith: Chapter 7, problem

7.15. (a) Answer: [|Ad| = 3.85, |Acm| = 0.05, CMRR = 37.7 dB
]
(b) Answer: [|Ad| = 7.7, |Acm| = 0.0005, CMRR = 83.7 dB ]
Problem 6: (Section 7.4) An NMOS differential pair operating at a bias current
I = 100 A uses transistors with n = 100 A/V2, W/L = 20, and Vt = 0.8 V.
kt
(a) How much input offset voltage is introduced if RD/RD = 5%? [5.57 mV ]
(b) How much input offset voltage is introduced if (W/L)/(W/L) =
5%? [5.57 mV ]
(c) How much input offset voltage is introduced if Vt = 5 mV? [5 mV ]
(d) What is the worst case input offset voltage if all three effects are present?
[16.14 mV ]
Problem 7: (Section 6.5) Consider the common source amplifier of Fig. 6.18(a)
2
in the text, where ktn =
p = 250 A/V , |Vt| = 0.6 V, and |VA| = 10 V.
2.5kt
(a) What is the required IREF to obtain an output resistance of 100 k? [0.05
mA]
(b) Find (W/L)1 to obtain a gain of -40 V/V with IREF as specified above.
[6.4 ]
(c) If Q2 and Q3 must have the same overdrive voltages as Q1, find their W/L
ratios. [16 ]
Problem 8:
[gm1 gm2 r2 /4]

## Problem 9: (Section 6.5) Consider the amplifier in Fig. 1. The power

supply voltage is VDD = 5 V; for NMOS devices nCox = 100 A/V2, for
PMOS devices pCox = 50 A/V2, |Vt| = 1 V for all devices, and the sizing
of the transistors is as follows: (W/L)1 = 8m/2m, (W/L)2 = 4m/2m,
and (W/L)3
= 4m/2m. You may ignore channel length modulation for M2 and M3, but
you must consider it for M1 with VA t = 15 V/m.
(a) What is the small signal input resistance, rin? [1620
(b) What is the small signal output resistance, rout? [1480

]
]

(c) What is the small signal voltage gain, vout/vsig ? [-1.24 V/V