'Silicon thin-film formation by direct photochemical

decomposition of dlsilane', Jpn. J . Appl. P h v s , 1983, 22, pp.

L4CL48
HALL, I T., and PETERS. J. w.: 'Photo-CVD for VLSI isolation'. J .
Efectrochem.Sue. 1984,9, pp. 214&2151
TARUI, Y., and HIUAKA,
1.: 'Low-temperature growth of silicon
dioxide film by photo-chemical vapor depositlon', J p n . J . A p p l
Phys., 1984, 23. pp. L827-LXZY
W!MASAWA,
Y., Y A M A Z K I . K., and HAMANO. K : 'Photo-CVD system
for silicon nitride film', J. Electron. M a t e r , 1986. IS, (I), pp. 27-30
UKARE: 'Photochemistry of small molecules', (John Wiley & Sons,
New York, 1 9 7 0 pp. 143

MISHIMA, Y . .

When the parenthesised clocks are used, this circuit performs

inverting amplification or attenuation, to produce the output
voltage

The addition and the subtraction are also possible by charging C i and C , to different signals in the
= 'I' phase. In any

0
I
T-r

CLOCK- FEEDTH ROUG H COMPENSATED

SWITCHED-CAPACITOR CIRCUITS
Indexing terms: Circuit deszgn, Circult theory and design,
Switched cuparitor circuits

Novel switched-capacitorcircuits are presented which greatly

suppress the clock-feedthrough effect. The principle is based
on the cancellation of feedthrough charges stored in two
capacitors. The circuit i s also insensitive to parasitic capacitances and offset voltages of the opamps, and thus allows
accurate analogue signal processing. Experimental waveforms are also given to demonstrate its validity.
Now that the parasitic-insensitive, gain- and offsetcompensated stages have solved the problems associated with
the CMOS ~ p a m p , ' -the
~ charge injection accompanying a
switch is the most serious error source that degrades the
signal-to-noise ratio in switched-capacitor circuits. The higher
the operating frequency and finer linewidth, the more serious
the degradation. A common way to reduce the charge injection is to connect a dummy switch in series with a main
This method is effective in cancelling the charge due
to the overlap capacitances between the gate and source/
drain, but not for the signal dependent charge stored in the
channel of a main switch. The signal-independent cancellation
can be realised by a fully differential configuration,' but it
requires additional components and opamps with balanced
outputs.
Recently, a simple method has been proposed to reduce the
clock-feedthrough effect in a sample/hold circuit.' This principle of cancelling the feedthrough charges is applied successfully to switched-capacitor circuits.
Fig. l a shows the clock-feedthrough compensated switchedcapacitor amplifier. This circuit is basically the same as the
multiply-by-2 stage used for the pipeline A/D convertor,' but
the switching sequence is modified as shown in Fig. Ib. These
clock signals are easily generated by simple logic gates
because 4, and 4, are delayed replicas of 4i and 4 is the
nonoverlapping complement of 4,. In Fig. la, capacitor C , is
incorporated to alleviate the slew rate requlrement. In the
$, = @, = 43 = ' I ' phase, capacitors C , and C , are charged
to the input voltage V,". Switch M i is then first turned off. The
clock-feedthrough charge from M i is then injected to capacitor C,. Switch M, is then turned off to inject the feedthrough charge into C , . The feedthrough charges stored in C ,
and C , are opposite in polarity, but equal in magnitude if M
and M, consist of matched transistors and are turned off
Finally, Switch M, is turned o f . The feedthrough
charge from M, is then injected only to capacitor C, which is
incorporated for spike-free operation," because the inverting
input terminal of the opamp is floating at this instant. In the
subsequent @ = ' I ' phase, the charge stored in C, is transferred to C , , to produce the output voltage

$3

Fl-J7--f
b

iP'

Fig. 1 Clock-feedthrough compen.sat~dswitched-capacitor amplifier and

timing diagram ofclock vgnuls
a

Amplifier

b Timing diagram

case, the offset voltage due to clock feedthrough does not

appear at the output because the feedthrough charges stored
in C , and C, cancel each other. Neither parasitic capacitances
nor the offset voltage of an opamp have an effect on the
operation.
Fig. 2 shows the clock-feedthrough compensated sample/
hold circuit. All the capacitors can assume any value providing that the holding capacitor C, is much larger than C , and
C,. Driven by the clock signals shown in Fig. Ib, the circuit
produces the exact replica of the input signal in the 4 = ' I '
phase.
T o confirm the principles of clock-feedthrough compensation, the noninverting amplifier shown in Fig. l a was
built using an LF356 opamp and MC14016 analogue
switches. Two 30pF capacitors were used for C, and C,. T o
identify the offset level of the output voltage, capacitor C, was
0

C?

M.
,P3

it

+a

C-

1
II

5~8' 2

Fig. 2 Clock-/redthrough < o m p e n s u ~ e dS ' H circuit

ELECTRONICS LETTERS 24th October 1991 Vol. 2 7

N o . 22

2045

short-circuited and the switch M , was disconnected. Experimentally observed waveforms when the circuit was driven by
the sinusoidal source with the peak amplitude of IOOmV are
shown in Fig. 3. The middle trace shows the output waveform

WECMANN, G., VITTOZ,

E. A., and RAHALI, F.: Charge injection in
analog MOS switches, IEEE J. Solid-Stare Circuits, 1987, SC-22,
pp. 1091-1097
12 MATSUMOTO, H., and WATANABE,
K.: Spike-free switched-capacitor
circuits, Electron. Lett., 1987,8, pp. 428429

11

SQUARE PULSE AMPLIFICATION USING

NONLINEAR LOOP M I R R O R
INCO R PO RAT1N G SATURABLE GAIN
Indexing term5: Optical communications, Amplifiers, Nonlinear
ODtlCS
____~

A nonlinear fibre loop mirror is described that comprises an

8.8 km length of dispersion shifted fibre and an erbium doped
Fig. 3 Experimentally observed output waveforms of amplifer shown in
Fig. In with and without clock-jeedthrough compensation

Bottom trace with compensation

Middle trace: without compensation
Horizontal scale: 0.1 msldivision
Vertical scale: IO V/division (top trace) and 200 mVidivision
(middle and bottom traces)
when the conventional two-phase clocks were used. The offset
voltage about 200mV can be seen generated by the clockfeedthrough charge. The bottom trace shows the output waveform when the switching sequence shown in Fig. l b was used.
It can be seen that the offset voltage is reduced to a negligibly
small level, independent of the signal amplitude.
The device requirement for the clock-feedthrough compensation is minimal. Therefore, the compensation technique
and switched-capacitor circuits described here appear to be
practical for accurate analogue signal processing in D/A and
A/D convertors. They are also applicable to filters because
inverting and noninverting integrators can be formed by the
adderpbtractor and the sample/hold circuit.
S . OGAWA
K. WATANABE
Research Institute of Electronics
Shizuoka University
Hamamatsu 432, Japan

13th August 1991

References
I
2
3
4
5

7
8
9

IO

VISWANATHAN,
I. R., and SINGHAL,
K.:
Switched-capacitorintegrator with reduced sensitivity to amplifier
gain, Electron. Lett., 1986, 22, pp. 1103-1 105
HAUG, K., MALOBERTI,F., and rem G . c.: Switched-capacitorcircuits with low op-amp gain sensitivity. Proc. Int. Symp. on Circuits and Systems, 1986, pp. 797-800
LARSON, L. E., and TEMFS, G . c.: Switched-capacitorgain stage with
reduced sensitivity to finite amplifier gain and offsetvoltage, Electron. Lett., 1986, 22, pp. 1281-1283
NAGARAJ,
K., VISWANAMAN,
T. R., SINGHAL,
K., and VLACH, J.:
Switched-capacitor circuits with reduced sensitivity to amplifier
gain, IEEE Trans., 1987, CAS34, pp. 571-574
SUAREZ,
R., GRAY, P. R., and HODGES,0. A.: ALL-MOS charge
redistribution analog-to-digital conversion techniques-Part I,
IEEE J. Solid-State Circuits, 1975, SC-IO, pp. 379-385
EICHENBERGER, C., and GUGGENBUHL, w.: Dummy transistor compensation of analog MOS switches, IEEE J. Solid-State Circuits,
1989, SC-24, pp. 1143-1146
LI, P. W., CHIN, M. J., GRAY,P. R., and CASTELLO,
R.: A ratioindependent algorithmic analog-to-digital conversion technique,
IEEE J . Solid-State Circuits, 1984, SC-19, pp. 828-836
WATANABE, K., and OGAWA, S.: Clock-feedthrough compensated
samplelhold circuits, Electron. Lett., 1988.24, pp. 12261227
VALENCIC, V., ANGHINOLFI, F., DEVAL, P., KRUMMENACHER, F.,
P., HEIJNE,
E. H. M.,and UECLERCQ,
M.: 1-M sample/sec
JARRON,
12-bit low-power pipelined AID converter. Proc. int. symp. on
circuits and systems, 1990, pp. 1360-1363
SHIEH, I.-H., PATIL, M., and SHEU, B. 1 . : Measurement and analysis of
charge injection in MOS analog switches, IEEE J Solid-State
Circuits, 1987, SC-22, pp. 277-281
NAGARAJ, K., VLACH, J.,

2046

fibre amplifier. The low calculated switching powers

(-milliwatts peak) afforded by the high gain (-20dB) and
long loop length have been confirmed by measurements of
the square pulse response. An experimental and theoretical
study of the effect of gain saturation on the device characteristics has also been conducted

In recent work, we studied the shaping of picosecondduration optical pulses by the intensity-dependent transmission characteristics of a nonlinear fibre loop mirror. We
demonstrated both experimentally and theoretically the
advantages to be gained from this pulse shaping, in particular
pulse compression and pedestal suppression. In this Letter we
report preliminary results involving a nonlinear loop mirror
incorporating an erbium-doped fibre amplifier (EDFA) as the
symmetry breaking element. The device is a simple extension
of the nonlinear optical loop mirror described by Doran and
Wood and bas been investigated experimentally by Fermann
et al.3 for an Nd3+-doped fibre amplifier and low repetition
rate (10Hz) pulse trains to avoid saturation of the amplifier
gain. It is a particularly attractive configuration for telecommunications applications because it combines both intensity
filtering and amplification functions. By employing the high
gains typically obtained from laser diode-pumped EDFAs and
long fibre loops, the switching powers can be reduced to the
power levels of mode-locked semiconductor lasers .(, 1mW
peak). At gigahertz repetition frequencies, however, the corresponding average powers (- 1CQpW) are sufficient to give rise
to significant gain saturation in the amplifier. In this work, we
have investigated in detail the effects of gain saturation on the
transmission characteristics of the device.
A schematic diagram of the fibre configuration is shown in
Fig. 1. The loop was constructed from a 30m long diodepumped EDFA and a length L = 8.8km of Corning dispersion shifted fibre. The dispersion zero of this fibre was around
1.55pm and was chosen to ensure that pulse shaping due to
loop, 1

Fig. 1 Loop mirror configuration

ELECTRONICS LETTERS 24th October 1991

Vol 2 7 No. 22

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