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Decoupled Space-Vector PWM Strategies for a

Four-Level Asymmetrical Open-End Winding
Induction Motor Drive With Waveform Symmetries
Barry Venugopal Reddy, Student Member, IEEE, Veeramraju Timurala Somasekhar, and Yenduri Kalyan

AbstractIn this paper, two space-vector-based pulsewidth

modulation (PWM) (SVPWM) strategies named equal- and
proportional-duty SVPWMs are described, which are used to synthesize a four-level waveform from an open-end winding configuration of an induction motor. Two isolated dc-link voltages,
which are in the ratio of 2 : 1, are employed to achieve this
objective. Both of these PWM strategies achieve the avoidance
of overcharging of the dc-link capacitor of an inverter operating
with lower dc-link voltage by its counterpart with higher dc-link
voltage. Implementation of these PWM strategies requires only
the instantaneous three-phase reference voltages, eliminating the
need of sector identification or lookup tables. The numbers of
samples per cycle for individual inverters are selected in such a
way that the quarter-wave, half-wave, and three-phase symmetries
are achieved for the dual-inverter drive despite unequal dc-link
voltages for the constituent inverters. It is also shown that one of
the two PWM techniques, called the proportional-duty SVPWM,
results in a better spectral performance and lower switching power
loss in the overall dual-inverter system compared to the equal-duty
SVPWM.
Index TermsFour-level inverter, open-end winding induction
motor, space-vector modulation, unequal dc-link voltages, waveform symmetries.

I. I NTRODUCTION

HE principles of pulsewidth modulation (PWM)

schemes for multilevel inverters, principally the neutralpoint-clamped, flying-capacitor, and H-bridge topologies
[1][8], are extensively investigated and well documented.
These PWM schemes generally fit into two categories, namely,
carrier based [9][11] and space vector based [12][14].
Considerable research work has also been carried out
to understand the relationship between these two PWM
methodologies [15], [16].
In a path-breaking work, Stemmler and Guggenbach have
shown that three-level inversion could also be achieved by the

Manuscript received July 9, 2010; revised October 26, 2010 and January 6,
2011; accepted January 25, 2011. Date of publication February 17, 2011; date
of current version September 7, 2011.
B. Venugopal Reddy and V. T. Somasekhar are with the Department of Electrical Engineering, National Institute of Technology, Warangal 506004, India
(e-mail: bvenugopal_reddy@yahoo.co.in; vtsomsekhar@rediffmail.com).
Y. Kalyan was with the Department of Electrical Engineering, National Institute of Technology, Warangal 506004, India. He is now with the Indian Institute
of Technology, Kanpur 208016, India (e-mail: kalyan.yenduri@gmail.com).
Digital Object Identifier 10.1109/TIE.2011.2116759

open-end winding connection of an induction motor with two

two-level inverters feeding the motor from either end [17].
One of the advantages of open-end winding configuration is
that multilevel inversion is achieved using the conventional
two-level inverter as the basic building block [18][23]. Consequently, the switching algorithm proposed in [24] for the
implementation of space-vector modulation for a two-level
inverter can readily be extended for multilevel inverters with the
open-end winding configuration also. In the work reported in
[23], a method of obtaining four-level inversion with open-end
winding configuration has been described, which uses unequal
dc-link voltages. The disadvantage with this configuration is
that the dc-link capacitor of the inverter with lower voltage
could be overcharged by the one corresponding to the inverter
operating with higher dc-link voltage.
This limitation was overcome in the work reported in [23]
by identifying the space-vector combinations, which cause this
trouble and avoiding their deployment. In other words, the
PWM strategy used in this work views both the inverters as a
single entity and hence could be described as the coupled spacevector modulation. Consequently, this method calls for the use
of sector-identification and lookup tables for the deployment
of vector combinations, making this scheme cumbersome to
implement [23].
In this paper, two decoupled synchronous space-vector-based
PWM (SVPWM) switching strategies are described for the
four-level inverter configuration. The SVPWM technique suggested in [25] is extended to the four-level configuration. With
this PWM strategy, the dc-link capacitor of the inverter with
lower voltage is not overcharged by that of the one with higher
dc-link voltage. It is shown that this PWM strategy obviates the
need for sector identification. The implementation of this PWM
strategy requires only instantaneous phase reference voltages
and does not require any lookup tables.
The principles described in [26] and [27] which render the
quarter-wave symmetry (QWS), half-wave symmetry (HWS),
and three-phase symmetry (TPS) for a two-level voltage source
inverter (VSI) are extended in this paper to obtain these waveform symmetries for the output voltage waveform of the fourlevel inverter. The fact that the output voltage waveform is
obtained by the superposition of the output of one inverter
with the output of the other inverter is exploited in this
paper to judiciously choose the number of samples for the
individual inverters, which constitute the dual-inverter drive
system.

0278-0046/$26.00 2011 IEEE

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TABLE II
P OLE AND P HASE VOLTAGES OF THE F OUR -L EVEL I NVERTER

Fig. 1.

Fig. 2.

Four-level inverter drive with open-end winding topology.

Voltage vectors for (left) inverter-1 and (right) inverter-2.

TABLE I
S WITCHING S TATES OF THE I NDIVIDUAL I NVERTERS

A given pole voltage of inverter-1, for example, Ao , assumes

two values, which are Vdc /3 and Vdc /3. Similarly, the pole
voltage corresponding to the phase-A leg of inverter-2, denoted
as A o , assumes two values, which are Vdc /6 and Vdc /6.
As the pole voltage of each inverter is capable of assuming
two values independently of the other, the difference of pole
voltages assumes four values, as shown in Table II (assuming
that the points O and O are short circuited).
The sum of the motor-phase voltages AA , BB  , and CC 
do not add to zero, meaning that there exists a substantial zerosequence voltage. However, when the short circuit between
O and O is removed, a path is denied to the zero-sequence
currents as each inverter is operated with an isolated power
supply. Consequently, the zero-sequence voltage is dropped
across the points O and O .
III. R EQUIREMENTS OF WAVEFORM S YMMETRIES FOR
D UAL -I NVERTER -F ED O PEN -E ND W INDING
I NDUCTION M OTOR D RIVE

II. F OUR -L EVEL O PEN -E ND W INDING I NDUCTION

M OTOR C ONFIGURATION W ITH A SYMMETRICAL
DC-L INK VOLTAGES
Fig. 1 shows the power circuit configuration of a four-level
inverter realized by the dual-inverter-fed open-end winding
configuration of induction motor.
In this drive, the two constituent inverters are operated with
unequal dc-link voltages. Inverter-1 is operated with a dc-link
voltage of 2 Vdc /3, while inverter-2 is operated with a dc-link
voltage of Vdc /3. Thus, the sum of the two dc-link voltages
is equal to Vdc , which is the dc-link voltage of an equivalent
conventional two-level inverter drive.
The pole voltages of inverter-1 are represented by the symbols Ao , Bo , and Co , while the symbols A o , B  o , and
C  o represent the pole voltages of inverter-2. Fig. 2 shows the
space-vector locations from individual inverters.
The numbers 1 to 8 refer to the states assumed by inverter-1.
Similarly, the numbers 1 to 8 indicate the states assumed by
inverter-2. Table I reviews the states offered by both of these
inverters.

The output waveform of a high-power VSI is expected to

have HWS, QWS, and TPS to avoid even order harmonics and
unbalancing effects. Synchronized PWM techniques are used
to eliminate the undesirable effects at low switching frequency
associated with high-power inverters. The output waveform of
an inverter employing a synchronized PWM technique can have
odd, as well as even, harmonics. However, the even harmonics
can be avoided if the waveform possesses HWS.
While HWS ensures that only odd harmonics are present
in the output waveforms, the QWS ensures that the existing
harmonics have only one serieseither the sine or cosine
series. In other words, all the harmonic components would have
their zero-crossing instances synchronized with respect to the
zero crossings of the fundamental component. Furthermore, to
ensure that every harmonic component is balanced, the TPS
must be realized. It is shown in [26] that, while employing
SVPWM, it is necessary to ensure the following conditions to
ensure the QWS, HWS, and TPS.
1) The number of samples in a span of 60 must be odd.
2) Sampling must be avoided along the sector boundaries.
3) Sampling is mandatory along the lines, which divide
sectors into two equal halves.
In the work presented in this paper, these three rules are
complied to ensure the aforementioned waveform symmetries.
As mentioned earlier, two synchronous decoupled SVPWM
schemes are reported in this paper, which use volts-per-hertz
control for the open-end winding induction motor drive. In
the first SVPWM strategy, named equal-duty SVPWM strategy,

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Direction of charging currents for 12 combination.

Fig. 3. Direction of charging currents for 11 combination.

Fig. 4.

42 samples are used per revolution (i.e., seven samples in a span

of 60 ) in such a way that samples on sector boundaries are
avoided. This is accomplished by choosing the first sample at
an angle of 4.286 , i.e., {360 /(42 2)} and with an angular
quantization of 8.571 (360 /42), so that the last sample occurs
at an angle of 355.714 , i.e., (360 4.286 ). A similar criterion
is adopted to select the number of samples in the second PWM
strategy, named proportional-duty SVPWM strategy, which will
be explained later in detail.

that a similar situation prevails for the combinations 33 and

55 , wherein one of the motor-phase windings is connected
directly across the positive plates of the two dc-link capacitors
(Table I). For the combinations 22 , 44 , and 66 , two motorphase windings are connected between the positive plates of
the two dc-link capacitors. In either of these circuit situations, the capacitor of inverter-1 directly sees the capacitor of inverter-2. Consequently, the capacitor of inverter-2
is charged up by the capacitor of inverter-1, causing an imbalance of the capacitor voltages, which would no more be in
the ratio of 2 : 1, which is essential for the operation of the
four-level inverter. To maintain a constant dc voltage across
the dc-link capacitor of inverter-2, one requires a regenerative
front-end rectifier, which is capable of recovering the excessive
charge from it and returning the same to the supply mains,
which would be a considerably expensive proposition. Reliability would be another issue to be addressed, owing to the
increased component count.

IV. E FFECT OF I NVERTER -S TATE C OMBINATIONS ON

DC-L INK C APACITOR OF I NDIVIDUAL I NVERTERS
As stated earlier, each inverter is capable of assuming eight
states independently of the other. This means that a total of
64 space-vector combinations are derivable from the dualinverter drive. However, all of these combinations are not
useful. In fact, some of them are deleterious and should not
be deployed. In general, for every active vector of inverter-1
(the inverter with a dc-link voltage of 2 Vdc /3), there are three
active vectors in inverter-2 (the inverter with a dc-link voltage
of Vdc /3), which are deployable. These vectors are the ones
which subtend an obtuse angle with the active vector output
by inverter-1. On the other hand, the vectors which subtend an
acute angle with the active vector output by inverter-1 should be
refrained from deployment, as they charge the dc-link capacitor
of inverter-2 by the dc-link capacitor of inverter-1. For example,
when inverter-1 assumes a state of 1(+ ), inverter-2 should
be allowed to output only the vectors 3 ( + ), 4 ( + +),
and 5 ( +), while it should not be allowed to output the
vectors 1 (+ ), 2 (+ + ), and 6 (+ +) (Fig. 2). The
phenomenon of charging of the dc-link capacitor of inverter-2
by its counterpart of inverter-1 is graphically described in the
following paragraphs:

B. Combination 12
Fig. 4 shows the equivalent circuit for the vector combination
12 . In this case, inverter-1 outputs the vector 1(+ ) while
inverter-2 outputs the vector 2 (+ + ), which subtends an
angle of 60 with respect to the vector output by inverter-1
(Fig. 2). It may readily be observed that the dc-link capacitor of
inverter-1 sees its counterpart in this circuit situation too. However, with this combination, the dc-link capacitor of inverter-2
is partially discharged as one of the motor phases (phase B in
the present case) that partially drains the excess charge from
the capacitor. Thus, this combination is not as deleterious as
combination 11 . The vector combination 16 also results in a
similar circuit situation, wherein the motor phases B and C
reverse their roles.

A. Combination 11

C. Combination 14

When inverter-1 assumes the state 1(+ ) and inverter2 assumes the state 1 (+ ), the switches S6 , S1 , and
S2 are turned on for inverter-1, while the switches S6 , S1 ,
and S2 are turned on for inverter-2 (Table I). In this case,
the vectors output by the inverters are parallel (Fig. 2). By
inspection, one may arrive at the equivalent circuit shown in
Fig. 3, wherein phase A of the motor is directly connected
between the positive plates of the capacitors, while phases
B and C are both connected between the negative plates.
Thus, the currents through phases B and C serve as the
return paths for the current through phase A. It may be noted

With this vector combination, inverter-1 and inverter-2 are

switched with the states 1(+ ) and 4 ( + +), respectively.
In this case, the switching vector output by inverter-2 is in
antiphase with respect to the vector output by inverter-1 (Fig. 2).
It may be noted that the positive plate of the former is connected
to the negative plate of the latter through phase A, while phases
B and C connected to the positive plate of the capacitor
of inverter-2 constitute the return path (Fig. 5). Thus, a direct
showdown between the dc-link capacitors of inverter-1 and
inverter-2 is avoided with this switching vector combination. A
similar circuit situation prevails for the switching combinations

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TABLE III
D EPLOYABLE AND F ORBIDDEN S WITCHING S TATES OF I NVERTER -2
FOR THE S TATES OF I NVERTER -1

Fig. 5.

Direction of charging currents for 14 combination.

Fig. 6.

Direction of charging currents for 15 combination.

of 25 , 36 , 41 , 52 , and 63 , wherein the motor phases change
their roles compared to the one shown in Fig. 5.
D. Combination 15
Fig. 6 shows the equivalent circuit for the combination 15 ,
in which inverter-1 is switched with vector 1(+ ) and
inverter-2 with 5 ( +). It is evident that this combination
also prevents the overcharging of the dc-link capacitor of
inverter-2, as the positive plates of the dc-link capacitors of
the inverters are not connected through any of the motor-phase
windings, avoiding a direct confrontation of the capacitors. A
similar equivalent circuit results for the combination 13 , in
which phases B and C interchange.
It should also be noted that, when one of the inverters is
switched with a null state (for example, 17 ), a switched neutral
is created at one end, making one of the capacitors to float.
When both inverters are switched with a null state (for example,
77 ), both of the capacitors are made to float, avoiding the
passage of any current. As there is no current through the
capacitors, they are not allowed to undergo a change in charge.
In other words, all switching vector combinations with a null
vector (for both of the inverters) could be employed in this fourlevel inverter configuration. Table III summarizes the useful and
forbidden switching vectors of inverter-2 for each of the states
of inverter-1.
V. D ECOUPLED SVPWM S TRATEGY W ITH
E QUAL S WITCHING D UTY
The decoupled SVPWM strategy used in this paper is based
on the fact that a space vector Vsr can be constructed by
taking the difference between two individual space vectors,
which are antiphased to each other. Since the dc-link voltages
of individual inverters are in the ratio of 2 : 1, it stands to
reason that they should be made to output space vectors, whose
magnitudes are proportional to their respective dc-link voltages.
Thus, inverter-1 and inverter-2 are individually operated with

Fig. 7. Decoupled PWM strategy for a four-level inverter.

reference voltage vectors 2Vsr /3 and vsr /3, respectively.

Subtraction of the latter component from the former achieves
the desired reconstruction of the reference vector (Vsr ).
The basic principle of the decoupled SVPWM strategy is
shown in Fig. 7, wherein the vector OT represents the actual
reference voltage space vector, which is to be synthesized from
the dual-inverter system and is given by |Vsr |. This vector
is resolved into two opposite components OT1 (|2Vsr /3|)
and OT2 (|Vsr /3| + ). The vector OT1 is synthesized
by inverter-1 in the average sense by switching among the
states (8127) while the vector OT2 is reconstructed by
inverter-2 in the average sense by switching among the states
(8 5 4 7 ), when the tip of the reference vector OT is
situated in sector-1.
In the first variant of the decoupled SVPWM schemes
described in this paper, the reference voltage space vector
(OT, Fig. 7) is sampled for a fixed number of times (42) per
one revolution for both of the inverters, in compliance with
the conditions required to achieve the waveform symmetries,
as explained earlier in Section III. Moreover, both inverters
are switched in each sampling time period of the reference
voltage space vector (OT) or, in other words, with equal
switching duty.
The rated value of the frequency of both
inverters (50 Hz)
corresponds to the modulation index of ( 3/2), which is the

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limit of linear modulation. The modulation index with which

the dual-inverter drive is operated is defined as
ma = |Vsr |/Vdc .
Thus, the frequency of the fundamental component of both
inverters at a modulation index of ma is given by
ma
fo =   50
3/2

To =

1
.
fo

(1)

Consequently, the sampling time period (Ts ) of individual

inverters is given by
Ts1 = Ts2 = Ts =

To
.
42

(2)

The switching algorithm described in [24] for the implementation of center-spaced SVM for a two-level inverter feeding a
conventional induction motor is extended for the computation
of the switching timings for individual inverters of the dualinverter system. This algorithm reduces the computational burden as it avoids the sector identification and obviates lookup
tables corresponding to the terms sin and sin(/3 ),
associated with the conventional implementation of SVM. It
also avoids the Tan1 computation needed to evaluate the angle
subtended by the reference voltage space vector. This algorithm
is briefly explained in the following paragraphs.
The algorithm proposed by Chung et al. [24] is based on
the concept of imaginary switching time periods, denoted as
Txs . (x a, b, c), which are defined as




Ts
Ts

Tas
Tbs
a
b
Vdc
Vdc


Ts
Tcs
(3)
c .
Vdc
The symbols a , b , and c denote the instantaneous reference phase voltages corresponding to the actual reference space
vector sr . The phase switching times are defined as the time
period for which a given output phase of the two-level inverter
is connected to the positive rail of the input dc power supply in
a sampling time period Ts and are denoted as Tga , Tgb , and Tgc .
In the work presented in [24], it is shown that the time period
Te , during which there exists a power flow from the dc side to
the ac side of the inverter, is given by
Te = max(Tas , Tbs , Tcs ) min(Tas , Tbs , Tcs ).

(5)

The offset time period needed to center-space the effective

time period block within the sampling time interval Ts is
given by
Toset = T0 /2 Tmin
where Tmin is min(Tas , Tbs , Tcs ).

It is shown in [24] that the phase switching time Tgx (x

a, b, c) is related to Txs (x a, b, c) by a simple expression

(6)

(x a, b, c).

Tgx = Txs + Toset

(7)

For a dual-inverter system, there would be two sets of phase

switching times, one for each inverter. The phase switching
timings of inverter-1 are denoted by the symbols Tga , Tgb , and



Tgc (Fig. 8). Similarly, the symbols Tga
, Tgb
, and Tgc
denote the
phase switching timings for inverter-2 (Fig. 8). The symbols a ,
b , and c denote the instantaneous reference phase voltages
corresponding to the actual reference space vector Vsr of the
dual-inverter system. As individual inverters operate with the
references 2Vsr /3 and Vsr /3, respectively, it follows that
the corresponding phase references are also divided in the ratio
of 2 : 1. Thus, the instantaneous phase reference values for
inverter-1 are given by 2a /3, 2b /3, and 2c /3, and those
for inverter-2 are given by a /3, b /3, and c /3. These
references are then used to find out the phase switching timings
of each inverter using the switching algorithm described in [22].
The imaginary switching times [24] for inverter-1 and inverter-2
are given by
Txs = (3Ts /2Vdc ) (2x /3) ,

Txs

= (3Ts /Vdc ) (x /3) ,

(x a, b, c)

(8)

(x a, b, c).

(9)

If the reference vector for inverter-1 (OT1 , Fig. 7) is situated

in sector-1, then the effective time periods [24] for inverter-1
and inverter-2 are given by

(4)

The time duration for which a zero vector is deployed is then

given by
T0 = Ts Te .

Fig. 8. Typical gate switching time periods of inverter-1 and inverter-2 over a
sampling time period in a decoupled control (simulation result).

min
)
Te = (3Ts /2Vdc ).(2/3). (max

(10)


Te

(11)

= (3Ts /Vdc ).(1/3). (max

min
)

where

= max (a , b , c )
max

min
= min (a , b , c ) .

From (10) and (11), it is evident that



= (Ts /Vdc ). (max

min
).
Te = Te

(12)

As the sampling time period and effective time periods are

equal for both inverters, it follows that the null time periods
are also the same for both inverters. The inverter leg switching

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5135

Fig. 10. Difference in pole voltages of phase A (simulation result).

Fig. 9. Experimentally obtained phase-A pole voltage of inverter-1 and

inverter-2 for (a) (Top) ma = 0.4. (b) (Bottom) overmodulation. Scale:
X-axis: 10 ms/div. Y -axis: 50 V/div.

time periods for inverter-1 and inverter-2 are denoted by Tgx


and Tgx
(x a, b, c), respectively. They are given by

Tgx = (T0 /2) + (Ts /Vdc ) (max

min
)

(13)


Tgx
= T0 /2.

(14)

From (13) and (14), it follows that


Tgx
= Ts Tgx .

(15)

Thus, it is shown that the phase switching timings need not

be exclusively computed for inverter-2, reducing the computational burden on the signal processing platform. Fig. 8 shows
a clear visualization of the implementation of this SVPWM
scheme for one sampling time interval.
From Fig. 8, it is evident that both inverters are operated with
the same sequence so that the null vector combinations are 88
and 77 . The advantage with the proposed decoupled control is
that the inverter switching timings of both inverters need not
be computed. It may be noted that the effective time periods
for both inverters are center spaced in any given sampling time
interval Ts . The proposed PWM scheme for the four-level openend winding induction motor drive is validated with simulation
studies and experimental results.
Inverter-1 and inverter-2 are operated with respective dc-link
voltages of 200 and 100 V (which amounts to an effective
dc-link voltage of 300 V in an equivalent two-level drive). The
control platform dSPACE is employed to generate the control
signals for the individual inverters. Simulation and experimental results are also presented for overmodulation, wherein the
tip of the revised reference voltage vector is forced to trace the
hexagon ABCDEF (Fig. 7) if the tip of the original reference
vector (OT) falls outside the hexagon. In the interest of brevity,
the method to implement overmodulation is not explained here.
However, it is explained in detail in [25].
Fig. 9 shows the experimentally obtained pole voltages of
inverter-1 and inverter-2 for (top trace) ma = 0.4 and (bottom
trace) overmodulation. As points O and O are the dc-neutral
points of individual inverters (Fig. 1), the pole voltage of

Fig. 11. Simulated and experimentally obtained zero-sequence voltages for

ma = 0.4. Scale: X-axis: 5 ms/div. Y -axis: 50 V/div.

inverter-1 switches between 100 V, and that of inverter-2

switches between the levels 50 V, as shown in Fig. 9.
Fig. 10 shows the computed difference in pole voltages of
the two inverters. It may be noted that an experimental result
could not be shown, as the available oscilloscope does not have
isolated channels. The four levels enumerated in Table II are
clearly discernable (assuming that the points O and O are short
circuited).
As isolated dc power supplies are used to feed individual
inverters, the zero-sequence current is denied a path to flow
through, and the zero-sequence content of the difference in
pole voltages is dropped across the points O and O (Fig. 1).
Consequently, the actual voltage applied across a given motorphase winding is shown in Fig. 12, is equal to the difference of
the difference of pole voltages and the zero-sequence voltage,
and is given by
AA = (Ao A o ) zs

(16)

where
zs =

1
[(AO A O) + (BO B  O) + (CO C  O )] .
3

Fig. 11(a) shows the simulated waveform of the zerosequence voltage for ma = 0.4. Fig. 11(b) shows the experimentally obtained voltage across the points O and O (Fig. 1),
i.e., the zero-sequence voltage corresponding to this condition.
The congruence of the simulated and experimental results,
shown in Fig. 11, indirectly serves as an experimental verification of the waveform for the difference in pole voltages for
ma = 0.4 (presented in Fig. 10).
Fig. 12 shows the (top) simulated phase voltage and (bottom)
its harmonic spectrum, wherein the zero-sequence voltage (the
harmonic components corresponding to the triplen order) is

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Fig. 14. Motor-phase current in loaded condition for ma = 0.4 Scale:

X-axis:10 s/div; Y -axis: 2 A/div (for both traces).

Fig. 12. (Top) Simulated waveform of phase-A voltage and (bottom) harmonic spectra corresponding to ma = 0.4.

Fig. 13. (Left) Motor-phase voltage and (right) motor-phase current for
(a) ma = 0.4 and (b) ma = 1.2, i.e., overmodulation. Scale for voltage traces:
X-axis: (Top trace) 20 and (bottom) 10 ms/div; Y -axis: 100 V/div (for the
two traces). Scale for current traces: X-axis: (Top trace) 20 and (bottom trace)
10 ms/div; Y -axis: 1 A/div (for the two traces).

absent, which are dropped across points O and O (Figs. 1 and

12). Thus, the simulation studies validate the decoupled PWM
strategy with equal switching duty of the inverters.
The motor-phase voltages and the corresponding motorphase currents at no load for the modulation indices (ma )
of 0.4 and overmodulation are shown in Fig. 13(a) and (b),
respectively.
Fig. 14 shows the motor-phase current in loaded condition
for ma = 0.4 in steps of 2 A. Fig. 15 shows the dc-link
voltages of the inverters operating with voltages of 200 and
100 V, respectively, for a modulation index (ma ) of 0.4, for
the corresponding load currents in Fig. 14. It should be noted
that the traces shown in Figs. 14 and 15(a) and (b) are not
synchronized, as each trace was taken separately, owing to the
lack of isolated channels of the oscilloscope. From Fig. 14,

Fig. 15. DC-link voltages of inverter-1 and inverter-2 under loaded condition
for ma = 0.4. Voltage scale: X-axis: 10 s/div; Y -axis: 50 V/div (for both
traces).

it is evident that each loading results in a small drop in the

capacitor voltagethe usual regulation associated with any dc
power supply.
Fig. 15 shows the effectiveness of the decoupled PWM
scheme. It is evident that the dc-link capacitor of the inverter
operating with lower voltage is not overcharged by its counterpart with higher voltage, as explained in Section IV. It is experimentally verified that the dc-link voltages are not disturbed
and are maintained in the ratio of 2 : 1, even under the loaded
condition. However, in this PWM scheme, both inverters are to
be switched with the same switching frequency, despite being
operated with different dc-link voltages. Although effective,
it would increase the switching power losses in the inverter
operating with higher dc-link voltage. Thus, an attempt is made
to further improve this PWM scheme, which tends to switch the
inverters with a switching frequency that is proportional to the
dc-link voltage. This PWM scheme is explained in detail in
the next section.
To demonstrate the effectiveness of the choice of the number
of samples per sector, which influences the waveform symmetries, an even number of samples (eight samples) per sector
are selected, which would violate the HWS. The normalized
harmonic spectrum of the motor-phase voltage is shown in
Fig. 16, from which it is evident that even harmonics occur
(corresponding to 22nd and 26th orders), which are generally
discouraged in electric drive applications.
With the choice of 44 samples per cycle, one would obtain a
fractional number of samples per sector (44/6). The normalized
harmonic spectrum corresponding to this case is shown in
Fig. 17. From Fig. 17, it may be noted that even harmonics
occur in this case also. As the number of samples (44) is
not a multiple of 3, the TPS is also lost. Consequently, the
output would contain a pronounced 45th harmonic (which also
corresponds to the side-band frequency), which is not a zerosequence component despite being a triplen component. Similar

VENUGOPAL REDDY et al.: SVPWM STRATEGIES FOR INDUCTION MOTOR DRIVE WITH WAVEFORM SYMMETRIES

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Fig. 16. Harmonic spectra corresponding to sample number 48.

Fig. 18. Locus of the individual space vectors of (outer circle) inverter-1 and
(inner circle) inverter-2.

Fig. 17. Harmonic spectra corresponding to sample number 44.

results are obtained when the number of samples per cycle is

43, wherein one would obtain very pronounced even harmonics
corresponding to 42nd and 44th orders. This spectrum is not
being presented in the interest of brevity.
The significance of waveform symmetries can also be
demonstrated through other common PWM techniques such as
sine-triangle PWM. It is shown in [24] that the sine-triangle
PWM can easily be implemented by setting Toset = T s/2 in
(6). In other words, with SVPWM, the reference phase voltages
would contain harmonics of triplen order, while they are purely
sinusoidal in the case of sine-triangle PWM.
VI. D ECOUPLED SVPWM S TRATEGY W ITH
P ROPORTIONAL S WITCHING D UTY
It can be reasoned out that the switching power loss Ploss in
an inverter employing space-vector modulation is proportional
to both the dc-link voltage (Vdc ) and the number of samples per
one revolution of the reference voltage space vector (Nsamp ),
which, in turn, is proportional to the switching frequency.
Hence, one may express
Ploss = KVdc Nsamp .

(17)

The constant of proportionality K depends on the operational

parameters of the inverter and the switching times of the
power semiconductor devices, used to constitute the inverter,
as detailed in the next section.
Thus, it would be an advantageous proposition to switch the
inverters with switching frequencies, which are proportional to
their dc-link voltages. In other words, the inverter with higher
dc-link voltage (i.e., with a voltage of 2/3 Vdc ) should be
switched with a lesser frequency, ideally at half of the switching frequency, compared to the one operating with a lower

dc-link voltage (i.e., with a voltage of 1/3 Vdc ). However, the

condition that both inverters be switched with an odd number
of samples in a span of 60 electrical degrees, based on the
constraints of waveform symmetry of the output voltage, rules
out such a possibility. As a consequence, one is constrained to
operate with a ratio of switching frequencies, which is slightly
deviant from the ratio 1 : 2. Thus, in this paper, a ratio of
5 : 9 (i.e., 1 : 1.8) is used to switch the respective inverters.
Consequently, the inverters are respectively operated with a
total of 30 (5 6) and 54 (9 6) samples per cycle. This means
that the angular displacement between successive samples of
inverter-1 is 12 (360 /30), while that of inverter-2 is 6.7
(360 /54). Fig. 18 shows the samples of respective inverters,
wherefrom it is evident that, unlike the previous PWM scheme,
the samples of inverter-1 and inverter-2 are not aligned, except
at the middle of the sectors (0 , 60 , 120 , etc., from the
reference time instant shown in Fig. 18). This misalignment
of samples would create a negligible discrepancy between
the actual reference voltage vector and the vector which is
synthesized in the average sense. In this PWM scheme, the
reference voltage vector having a magnitude of Vsr is divided
in the ratio 2 : 1 for the individual inverters, based only on the
magnitude disregarding the phase. In other words, inverter-1 is
operated with samples which are given by magnitude and angle
as (2/3)|Vsr |0 , (2/3)|Vsr |12 , . . . , (2/3)|Vsr |60 in a
span of 60 . Similarly, inverter-2 is operated with samples
(1/3)|Vsr |0 , (1/3)|Vsr |6.7 , . . . , (1/3)|Vsr |60 in the
same span. Table IV shows the respective angular positions of
the reference vectors of both inverters for all of the samples in
a span of 60 electrical degrees. From the third column of the
table, it may be noted that the maximum angle of misalignment
(denoted by ) between the samples is 10.67 .
The fourth and fifth columns of the table respectively present
the magnitude and phase of the resultant vector (denoted by
Vsr ), produced by the vector addition of the voltage space
vectors produced by individual inverters (denoted by Vsr1 and
Vsr2 ), which is given by

|Vsr
|=

Vsr

|Vsr1 |2 + |Vsr2 |2 + 2|Vsr1 ||Vsr2 | cos

= (Vsr1 + Vsr2 ).

(18)
(19)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

TABLE IV
M AGNITUDE AND A NGULAR P OSITIONS OF THE R EFERENCE
S PACE V ECTORS OF I NVERTER -1 AND I NVERTER -2 IN A
S PAN OF 60 E LECTRICAL D EGREES

Fig. 20. (Top) Simulated waveform of phase-A voltage and (bottom) harmonic spectra corresponding to ma = 0.4.

Fig. 19. Experimentally obtained phase-A pole voltages of inverter-1 and

inverter-2 for (a) ma = 0.4 and (b) overmodulation. Scale: X-axis: 10 ms/div;
Y -axis: 50 V/div.

Substituting Vsr1 = (2/3)Vsr , Vsr2 = (1/3)Vsr , and =

10.670 , one obtains

|Vsr
| = 0.996

Vsr
= 3.550 .

(20)

Equation (20) suggests that the maximum error incurred

in synthesizing the reference vector with the proportionalswitching-duty SVPWM strategy is about 0.4%, with a negligibly small phase discrepancy compared to the equal-duty
SVPWM. Thus, it is justified to employ the principle of decoupled PWM, even though there is a misalignment of samples
for the respective inverters with proportional switching.
Fig. 19 shows the experimentally obtained waveforms of the
pole voltages of both inverters for the modulation indices of
0.4 and overmodulation, respectively. From these waveforms,

it is evident that inverter-1 is operated with a lower switching

frequency compared to inverter-2.
Fig. 20 shows the (top) waveform (simulation result) of
the phase voltage and (bottom) its harmonic spectrum for a
modulation index (ma ) of 0.4. One may conclude, by noting
the spectra shown in Figs. 12 and 20, that the fundamental
component remains the same (a peak value of 80 V) despite
the redistribution of other spectral components.
This vindicates the assertion that the proportional-duty
SVPWM scheme constructs the same space vector as the
one constructed by the equal-duty SVPWM with negligible
deviation.
The motor-phase voltages and the corresponding motorphase currents at no load for the modulation indices (ma ) of
0.4 and overmodulation with proportional-duty SVPWM are
shown in Fig. 21(a) and (b), respectively. Fig. 22 shows the
motor-phase current under loaded conditions for ma = 0.4 in
steps of 2 A.
The dc-link voltages of individual inverters corresponding
to the loaded condition shown in Fig. 22 for ma = 0.4 are
shown in Fig. 23. It may be noted that the dc-link voltages are
maintained in the ratio 2 : 1 when proportional-duty SVPWM is
employed, similar to the case of equal-duty SVPWM (Fig. 15).
Thus, it is demonstrated that the proportional-duty SVPWM
retains the merit of the equal-duty SVPWM, namely, the avoidance of the overcharging of the dc-link capacitor of the inverter
with lower voltage by its counterpart with higher voltage.
Fig. 24 shows the experimentally obtained waveforms of
the motor-phase voltage and current for a three-level inverter
operated with decoupled SVPWM strategy [22], [25] for a
modulation index ma = 0.4. In this case, the dc-link voltages
would be equal and are equal to Vdc /2.

VENUGOPAL REDDY et al.: SVPWM STRATEGIES FOR INDUCTION MOTOR DRIVE WITH WAVEFORM SYMMETRIES

5139

Fig. 25. Percent THD in motor-phase voltage versus ma for decoupled threelevel and four-level equal-duty and four-level proportional-duty schemes.

Fig. 21. Motor-phase voltage and current for (a) ma = 0.4 and (b) overmodulation. Voltage scale: X-axis: 20 ms/div; Y -axis: 100 V/div. Current scale:
X-axis: 10 ms/div; Y -axis:1 A/div.

Fig. 22. Motor-phase current in loaded condition for ma = 0.4. Scale:

X-axis: 10 s/div; Y -axis: 2 A/div.

the corresponding THD for a three-level inverter operated with

the decoupled PWM strategy. It is evident that the proportionalduty SVPWM of four-level inverter renders a lesser harmonic
contamination vis--vis the equal-duty SVPWMs of four-level
inverter and three-level inverter with equal dc-link voltages.
The motor-phase voltages shown in Fig. 13 (for fourlevel equal-duty SVPWM strategy), Fig. 21 (for four-level
proportional-duty SVPWM strategy), and Fig. 24 (for threelevel equal-duty SVPWM strategy with equal dc-link voltages)
are analyzed for their harmonic content, and their normalized
harmonic spectra are shown in Fig. 25. Moreover, the THD in
the motor-phase current is evaluated for these three cases for
a modulation index of 0.4. While the percent THDs of motorphase current of three- and four-level equal-duty strategies yield
comparable results (20% in each case), the percent THD (of
motor-phase current) is better for the four-level inverter with
the proportional-duty PWM strategy (15.5%). The comparison
of switching power losses and the advantage obtained by the
proportional SVPWM strategy with a four-level inverter is
described in the following section.

VII. C OMPARISON OF S WITCHING P OWER L OSS

W ITH THE P ROPOSED PWM S TRATEGIES
Fig. 23. Inverter-1 and inverter-2 dc-link voltages under loaded condition for
ma = 0.4. Voltage scale: X-axis:10 s/div; Y -axis: 50 V/div.

The power loss in a power semiconductor device is fairly

generic, given by the following expression:
Ploss =

Fig. 24. Motor-phase (a) voltage and (b) current for ma = 0.4. Voltage
scale: X-axis: 20 ms/div; Y -axis: 100 V/div. Current scale: X-axis: 20 ms/div;
Y -axis: 1 A/div.

Fig. 25 shows the comparison of equal- and proportionalduty SVPWM strategies on the basis of the total harmonic
distortion (THD) of the motor-phase voltages for different
values of ma , based on 150 harmonic components along with

Vsw Isw (ton + to )fs

.
2

(21)

In (21), Vsw , Isw , ton , to , and fs denote the voltage blocked

by the switch when it is turned off, the current switched through
the device when it is turned on, the turn-on time delay, the
turnoff time delay, and the switching frequency of the device,
respectively.
Realize that fs = fsamp /2 for space-vector modulation,
where fsamp is the sampling frequency which, in turn, is
given by
2
fsamp = ma Nsamp frated .
3

(22)

From (21) and (22), one gets

Ploss = K  (ma Nsamp )

(23)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

where
K =

Vsw Isw (ton + to )frated

.
2 3

From (23), it is evident that the power loss in one semiconductor device is proportional to the product of the modulation
index (ma ) and the number of samples per revolution of the
reference voltage vector for the individual inverters (Nsamp ).
Thus, the total power loss in a given inverter could be estimated
to be six times the power loss incurred in one device. For a given
modulation index (ma ), (23) may be rewritten in terms of the
dc-link voltage of the inverter (Vdc ) and the number of samples
as Ploss = K(Vdc Nsamp ), which is the same as (17).
With the equal-duty SVPWM strategy, both inverters are
switched with 42 samples, while with the proportionalswitching-duty SVPWM, the inverters are switched with 30 and
54 samples, respectively. Thus, the total number of samples
remains the same. However, the fact that the inverter with
higher dc-link voltage is switched with a frequency which is
about half of the one with lower dc-link voltage would lower
the overall switching power loss.
The total switching power loss incurred in the dual-inverter
system is given by
Ploss =

Ploss,1 + Ploss,2 .

(24)

In (24), the symbols Ploss,1 and Ploss,2 denote the power

losses incurred in inverter-1 and inverter-2, respectively.
From (23), the total switching power loss with equal-duty
SVPWM strategy is given by
 
 
2
1
Pequal duty = K
Vdc 42 + K
Vdc 42
3
3
= K Vdc 42.

(25)

The total switching power loss with proportional-duty

SVPWM is given by
 
 
2
1
Pproportional = K
Vdc 30 + K
Vdc 54
3
3
= K Vdc 38.

(26)

From (25) and (26), it is evident that

Pproportional = (19/21) Pequal duty 0.904Pequal duty .
Thus, it is apparent that the switching power loss in the
dual-inverter system with proportional-duty SVPWM results
in an energy saving of about 10% compared to the equal-duty
SVPWM.
VIII. C ONCLUSION
Two decoupled SVPWM strategies, namely, equal- and
proportional-duty SVPWMs, have been described for a fourlevel dual-inverter-fed open-end winding induction motor drive.
Two unequal dc-link voltages, which are in the ratio of 2 : 1, are
used to achieve this objective. The zero-sequence current is not
allowed to flow in this circuit, as two isolated dc power supplies

are employed to feed individual inverters. It is shown that,

with the equal-duty SVPWM strategy, the gating waveforms
of only one inverter need to be generated, from which the
gating waveforms for the other inverter could be deduced. It
is shown experimentally that both of the schemes achieve the
avoidance of overcharging of the dc-link voltage of the inverter
operating with lower dc-link voltage. It is apparent that the
proportional-duty SVPWM accomplishes an energy saving of
about 10% compared to the equal-duty SVPWM, which could
be significant for medium- and high-power applications. Moreover, the proportional-duty SVPWM displays a lesser harmonic
contamination (i.e., a lesser THD) compared to the equal-duty
SVPWM, which would result in lesser iron loss in the motor
and, therefore, an enhanced performance of the overall drive
system.
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5141

Barry Venugopal Reddy (S08) received the

B.Tech. degree in electrical engineering from the
College of Engineering, Jawaharlal Nehru Technological University, Hyderabad, India, in 2001 and
the M.Tech. degree from the National Institute of
Technology, Warangal, India, in 2005, where he is
currently working toward the Ph.D. degree.
His research interests are multilevel inverters,
multilevel pulsewidth modulation switching strategies, and multilevel inversion realized through openend winding induction motor drives.

Veeramraju Tirumala Somasekhar received the

B.Tech. degree from Regional Engineering College
Warangal [presently the National Institute of Technology (NIT)], Warangal, India, in 1988, the M.Tech.
degree with specialization in power electronics from
the Indian Institute of Technology Bombay, Mumbai,
India, in 1990, and the Ph.D. degree from the Indian
Institute of Science, Bangalore, India, in 2003.
He was an R&D Engineer with M/s Perpetual
Power Technologies, Bangalore, and a Senior Engineer with M/s Kirloskar Electric Company, Ltd.,
Mysore, India. In 1993, he joined the Faculty of Electrical Engineering, NIT,
where he is currently serving. His current interests are multilevel inversion with
open-end induction motors, ac drives, and pulsewidth modulation strategies.

Yenduri Kalyan received the B.Tech. degree

from Jawaharlal Nehru Technological University,
Hyderabad, India, in 2007 and the M.Tech. degree
with specialization in power electronics and drives
from the National Institute of Technology, Warangal,
India, in 2009. He is currently working toward the
Ph.D. degree at Advanced Centre for Electronic Systems, Indian Institute of Technology, Kanpur, India.
His research interests include the control of power
electronic converters, electric drives, and renewable
energy.