Features
Compatible with MCS-51
Products
microcomputer which
provides a highly flexible and
4 Kbytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles
applications.
Three-Level Program Memory Lock
8-Bit
Microcontroller
with 4 Kbytes
Description
Flash
AT89C51
Pin Configurations
PQFP/TQFP
(continued)
PDIP/Cerdip
P1.0
1
40
VCC
P1.1
2
39
P0.0 (AD0)
P1.2
3
38
P0.1 (AD1)
P1.3
4
37
P0.2 (AD2)
P1.4
36
P0.3 (AD3)
P1.5
6
35
P0.4 (AD4)
P1.6
7
34
P0.5
(AD5)
P1.7
8
33
P0.6
(AD6)
RST
9
32
P0.7
(AD7)
(RXD) P3.0
10
31
EA
/VPP
(TXD) P3.1
11
30
ALE/
PROG
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD)
P3.0
NC
(TXD)
P3.1
P3.2
INT0
INT1
P3.3
(T0)
P3.4
(T1)
P3.5
(AD0)(AD1)(AD2)(AD3)
1.41.31.21.11.0C
CC
0.00.10.20.3
PPPPPN
V
PPPP
44
42
40
38
36
34
43
41
39
37
35
33
P0.4 (AD4)
32
P0.5 (AD5)
31
P0.6 (AD6)
30
P0.7 (AD7)
29
EA
/VPP
28
NC
27
ALE/PRO
26
PSEN
25
P2.7 (A15)
10
24
P2.6 (A14)
11
23
P2.5 (A13)
12
13
14
15
16
17
18
19
20
21
22
P3.6P3.7TAL2TAL1GNDGNDP2.0P2.1P2.2P2.3P2.4
)XX
)))))
(WR
(RD
(A8(A9(A10(A11(A12
29
PSEN
(I NT 0) P3 .2
12
(
INT1
) P3.3
13
28
P2.7 (A15)
(T0) P3.4
14
27
P2.6 (A14)
(T1) P3.5
15
26
P2.5 (A13)
) P3.6
16
25
P2.4 (A12)
WR
(
RD
) P3.7
17
24
P2.3 (A11)
X TA L 2
18
23
P2.2 (A10)
X TA L 1
19
22
P2.1 (A9)
GND
20
21
P2.0 (A8)
PLCC/LCC
(AD0)(AD1)(AD2)(AD3)
INDEX
P1.4P1.3P1.2P1.1P1.0NC
VCC
P0.0P0.1P0.2P0.3
CORNER
1
44
42
40
P1.5
43 4139
P0.4 (AD4)
P1.6
38
P0.5 (AD5)
P1.7
37
P0.6 (AD6)
RST
10
36
P0.7 (AD7)
(RXD) P3.0
11
35
EA
/VPP
NC
12
34
NC
(TXD) P3.1
13
33
ALE/
PROG
) P3.2
14
32
INT0
PSEN
) P3.3
15
31
P2.7 (A15)
INT1
(T0) P3.4
16
30
P2.6 (A14)
(T1) P3.5
17
19 21
23
25 27
29
P2.5 (A13)
18
20
22
24
26
28
P3.6P3.7TAL2TAL1GNDNCP2.0P2.1P2.2P2.3P2.4
(WR)(RD)
XX
(A8)(A9)(A10)(A11)(A12)
0265E
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
CC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
RAM
PORT 0
PORT 2
FLASH
REGISTER
LATCH
LATCH
STACK
PROGRAM
ACC
ADDRESS
REGISTER
POINTER
REGISTER
TMP2
TMP1
BUFFER
PC
ALU
INCREMENTER
PROGRAM
PSW
COUNTER
PSEN
ALE/PROG
TIMING
INSTRUCTION
DPTR
AND
REGISTER
EA / VPP
CONTROL
RST
PORT 1
PORT 3
LATCH
LATCH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0
- P1.7
P3.0
- P3.7
AT89C51
AT89C51
Port 0 is an 8-bit open drain bidirectional I/O port.
As an output port each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the
Description (Continued)
Port 1
Pin Description
VCC
Supply voltage.
GND
Port 2
Ground.
Port 2 is an 8-bit bidirectional I/O port with internal
Port 0
P3.1
P3.2
P3.3
P3.4
T0
Port Pin
Alternate Functions
P3.0
T1
(timer 1 external input)
ALE/PROG
P3.6
verification.
PSEN
RST
EA/VPP
XTAL2
XTAL2
C1
Oscillator Characteristics
XTAL1
GND
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip RAM and all the spe-cial functions registers remain
unchanged during this
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
AT89C51
AT89C51
is restored to its normal operating level and must
ware inhibits access to internal RAM in this
event, but ac-cess to the port pins is not
VCC
LB1
LB2
LB3
Protection Type
1
U
U
U
No program lock features.
MOVC instructions executed from external program memory are disabled from
2
P
U
U
fetching code bytes from internal memory, EA is sampled and latched on reset, and
3
P
P
U
Same as mode 2, also verify is disabled.
4
P
P
P
Same as mode 3, also external execution is disabled.
The AT89C51 is shipped with either the highvoltage or low-voltage programming mode
enabled. The respective top-side marking and
mode. To program any non-blank byte in the onchip Flash Memory, the entire memory must be
erased using the Chip Erase Mode.
VPP = 12 V
VPP = 5 V
AT89C51
AT89C51
Top-Side Mark
xxxx
xxxx-5
yyww
yyww
(030H)=1EH
(030H)=1EH
Signature
(031H)=51H
(031H)=51H
(032H)=FFH
(032H)=05H
(continued)
indicate READY.
(032H) = 05H indicates 5 V programming
Program Verify: If lock bits LB1 and LB2 have
not been programmed, the programmed code
data can be read back via the address and data
Programming Interface
completion.
ALE/
EA/
Mode
RST
PSEN
VPP
P2.6
P2.7
P3.6
P3.7
PROG
H
L
H/12V
(1)
H
H
H
H
L
H
H
L
L
H
H
Write Lock
Bit - 1
H
L
H/12V
H
H
H
H
Bit - 2
H
L
(2)
H/12V
H
H
L
L
Bit - 3
H
L
H/12V
L
H
L
Chip Erase
H
L
H/12V
H
L
L
L
Read Signature
H
L
H
H
L
L
L
Byte
enable programming.
AT89C51
AT89C51
P2.0
V /V
IH
PP
- P2.3
A0 - A7 ADDR.
4-24 MHz
P0
ALE
P3.6
P2.6
AT89C51
P1
OOOOH/OFFFH
XTAL 1
A8 - A11
SEE FLASH
PROGRAMMING MODES
TABLE
V
P2.7
RST
CC
P3.7
IH
ALE
P3.6
GND
A0 - A7 ADDR.
PSEN
P3.7
+5V
OOOOH/0FFFH
P2.0
- P2.3
A8 - A11
4-24 MHz
P0
PGM
SEE FLASH
PROGRAMMING
DATA
AT89C51
P1
CC
XTAL 2
MODES TABLE
P2.6
PROG
EA
P2.7
XTAL 2
EA
+5V
(USE 10K
IH
PULLUPS)
XTAL 1
GND
PGM
DATA
PSEN
RST
IH
Symbol
Parameter
Min
Max
Units
(1)
VPP
IPP
(1)
1.0
mA
1/tCLCL
Oscillator Frequency
4
24
MHz
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
10
(1)
tGHSL
tGLGH
PROG Width
1
110
tAVQV
48tCLCL
tELQV
48tCLCL
tEHQV
tGHBL
1.0
tWC
2.0
ms
Note:
P1.0
P1.7
PROGRAMMING
VERIFICATION
ADDRESS
ADDRESS
P2.0
P2.3
AVQV
PORT 0
DATA IN
DATA OUT
AVGL
DVGL GHDX
GHAX
ALE/PROG
SHGL
GLGH
GHSL
PP
LOGIC 1
EA/VPP
EHSH
LOGIC 0
EHQZ
ELQV
P2.7
(ENABLE)
GHBL
P3.4
BUSY
(RDY/BSY)
READY
WC
P1.0 - P1.7
P2.0 - P2.3
VERIFICATION
PORT 0
ADDRESS
ADDRESS
ALE/PROG
EA/VPP
AVQV
P2.7
(ENABLE)
DATA IN
P3.4
(RDY/BSY)
DATA OUT
AVGL
t
t
t
DVGL
GHDX
GHAX
LOGIC 0
EHSH
ELQV
SHGL
EHQZ
GLGH
GHBL
LOGIC 1
BUSY
WC
READY
AT89C51
AT89C51
6.6
V
...................OperatingTemperature
-55C to +125C
Storage Temperature......................
-65C to +150C
Voltage on Any Pin
D.C. Characteristics
Symbol
Parameter
Condition
Min
Max
Units
VIL
Input Low Voltage
(Except
EA)
-0.5
0.2 VCC-0.1
V
-0.5
0.2 VCC-0.3
V
VIL1
Input Low Voltage (EA)
VIH
Input High Voltage
(Except XTAL1, RST)
0.2 VCC+0.9
VCC+0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7 VCC
VCC+0.5
V
VOL
(1)
IOL = 1.6 mA
0.45
V
(Ports 1,2,3)
VOL1
(1)
IOL = 3.2 mA
0.45
V
VOH
IOH = -25 A
0.75 VCC
IOH = -10 A
0.9 VCC
VOH1
IOH = -300 A
0.75 VCC
IOH = -80 A
0.9 VCC
IIL
Logical 0 Input Current
VIN = 0.45 V
-50
A
(Ports 1,2,3)
ITL
Logical 1 to 0 Transition
VIN = 2 V
-650
A
ILI
Input Leakage Current
10
A
(Port 0, EA)
RRST
Reset Pulldown Resistor
50
300
CIO
Pin Capacitance
10
pF
20
mA
ICC
5
mA
(2)
VCC = 6 V
100
A
VCC = 3 V
40
A.C. Characteristics
(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all
other outputs = 80 pF)
Symbol
Parameter
12 MHz Oscillator
16 to 24 MHz Oscillator
Units
Min
Max
Min
Max
1/tCLCL
Oscillator Frequency
24
MHz
tLHLL
2tCLCL-40
ns
tAVLL
tCLCL-13
ns
tLLAX
tCLCL-20
ns
tLLIV
233
4tCLCL-65
ns
tLLPL
tCLCL-13
ns
tPLPH
3tCLCL-20
ns
tPLIV
145
3tCLCL-45
ns
tPXIX
ns
tPXIZ
59
tCLCL-10
ns
tPXAV
tCLCL-8
ns
tAVIV
312
5tCLCL-55
ns
tPLAZ
10
10
ns
tRLRH
RD Pulse Width
400
6tCLCL-100
ns
tWLWH
WR Pulse Width
400
6tCLCL-100
ns
tRLDV
252
5tCLCL-90
ns
tRHDX
ns
tRHDZ
97
2tCLCL-28
ns
tLLDV
517
8tCLCL-150
ns
tAVDV
585
9tCLCL-165
ns
tLLWL
tAVWL
Address to RD or WR Low
203
4tCLCL-75
ns
tQVWX
tCLCL-20
ns
tQVWH
7tCLCL-120
ns
tWHQX
tCLCL-20
ns
tRLAZ
0
ns
tWHLH
10
AT89C51
AT89C51
ALE
LHLL
PLPH
AVLL
LLIV
LLPL
PLIV
PSEN
PXAV
PLAZ
LLAX
PXIZ
PORT 0
PXIX
A0 - A7
INSTR IN
A0 - A7
PORT 2
AVIV
A8 - A15
A8 - A15
ALE
LHLL
WHLH
PSEN
LLDV
RLRH
LLWL
RD
AVLL
LLAX
RLDV
RHDZ
RLAZ
PORT 0
RHDX
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
AVWL
PORT 2
AVDV
11
ALE
LHLL
WHLH
PSEN
LLWL
WLWH
WR
LLAX
PORT 0
AVLL
QVWX
QVWH
WHQX
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCLINSTR IN
PORT 2
AVWL
CHCX
CHCX
VCC - 0.5V
CLCH
CHCL
VCC
VCC - 0.1V
0.45V
t
t
CLCX
CLCL
Symbol
Parameter
Min
Max
Units
1/tCLCL
Oscillator Frequency
0
24
MHz
tCLCL
Clock Period
41.6
ns
tCHCX
High Time
15
ns
tCLCX
Low Time
15
ns
tCLCH
Rise Time
20
ns
tCHCL
Fall Time
20
ns
12
AT89C51
AT89C51
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
Units
tXLXL
Serial Port Clock Cycle Time
1.0
12tCLCL
s
tQVXH
Output Data Setup to Clock Rising Edge
700
10tCLCL-133
ns
tXHQX
Output Data Hold After Clock Rising Edge
50
2tCLCL-33
ns
tXHDX
Input Data Hold After Clock Rising Edge
0
ns
tXHDV
Clock Rising Edge to Input Data Valid
700
10tCLCL-133
ns
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
XLXL
CLOCK
QVXH
XHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
OUTPUT DATA
XHDV
XHDX
SET TI
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
INPUT DATA
SET RI
CC
- 0.5V
+ 0.1V
TEST POINTS
- 0.1V
0.2
LOAD
VCC - 0.1V
OL
LOAD
0.45V
Timing Reference
- 0.1V
LOAD
V OL
+ 0.1V
Points
13
Ordering Information
Speed
Power
Ordering Code
Package
Operation Range
(MHz)
Supply
12
5 V 20%
AT89C51-12AC
44A
Commercial
AT89C51-12JC
44J
(0C to 70C)
AT89C51-12PC
40P6
AT89C51-12QC
44Q
AT89C51-12AI
44A
Industrial
AT89C51-12JI
44J
(-40C to 85C)
AT89C51-12PI
40P6
AT89C51-12QI
44Q
AT89C51-12AA
44A
Automotive
AT89C51-12JA
44J
(-40C to 125C)
AT89C51-12PA
40P6
AT89C51-12QA
44Q
5 V 10%
AT89C51-12DM
40D6
Military
AT89C51-12LM
44L
(-55C to 125C)
AT89C51-12DM/883
40D6
Military/883C
AT89C51-12LM/883
44L
Class B, Fully Compliant
(-55C to 125C)
16
5 V 20%
AT89C51-16AC
44A
Commercial
AT89C51-16JC
44J
(0C to 70C)
AT89C51-16PC
40P6
AT89C51-16QC
44Q
AT89C51-16AI
44A
Industrial
AT89C51-16JI
44J
(-40C to 85C)
AT89C51-16PI
40P6
AT89C51-16QI
44Q
AT89C51-16AA
44A
Automotive
AT89C51-16JA
44J
(-40C to 125C)
AT89C51-16PA
40P6
AT89C51-16QA
44Q
20
5 V 20%
AT89C51-20AC
44A
Commercial
AT89C51-20JC
44J
(0C to 70C)
AT89C51-20PC
40P6
AT89C51-20QC
44Q
AT89C51-20AI
44A
Industrial
AT89C51-20JI
44J
(-40C to 85C)
AT89C51-20PI
40P6
AT89C51-20QI
44Q
14
AT89C51
AT89C51
Ordering Information
Speed
Power
Ordering Code
Package
Operation Range
(MHz)
Supply
24
5 V 20%
AT89C51-24AC
44A
Commercial
AT89C51-24JC
44J
(0C to 70C)
AT89C51-24PC
44P6
AT89C51-24QC
44Q
AT89C51-24AI
44A
Industrial
AT89C51-24JI
44J
(-40C to 85C)
AT89C51-24PI
44P6
AT89C51-24QI
44Q
Package Type
44A
44
Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
40D6
40
44J
44
Lead, Plastic J-Leaded Chip Carrier (PLCC)
44L
44
Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
40P6
40
Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44Q
44
Lead, Plastic Gull Wing Quad Flatpack (PQFP)
15
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